1b2f74ec5SSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2b2f74ec5SSameer Pujar /* 3b2f74ec5SSameer Pujar * tegra210_sfc.h - Definitions for Tegra210 SFC driver 4b2f74ec5SSameer Pujar * 5*d900d9a4SSheetal * Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved. 6b2f74ec5SSameer Pujar * 7b2f74ec5SSameer Pujar */ 8b2f74ec5SSameer Pujar 9b2f74ec5SSameer Pujar #ifndef __TEGRA210_SFC_H__ 10b2f74ec5SSameer Pujar #define __TEGRA210_SFC_H__ 11b2f74ec5SSameer Pujar 12b2f74ec5SSameer Pujar /* 13b2f74ec5SSameer Pujar * SFC_RX registers are with respect to XBAR. 14b2f74ec5SSameer Pujar * The data comes from XBAR to SFC. 15b2f74ec5SSameer Pujar */ 16b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_STATUS 0x0c 17b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_INT_STATUS 0x10 18b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_INT_MASK 0x14 19b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_INT_SET 0x18 20b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_INT_CLEAR 0x1c 21b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_CIF_CTRL 0x20 22b2f74ec5SSameer Pujar #define TEGRA210_SFC_RX_FREQ 0x24 23b2f74ec5SSameer Pujar 24b2f74ec5SSameer Pujar /* 25b2f74ec5SSameer Pujar * SFC_TX registers are with respect to XBAR. 26b2f74ec5SSameer Pujar * The data goes out of SFC. 27b2f74ec5SSameer Pujar */ 28b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_STATUS 0x4c 29b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_INT_STATUS 0x50 30b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_INT_MASK 0x54 31b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_INT_SET 0x58 32b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_INT_CLEAR 0x5c 33b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_CIF_CTRL 0x60 34b2f74ec5SSameer Pujar #define TEGRA210_SFC_TX_FREQ 0x64 35b2f74ec5SSameer Pujar 36b2f74ec5SSameer Pujar /* Register offsets from TEGRA210_SFC*_BASE */ 37b2f74ec5SSameer Pujar #define TEGRA210_SFC_ENABLE 0x80 38b2f74ec5SSameer Pujar #define TEGRA210_SFC_SOFT_RESET 0x84 39b2f74ec5SSameer Pujar #define TEGRA210_SFC_CG 0x88 40b2f74ec5SSameer Pujar #define TEGRA210_SFC_STATUS 0x8c 41b2f74ec5SSameer Pujar #define TEGRA210_SFC_INT_STATUS 0x90 42b2f74ec5SSameer Pujar #define TEGRA210_SFC_COEF_RAM 0xbc 43b2f74ec5SSameer Pujar #define TEGRA210_SFC_CFG_RAM_CTRL 0xc0 44b2f74ec5SSameer Pujar #define TEGRA210_SFC_CFG_RAM_DATA 0xc4 45b2f74ec5SSameer Pujar 46b2f74ec5SSameer Pujar /* Fields in TEGRA210_SFC_ENABLE */ 47b2f74ec5SSameer Pujar #define TEGRA210_SFC_EN_SHIFT 0 48b2f74ec5SSameer Pujar #define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT) 49b2f74ec5SSameer Pujar 50*d900d9a4SSheetal #define TEGRA210_SFC_NUM_RATES 13 51b2f74ec5SSameer Pujar 52b2f74ec5SSameer Pujar /* Fields in TEGRA210_SFC_COEF_RAM */ 53b2f74ec5SSameer Pujar #define TEGRA210_SFC_COEF_RAM_EN BIT(0) 54b2f74ec5SSameer Pujar 55b2f74ec5SSameer Pujar #define TEGRA210_SFC_SOFT_RESET_EN BIT(0) 56b2f74ec5SSameer Pujar 57b2f74ec5SSameer Pujar /* Coefficients */ 58b2f74ec5SSameer Pujar #define TEGRA210_SFC_COEF_RAM_DEPTH 64 59b2f74ec5SSameer Pujar #define TEGRA210_SFC_RAM_CTRL_RW_WRITE (1 << 14) 60b2f74ec5SSameer Pujar #define TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN (1 << 13) 61b2f74ec5SSameer Pujar #define TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN (1 << 12) 62b2f74ec5SSameer Pujar 63b2f74ec5SSameer Pujar 64b2f74ec5SSameer Pujar enum tegra210_sfc_path { 65b2f74ec5SSameer Pujar SFC_RX_PATH, 66b2f74ec5SSameer Pujar SFC_TX_PATH, 67b2f74ec5SSameer Pujar SFC_PATHS, 68b2f74ec5SSameer Pujar }; 69b2f74ec5SSameer Pujar 70b2f74ec5SSameer Pujar struct tegra210_sfc { 71b2f74ec5SSameer Pujar unsigned int mono_to_stereo[SFC_PATHS]; 72b2f74ec5SSameer Pujar unsigned int stereo_to_mono[SFC_PATHS]; 73b2f74ec5SSameer Pujar unsigned int srate_out; 74b2f74ec5SSameer Pujar unsigned int srate_in; 75b2f74ec5SSameer Pujar struct regmap *regmap; 76b2f74ec5SSameer Pujar }; 77b2f74ec5SSameer Pujar 78b2f74ec5SSameer Pujar #endif 79