1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * tegra210_peq.h - Definitions for Tegra210 PEQ driver 4 * 5 * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. 6 * 7 */ 8 9 #ifndef __TEGRA210_PEQ_H__ 10 #define __TEGRA210_PEQ_H__ 11 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <sound/soc.h> 15 16 /* Register offsets from PEQ base */ 17 #define TEGRA210_PEQ_SOFT_RESET 0x0 18 #define TEGRA210_PEQ_CG 0x4 19 #define TEGRA210_PEQ_STATUS 0x8 20 #define TEGRA210_PEQ_CFG 0xc 21 #define TEGRA210_PEQ_CFG_RAM_CTRL 0x10 22 #define TEGRA210_PEQ_CFG_RAM_DATA 0x14 23 #define TEGRA210_PEQ_CFG_RAM_SHIFT_CTRL 0x18 24 #define TEGRA210_PEQ_CFG_RAM_SHIFT_DATA 0x1c 25 26 /* Fields in TEGRA210_PEQ_CFG */ 27 #define TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT 2 28 #define TEGRA210_PEQ_CFG_BIQUAD_STAGES_MASK (0xf << TEGRA210_PEQ_CFG_BIQUAD_STAGES_SHIFT) 29 30 #define TEGRA210_PEQ_CFG_MODE_SHIFT 0 31 #define TEGRA210_PEQ_CFG_MODE_MASK (0x1 << TEGRA210_PEQ_CFG_MODE_SHIFT) 32 33 #define TEGRA210_PEQ_RAM_CTRL_RW_READ 0 34 #define TEGRA210_PEQ_RAM_CTRL_RW_WRITE (1 << 14) 35 #define TEGRA210_PEQ_RAM_CTRL_ADDR_INIT_EN (1 << 13) 36 #define TEGRA210_PEQ_RAM_CTRL_SEQ_ACCESS_EN (1 << 12) 37 #define TEGRA210_PEQ_RAM_CTRL_RAM_ADDR_MASK 0x1ff 38 39 /* PEQ register definition ends here */ 40 #define TEGRA210_PEQ_MAX_BIQUAD_STAGES 12 41 42 #define TEGRA210_PEQ_MAX_CHANNELS 8 43 44 #define TEGRA210_PEQ_BIQUAD_INIT_STAGE 5 45 46 #define TEGRA210_PEQ_GAIN_PARAM_SIZE_PER_CH (2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES * 5) 47 #define TEGRA210_PEQ_SHIFT_PARAM_SIZE_PER_CH (2 + TEGRA210_PEQ_MAX_BIQUAD_STAGES) 48 49 int tegra210_peq_regmap_init(struct platform_device *pdev); 50 int tegra210_peq_component_init(struct snd_soc_component *cmpnt); 51 void tegra210_peq_restore(struct regmap *regmap, u32 *biquad_gains, 52 u32 *biquad_shifts); 53 void tegra210_peq_save(struct regmap *regmap, u32 *biquad_gains, 54 u32 *biquad_shifts); 55 56 #endif 57