1*8c8ff982SSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2*8c8ff982SSameer Pujar /* 3*8c8ff982SSameer Pujar * tegra210_dmic.h - Definitions for Tegra210 DMIC driver 4*8c8ff982SSameer Pujar * 5*8c8ff982SSameer Pujar * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6*8c8ff982SSameer Pujar * 7*8c8ff982SSameer Pujar */ 8*8c8ff982SSameer Pujar 9*8c8ff982SSameer Pujar #ifndef __TEGRA210_DMIC_H__ 10*8c8ff982SSameer Pujar #define __TEGRA210_DMIC_H__ 11*8c8ff982SSameer Pujar 12*8c8ff982SSameer Pujar /* Register offsets from DMIC BASE */ 13*8c8ff982SSameer Pujar #define TEGRA210_DMIC_TX_STATUS 0x0c 14*8c8ff982SSameer Pujar #define TEGRA210_DMIC_TX_INT_STATUS 0x10 15*8c8ff982SSameer Pujar #define TEGRA210_DMIC_TX_INT_MASK 0x14 16*8c8ff982SSameer Pujar #define TEGRA210_DMIC_TX_INT_SET 0x18 17*8c8ff982SSameer Pujar #define TEGRA210_DMIC_TX_INT_CLEAR 0x1c 18*8c8ff982SSameer Pujar #define TEGRA210_DMIC_TX_CIF_CTRL 0x20 19*8c8ff982SSameer Pujar #define TEGRA210_DMIC_ENABLE 0x40 20*8c8ff982SSameer Pujar #define TEGRA210_DMIC_SOFT_RESET 0x44 21*8c8ff982SSameer Pujar #define TEGRA210_DMIC_CG 0x48 22*8c8ff982SSameer Pujar #define TEGRA210_DMIC_STATUS 0x4c 23*8c8ff982SSameer Pujar #define TEGRA210_DMIC_INT_STATUS 0x50 24*8c8ff982SSameer Pujar #define TEGRA210_DMIC_CTRL 0x64 25*8c8ff982SSameer Pujar #define TEGRA210_DMIC_DBG_CTRL 0x70 26*8c8ff982SSameer Pujar #define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 0x88 27*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_FILTER_GAIN 0x8c 28*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_0 0x90 29*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_1 0x94 30*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_2 0x98 31*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_3 0x9c 32*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_4 0xa0 33*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_0 0xa4 34*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_1 0xa8 35*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_2 0xac 36*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_3 0xb0 37*8c8ff982SSameer Pujar #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_4 0xb4 38*8c8ff982SSameer Pujar 39*8c8ff982SSameer Pujar /* Fields in TEGRA210_DMIC_CTRL */ 40*8c8ff982SSameer Pujar #define CH_SEL_SHIFT 8 41*8c8ff982SSameer Pujar #define TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT) 42*8c8ff982SSameer Pujar #define LRSEL_POL_SHIFT 4 43*8c8ff982SSameer Pujar #define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT) 44*8c8ff982SSameer Pujar #define OSR_SHIFT 0 45*8c8ff982SSameer Pujar #define TEGRA210_DMIC_CTRL_OSR_MASK (0x3 << OSR_SHIFT) 46*8c8ff982SSameer Pujar 47*8c8ff982SSameer Pujar #define DMIC_OSR_FACTOR 64 48*8c8ff982SSameer Pujar 49*8c8ff982SSameer Pujar #define DEFAULT_GAIN_Q23 0x800000 50*8c8ff982SSameer Pujar 51*8c8ff982SSameer Pujar /* Max boost gain factor used for mixer control */ 52*8c8ff982SSameer Pujar #define MAX_BOOST_GAIN 25599 53*8c8ff982SSameer Pujar 54*8c8ff982SSameer Pujar enum tegra_dmic_ch_select { 55*8c8ff982SSameer Pujar DMIC_CH_SELECT_LEFT, 56*8c8ff982SSameer Pujar DMIC_CH_SELECT_RIGHT, 57*8c8ff982SSameer Pujar DMIC_CH_SELECT_STEREO, 58*8c8ff982SSameer Pujar }; 59*8c8ff982SSameer Pujar 60*8c8ff982SSameer Pujar enum tegra_dmic_osr { 61*8c8ff982SSameer Pujar DMIC_OSR_64, 62*8c8ff982SSameer Pujar DMIC_OSR_128, 63*8c8ff982SSameer Pujar DMIC_OSR_256, 64*8c8ff982SSameer Pujar }; 65*8c8ff982SSameer Pujar 66*8c8ff982SSameer Pujar enum tegra_dmic_lrsel { 67*8c8ff982SSameer Pujar DMIC_LRSEL_LEFT, 68*8c8ff982SSameer Pujar DMIC_LRSEL_RIGHT, 69*8c8ff982SSameer Pujar }; 70*8c8ff982SSameer Pujar 71*8c8ff982SSameer Pujar struct tegra210_dmic { 72*8c8ff982SSameer Pujar struct clk *clk_dmic; 73*8c8ff982SSameer Pujar struct regmap *regmap; 74*8c8ff982SSameer Pujar unsigned int mono_to_stereo; 75*8c8ff982SSameer Pujar unsigned int stereo_to_mono; 76*8c8ff982SSameer Pujar unsigned int boost_gain; 77*8c8ff982SSameer Pujar unsigned int ch_select; 78*8c8ff982SSameer Pujar unsigned int osr_val; 79*8c8ff982SSameer Pujar unsigned int lrsel; 80*8c8ff982SSameer Pujar }; 81*8c8ff982SSameer Pujar 82*8c8ff982SSameer Pujar #endif 83