1*a99ab6f3SSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2*a99ab6f3SSameer Pujar /* 3*a99ab6f3SSameer Pujar * tegra210_adx.h - Definitions for Tegra210 ADX driver 4*a99ab6f3SSameer Pujar * 5*a99ab6f3SSameer Pujar * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. 6*a99ab6f3SSameer Pujar * 7*a99ab6f3SSameer Pujar */ 8*a99ab6f3SSameer Pujar 9*a99ab6f3SSameer Pujar #ifndef __TEGRA210_ADX_H__ 10*a99ab6f3SSameer Pujar #define __TEGRA210_ADX_H__ 11*a99ab6f3SSameer Pujar 12*a99ab6f3SSameer Pujar /* Register offsets from TEGRA210_ADX*_BASE */ 13*a99ab6f3SSameer Pujar #define TEGRA210_ADX_RX_STATUS 0x0c 14*a99ab6f3SSameer Pujar #define TEGRA210_ADX_RX_INT_STATUS 0x10 15*a99ab6f3SSameer Pujar #define TEGRA210_ADX_RX_INT_MASK 0x14 16*a99ab6f3SSameer Pujar #define TEGRA210_ADX_RX_INT_SET 0x18 17*a99ab6f3SSameer Pujar #define TEGRA210_ADX_RX_INT_CLEAR 0x1c 18*a99ab6f3SSameer Pujar #define TEGRA210_ADX_RX_CIF_CTRL 0x20 19*a99ab6f3SSameer Pujar #define TEGRA210_ADX_TX_STATUS 0x4c 20*a99ab6f3SSameer Pujar #define TEGRA210_ADX_TX_INT_STATUS 0x50 21*a99ab6f3SSameer Pujar #define TEGRA210_ADX_TX_INT_MASK 0x54 22*a99ab6f3SSameer Pujar #define TEGRA210_ADX_TX_INT_SET 0x58 23*a99ab6f3SSameer Pujar #define TEGRA210_ADX_TX_INT_CLEAR 0x5c 24*a99ab6f3SSameer Pujar #define TEGRA210_ADX_TX1_CIF_CTRL 0x60 25*a99ab6f3SSameer Pujar #define TEGRA210_ADX_TX2_CIF_CTRL 0x64 26*a99ab6f3SSameer Pujar #define TEGRA210_ADX_TX3_CIF_CTRL 0x68 27*a99ab6f3SSameer Pujar #define TEGRA210_ADX_TX4_CIF_CTRL 0x6c 28*a99ab6f3SSameer Pujar #define TEGRA210_ADX_ENABLE 0x80 29*a99ab6f3SSameer Pujar #define TEGRA210_ADX_SOFT_RESET 0x84 30*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CG 0x88 31*a99ab6f3SSameer Pujar #define TEGRA210_ADX_STATUS 0x8c 32*a99ab6f3SSameer Pujar #define TEGRA210_ADX_INT_STATUS 0x90 33*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CTRL 0xa4 34*a99ab6f3SSameer Pujar #define TEGRA210_ADX_IN_BYTE_EN0 0xa8 35*a99ab6f3SSameer Pujar #define TEGRA210_ADX_IN_BYTE_EN1 0xac 36*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CFG_RAM_CTRL 0xb8 37*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CFG_RAM_DATA 0xbc 38*a99ab6f3SSameer Pujar 39*a99ab6f3SSameer Pujar /* Fields in TEGRA210_ADX_ENABLE */ 40*a99ab6f3SSameer Pujar #define TEGRA210_ADX_ENABLE_SHIFT 0 41*a99ab6f3SSameer Pujar 42*a99ab6f3SSameer Pujar /* Fields in TEGRA210_ADX_CFG_RAM_CTRL */ 43*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT 0 44*a99ab6f3SSameer Pujar 45*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT 14 46*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT) 47*a99ab6f3SSameer Pujar 48*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13 49*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT) 50*a99ab6f3SSameer Pujar 51*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12 52*a99ab6f3SSameer Pujar #define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT) 53*a99ab6f3SSameer Pujar 54*a99ab6f3SSameer Pujar /* Fields in TEGRA210_ADX_SOFT_RESET */ 55*a99ab6f3SSameer Pujar #define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 0 56*a99ab6f3SSameer Pujar #define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) 57*a99ab6f3SSameer Pujar #define TEGRA210_ADX_SOFT_RESET_SOFT_EN (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) 58*a99ab6f3SSameer Pujar #define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) 59*a99ab6f3SSameer Pujar 60*a99ab6f3SSameer Pujar #define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4 61*a99ab6f3SSameer Pujar #define TEGRA210_ADX_RAM_DEPTH 16 62*a99ab6f3SSameer Pujar #define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6 63*a99ab6f3SSameer Pujar #define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2 64*a99ab6f3SSameer Pujar #define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0 65*a99ab6f3SSameer Pujar 66*a99ab6f3SSameer Pujar struct tegra210_adx { 67*a99ab6f3SSameer Pujar struct regmap *regmap; 68*a99ab6f3SSameer Pujar unsigned int map[TEGRA210_ADX_RAM_DEPTH]; 69*a99ab6f3SSameer Pujar unsigned int byte_mask[2]; 70*a99ab6f3SSameer Pujar }; 71*a99ab6f3SSameer Pujar 72*a99ab6f3SSameer Pujar #endif 73