1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This driver supports the digital controls for the internal codec 4 * found in Allwinner's A33 SoCs. 5 * 6 * (C) Copyright 2010-2016 7 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com> 8 * huangxin <huangxin@Reuuimllatech.com> 9 * Mylène Josserand <mylene.josserand@free-electrons.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/log2.h> 20 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/soc-dapm.h> 24 25 #define SUN8I_SYSCLK_CTL 0x00c 26 #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 27 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL 9 28 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC 8 29 #define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3 30 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0 31 #define SUN8I_MOD_CLK_ENA 0x010 32 #define SUN8I_MOD_CLK_ENA_AIF1 15 33 #define SUN8I_MOD_CLK_ENA_ADC 3 34 #define SUN8I_MOD_CLK_ENA_DAC 2 35 #define SUN8I_MOD_RST_CTL 0x014 36 #define SUN8I_MOD_RST_CTL_AIF1 15 37 #define SUN8I_MOD_RST_CTL_ADC 3 38 #define SUN8I_MOD_RST_CTL_DAC 2 39 #define SUN8I_SYS_SR_CTRL 0x018 40 #define SUN8I_SYS_SR_CTRL_AIF1_FS 12 41 #define SUN8I_SYS_SR_CTRL_AIF2_FS 8 42 #define SUN8I_AIF1CLK_CTRL 0x040 43 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 44 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14 45 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13 46 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 47 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 48 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 49 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) 50 #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 51 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 52 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 53 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 54 #define SUN8I_AIF1_DACDAT_CTRL 0x048 55 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 56 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 57 #define SUN8I_AIF1_MXR_SRC 0x04c 58 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 59 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 60 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL 13 61 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR 12 62 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11 63 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 64 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 65 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8 66 #define SUN8I_ADC_DIG_CTRL 0x100 67 #define SUN8I_ADC_DIG_CTRL_ENAD 15 68 #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 69 #define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1 70 #define SUN8I_DAC_DIG_CTRL 0x120 71 #define SUN8I_DAC_DIG_CTRL_ENDA 15 72 #define SUN8I_DAC_MXR_SRC 0x130 73 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15 74 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14 75 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13 76 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12 77 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11 78 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10 79 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 80 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8 81 82 #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) 83 #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) 84 #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) 85 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) 86 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) 87 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) 88 89 struct sun8i_codec_quirks { 90 bool legacy_widgets : 1; 91 bool lrck_inversion : 1; 92 }; 93 94 struct sun8i_codec { 95 struct regmap *regmap; 96 struct clk *clk_module; 97 struct clk *clk_bus; 98 const struct sun8i_codec_quirks *quirks; 99 }; 100 101 static int sun8i_codec_runtime_resume(struct device *dev) 102 { 103 struct sun8i_codec *scodec = dev_get_drvdata(dev); 104 int ret; 105 106 ret = clk_prepare_enable(scodec->clk_module); 107 if (ret) { 108 dev_err(dev, "Failed to enable the module clock\n"); 109 return ret; 110 } 111 112 ret = clk_prepare_enable(scodec->clk_bus); 113 if (ret) { 114 dev_err(dev, "Failed to enable the bus clock\n"); 115 goto err_disable_modclk; 116 } 117 118 regcache_cache_only(scodec->regmap, false); 119 120 ret = regcache_sync(scodec->regmap); 121 if (ret) { 122 dev_err(dev, "Failed to sync regmap cache\n"); 123 goto err_disable_clk; 124 } 125 126 return 0; 127 128 err_disable_clk: 129 clk_disable_unprepare(scodec->clk_bus); 130 131 err_disable_modclk: 132 clk_disable_unprepare(scodec->clk_module); 133 134 return ret; 135 } 136 137 static int sun8i_codec_runtime_suspend(struct device *dev) 138 { 139 struct sun8i_codec *scodec = dev_get_drvdata(dev); 140 141 regcache_cache_only(scodec->regmap, true); 142 regcache_mark_dirty(scodec->regmap); 143 144 clk_disable_unprepare(scodec->clk_module); 145 clk_disable_unprepare(scodec->clk_bus); 146 147 return 0; 148 } 149 150 static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) 151 { 152 unsigned int rate = params_rate(params); 153 154 switch (rate) { 155 case 8000: 156 case 7350: 157 return 0x0; 158 case 11025: 159 return 0x1; 160 case 12000: 161 return 0x2; 162 case 16000: 163 return 0x3; 164 case 22050: 165 return 0x4; 166 case 24000: 167 return 0x5; 168 case 32000: 169 return 0x6; 170 case 44100: 171 return 0x7; 172 case 48000: 173 return 0x8; 174 case 96000: 175 return 0x9; 176 case 192000: 177 return 0xa; 178 default: 179 return -EINVAL; 180 } 181 } 182 183 static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 184 { 185 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); 186 u32 value; 187 188 /* clock masters */ 189 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 190 case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ 191 value = 0x1; 192 break; 193 case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */ 194 value = 0x0; 195 break; 196 default: 197 return -EINVAL; 198 } 199 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, 200 BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD), 201 value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD); 202 203 /* clock inversion */ 204 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 205 case SND_SOC_DAIFMT_NB_NF: /* Normal */ 206 value = 0x0; 207 break; 208 case SND_SOC_DAIFMT_IB_IF: /* Inversion */ 209 value = 0x1; 210 break; 211 default: 212 return -EINVAL; 213 } 214 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, 215 BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV), 216 value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV); 217 218 /* 219 * It appears that the DAI and the codec in the A33 SoC don't 220 * share the same polarity for the LRCK signal when they mean 221 * 'normal' and 'inverted' in the datasheet. 222 * 223 * Since the DAI here is our regular i2s driver that have been 224 * tested with way more codecs than just this one, it means 225 * that the codec probably gets it backward, and we have to 226 * invert the value here. 227 */ 228 value ^= scodec->quirks->lrck_inversion; 229 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, 230 BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV), 231 value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV); 232 233 /* DAI format */ 234 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 235 case SND_SOC_DAIFMT_I2S: 236 value = 0x0; 237 break; 238 case SND_SOC_DAIFMT_LEFT_J: 239 value = 0x1; 240 break; 241 case SND_SOC_DAIFMT_RIGHT_J: 242 value = 0x2; 243 break; 244 case SND_SOC_DAIFMT_DSP_A: 245 case SND_SOC_DAIFMT_DSP_B: 246 value = 0x3; 247 break; 248 default: 249 return -EINVAL; 250 } 251 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, 252 SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, 253 value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT); 254 255 return 0; 256 } 257 258 struct sun8i_codec_clk_div { 259 u8 div; 260 u8 val; 261 }; 262 263 static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = { 264 { .div = 1, .val = 0 }, 265 { .div = 2, .val = 1 }, 266 { .div = 4, .val = 2 }, 267 { .div = 6, .val = 3 }, 268 { .div = 8, .val = 4 }, 269 { .div = 12, .val = 5 }, 270 { .div = 16, .val = 6 }, 271 { .div = 24, .val = 7 }, 272 { .div = 32, .val = 8 }, 273 { .div = 48, .val = 9 }, 274 { .div = 64, .val = 10 }, 275 { .div = 96, .val = 11 }, 276 { .div = 128, .val = 12 }, 277 { .div = 192, .val = 13 }, 278 }; 279 280 static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec, 281 unsigned int rate, 282 unsigned int word_size) 283 { 284 unsigned long clk_rate = clk_get_rate(scodec->clk_module); 285 unsigned int div = clk_rate / rate / word_size / 2; 286 unsigned int best_val = 0, best_diff = ~0; 287 int i; 288 289 for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) { 290 const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i]; 291 unsigned int diff = abs(bdiv->div - div); 292 293 if (diff < best_diff) { 294 best_diff = diff; 295 best_val = bdiv->val; 296 } 297 } 298 299 return best_val; 300 } 301 302 static int sun8i_codec_get_lrck_div(unsigned int channels, 303 unsigned int word_size) 304 { 305 unsigned int div = word_size * channels; 306 307 if (div < 16 || div > 256) 308 return -EINVAL; 309 310 return ilog2(div) - 4; 311 } 312 313 static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, 314 struct snd_pcm_hw_params *params, 315 struct snd_soc_dai *dai) 316 { 317 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); 318 int sample_rate, lrck_div; 319 u8 bclk_div; 320 321 /* 322 * The CPU DAI handles only a sample of 16 bits. Configure the 323 * codec to handle this type of sample resolution. 324 */ 325 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, 326 SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, 327 SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16); 328 329 bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16); 330 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, 331 SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, 332 bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); 333 334 lrck_div = sun8i_codec_get_lrck_div(params_channels(params), 335 params_physical_width(params)); 336 if (lrck_div < 0) 337 return lrck_div; 338 339 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, 340 SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, 341 lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV); 342 343 sample_rate = sun8i_codec_get_hw_rate(params); 344 if (sample_rate < 0) 345 return sample_rate; 346 347 regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, 348 SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, 349 sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); 350 regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, 351 SUN8I_SYS_SR_CTRL_AIF2_FS_MASK, 352 sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS); 353 354 return 0; 355 } 356 357 static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { 358 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", 359 SUN8I_DAC_MXR_SRC, 360 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, 361 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), 362 SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", 363 SUN8I_DAC_MXR_SRC, 364 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, 365 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), 366 SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, 367 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, 368 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), 369 SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, 370 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, 371 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), 372 }; 373 374 static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = { 375 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", 376 SUN8I_AIF1_MXR_SRC, 377 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, 378 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), 379 SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, 380 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, 381 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), 382 SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", 383 SUN8I_AIF1_MXR_SRC, 384 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, 385 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), 386 SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", 387 SUN8I_AIF1_MXR_SRC, 388 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, 389 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), 390 }; 391 392 static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { 393 /* Digital parts of the DACs and ADC */ 394 SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 395 0, NULL, 0), 396 SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, 397 0, NULL, 0), 398 399 /* AIF "DAC" Inputs */ 400 SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, 401 SUN8I_AIF1_DACDAT_CTRL, 402 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), 403 SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 0, 404 SUN8I_AIF1_DACDAT_CTRL, 405 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), 406 407 /* AIF "ADC" Outputs */ 408 SND_SOC_DAPM_AIF_IN("AIF1 AD0L", "Capture", 0, 409 SUN8I_AIF1_ADCDAT_CTRL, 410 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), 411 SND_SOC_DAPM_AIF_IN("AIF1 AD0R", "Capture", 0, 412 SUN8I_AIF1_ADCDAT_CTRL, 413 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), 414 415 /* ADC Inputs (connected to analog codec DAPM context) */ 416 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), 417 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 418 419 /* DAC Outputs (connected to analog codec DAPM context) */ 420 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 421 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 422 423 /* DAC and ADC Mixers */ 424 SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, 425 sun8i_dac_mixer_controls), 426 SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0, 427 sun8i_dac_mixer_controls), 428 SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0, 429 sun8i_input_mixer_controls), 430 SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0, 431 sun8i_input_mixer_controls), 432 433 /* Clocks */ 434 SND_SOC_DAPM_SUPPLY("MODCLK AIF1", SUN8I_MOD_CLK_ENA, 435 SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), 436 SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, 437 SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), 438 SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA, 439 SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), 440 SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL, 441 SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), 442 SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL, 443 SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), 444 445 SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL, 446 SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0), 447 /* Inversion as 0=AIF1, 1=AIF2 */ 448 SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL, 449 SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0), 450 451 /* Module reset */ 452 SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL, 453 SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), 454 SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, 455 SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), 456 SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, 457 SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), 458 }; 459 460 static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { 461 /* Clock Routes */ 462 { "AIF1", NULL, "SYSCLK AIF1" }, 463 { "AIF1 PLL", NULL, "AIF1" }, 464 { "SYSCLK", NULL, "AIF1 PLL" }, 465 466 { "RST AIF1", NULL, "SYSCLK" }, 467 { "MODCLK AIF1", NULL, "RST AIF1" }, 468 { "AIF1 AD0L", NULL, "MODCLK AIF1" }, 469 { "AIF1 AD0R", NULL, "MODCLK AIF1" }, 470 { "AIF1 DA0L", NULL, "MODCLK AIF1" }, 471 { "AIF1 DA0R", NULL, "MODCLK AIF1" }, 472 473 { "RST DAC", NULL, "SYSCLK" }, 474 { "MODCLK DAC", NULL, "RST DAC" }, 475 { "DAC", NULL, "MODCLK DAC" }, 476 { "DACL", NULL, "DAC" }, 477 { "DACR", NULL, "DAC" }, 478 479 { "RST ADC", NULL, "SYSCLK" }, 480 { "MODCLK ADC", NULL, "RST ADC" }, 481 { "ADC", NULL, "MODCLK ADC" }, 482 { "ADCL", NULL, "ADC" }, 483 { "ADCR", NULL, "ADC" }, 484 485 /* DAC Routes */ 486 { "DACL", NULL, "Left Digital DAC Mixer" }, 487 { "DACR", NULL, "Right Digital DAC Mixer" }, 488 489 /* DAC Mixer Routes */ 490 { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L" }, 491 { "Left Digital DAC Mixer", "ADC Digital DAC Playback Switch", "ADCL" }, 492 493 { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R" }, 494 { "Right Digital DAC Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, 495 496 /* ADC Routes */ 497 { "AIF1 AD0L", NULL, "Left Digital ADC Mixer" }, 498 { "AIF1 AD0R", NULL, "Right Digital ADC Mixer" }, 499 500 /* ADC Mixer Routes */ 501 { "Left Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L" }, 502 { "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" }, 503 504 { "Right Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R" }, 505 { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" }, 506 }; 507 508 static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = { 509 /* Legacy ADC Inputs (connected to analog codec DAPM context) */ 510 SND_SOC_DAPM_ADC("AIF1 Slot 0 Left ADC", NULL, SND_SOC_NOPM, 0, 0), 511 SND_SOC_DAPM_ADC("AIF1 Slot 0 Right ADC", NULL, SND_SOC_NOPM, 0, 0), 512 513 /* Legacy DAC Outputs (connected to analog codec DAPM context) */ 514 SND_SOC_DAPM_DAC("AIF1 Slot 0 Left", NULL, SND_SOC_NOPM, 0, 0), 515 SND_SOC_DAPM_DAC("AIF1 Slot 0 Right", NULL, SND_SOC_NOPM, 0, 0), 516 }; 517 518 static const struct snd_soc_dapm_route sun8i_codec_legacy_routes[] = { 519 /* Legacy ADC Routes */ 520 { "ADCL", NULL, "AIF1 Slot 0 Left ADC" }, 521 { "ADCR", NULL, "AIF1 Slot 0 Right ADC" }, 522 523 /* Legacy DAC Routes */ 524 { "AIF1 Slot 0 Left", NULL, "DACL" }, 525 { "AIF1 Slot 0 Right", NULL, "DACR" }, 526 }; 527 528 static int sun8i_codec_component_probe(struct snd_soc_component *component) 529 { 530 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 531 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); 532 int ret; 533 534 /* Add widgets for backward compatibility with old device trees. */ 535 if (scodec->quirks->legacy_widgets) { 536 ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets, 537 ARRAY_SIZE(sun8i_codec_legacy_widgets)); 538 if (ret) 539 return ret; 540 541 ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_legacy_routes, 542 ARRAY_SIZE(sun8i_codec_legacy_routes)); 543 if (ret) 544 return ret; 545 } 546 547 return 0; 548 } 549 550 static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { 551 .hw_params = sun8i_codec_hw_params, 552 .set_fmt = sun8i_set_fmt, 553 }; 554 555 static struct snd_soc_dai_driver sun8i_codec_dai = { 556 .name = "sun8i", 557 /* playback capabilities */ 558 .playback = { 559 .stream_name = "Playback", 560 .channels_min = 1, 561 .channels_max = 2, 562 .rates = SNDRV_PCM_RATE_8000_192000, 563 .formats = SNDRV_PCM_FMTBIT_S16_LE, 564 }, 565 /* capture capabilities */ 566 .capture = { 567 .stream_name = "Capture", 568 .channels_min = 1, 569 .channels_max = 2, 570 .rates = SNDRV_PCM_RATE_8000_192000, 571 .formats = SNDRV_PCM_FMTBIT_S16_LE, 572 .sig_bits = 24, 573 }, 574 /* pcm operations */ 575 .ops = &sun8i_codec_dai_ops, 576 }; 577 578 static const struct snd_soc_component_driver sun8i_soc_component = { 579 .dapm_widgets = sun8i_codec_dapm_widgets, 580 .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), 581 .dapm_routes = sun8i_codec_dapm_routes, 582 .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes), 583 .probe = sun8i_codec_component_probe, 584 .idle_bias_on = 1, 585 .use_pmdown_time = 1, 586 .endianness = 1, 587 .non_legacy_dai_naming = 1, 588 }; 589 590 static const struct regmap_config sun8i_codec_regmap_config = { 591 .reg_bits = 32, 592 .reg_stride = 4, 593 .val_bits = 32, 594 .max_register = SUN8I_DAC_MXR_SRC, 595 596 .cache_type = REGCACHE_FLAT, 597 }; 598 599 static int sun8i_codec_probe(struct platform_device *pdev) 600 { 601 struct sun8i_codec *scodec; 602 void __iomem *base; 603 int ret; 604 605 scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL); 606 if (!scodec) 607 return -ENOMEM; 608 609 scodec->clk_module = devm_clk_get(&pdev->dev, "mod"); 610 if (IS_ERR(scodec->clk_module)) { 611 dev_err(&pdev->dev, "Failed to get the module clock\n"); 612 return PTR_ERR(scodec->clk_module); 613 } 614 615 scodec->clk_bus = devm_clk_get(&pdev->dev, "bus"); 616 if (IS_ERR(scodec->clk_bus)) { 617 dev_err(&pdev->dev, "Failed to get the bus clock\n"); 618 return PTR_ERR(scodec->clk_bus); 619 } 620 621 base = devm_platform_ioremap_resource(pdev, 0); 622 if (IS_ERR(base)) { 623 dev_err(&pdev->dev, "Failed to map the registers\n"); 624 return PTR_ERR(base); 625 } 626 627 scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, 628 &sun8i_codec_regmap_config); 629 if (IS_ERR(scodec->regmap)) { 630 dev_err(&pdev->dev, "Failed to create our regmap\n"); 631 return PTR_ERR(scodec->regmap); 632 } 633 634 scodec->quirks = of_device_get_match_data(&pdev->dev); 635 636 platform_set_drvdata(pdev, scodec); 637 638 pm_runtime_enable(&pdev->dev); 639 if (!pm_runtime_enabled(&pdev->dev)) { 640 ret = sun8i_codec_runtime_resume(&pdev->dev); 641 if (ret) 642 goto err_pm_disable; 643 } 644 645 ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component, 646 &sun8i_codec_dai, 1); 647 if (ret) { 648 dev_err(&pdev->dev, "Failed to register codec\n"); 649 goto err_suspend; 650 } 651 652 return ret; 653 654 err_suspend: 655 if (!pm_runtime_status_suspended(&pdev->dev)) 656 sun8i_codec_runtime_suspend(&pdev->dev); 657 658 err_pm_disable: 659 pm_runtime_disable(&pdev->dev); 660 661 return ret; 662 } 663 664 static int sun8i_codec_remove(struct platform_device *pdev) 665 { 666 pm_runtime_disable(&pdev->dev); 667 if (!pm_runtime_status_suspended(&pdev->dev)) 668 sun8i_codec_runtime_suspend(&pdev->dev); 669 670 return 0; 671 } 672 673 static const struct sun8i_codec_quirks sun8i_a33_quirks = { 674 .legacy_widgets = true, 675 .lrck_inversion = true, 676 }; 677 678 static const struct sun8i_codec_quirks sun50i_a64_quirks = { 679 }; 680 681 static const struct of_device_id sun8i_codec_of_match[] = { 682 { .compatible = "allwinner,sun8i-a33-codec", .data = &sun8i_a33_quirks }, 683 { .compatible = "allwinner,sun50i-a64-codec", .data = &sun50i_a64_quirks }, 684 {} 685 }; 686 MODULE_DEVICE_TABLE(of, sun8i_codec_of_match); 687 688 static const struct dev_pm_ops sun8i_codec_pm_ops = { 689 SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend, 690 sun8i_codec_runtime_resume, NULL) 691 }; 692 693 static struct platform_driver sun8i_codec_driver = { 694 .driver = { 695 .name = "sun8i-codec", 696 .of_match_table = sun8i_codec_of_match, 697 .pm = &sun8i_codec_pm_ops, 698 }, 699 .probe = sun8i_codec_probe, 700 .remove = sun8i_codec_remove, 701 }; 702 module_platform_driver(sun8i_codec_driver); 703 704 MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver"); 705 MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>"); 706 MODULE_LICENSE("GPL"); 707 MODULE_ALIAS("platform:sun8i-codec"); 708