1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Andrea Venturi 4 * Andrea Venturi <be17068@iperbole.bo.it> 5 * 6 * Copyright (C) 2016 Maxime Ripard 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/dmaengine.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/soc-dai.h> 23 24 #define SUN4I_I2S_CTRL_REG 0x00 25 #define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8) 26 #define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo)) 27 #define SUN4I_I2S_CTRL_MODE_MASK BIT(5) 28 #define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5) 29 #define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5) 30 #define SUN4I_I2S_CTRL_TX_EN BIT(2) 31 #define SUN4I_I2S_CTRL_RX_EN BIT(1) 32 #define SUN4I_I2S_CTRL_GL_EN BIT(0) 33 34 #define SUN4I_I2S_FMT0_REG 0x04 35 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7) 36 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7) 37 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7) 38 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6) 39 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6) 40 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6) 41 #define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4) 42 #define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4) 43 #define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2) 44 #define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2) 45 #define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0) 46 #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0) 47 #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0) 48 #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) 49 50 #define SUN4I_I2S_FMT1_REG 0x08 51 #define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8) 52 #define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8) 53 54 #define SUN4I_I2S_FIFO_TX_REG 0x0c 55 #define SUN4I_I2S_FIFO_RX_REG 0x10 56 57 #define SUN4I_I2S_FIFO_CTRL_REG 0x14 58 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25) 59 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24) 60 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2) 61 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2) 62 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0) 63 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode) 64 65 #define SUN4I_I2S_FIFO_STA_REG 0x18 66 67 #define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c 68 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7) 69 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3) 70 71 #define SUN4I_I2S_INT_STA_REG 0x20 72 73 #define SUN4I_I2S_CLK_DIV_REG 0x24 74 #define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7) 75 #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4) 76 #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4) 77 #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0) 78 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0) 79 80 #define SUN4I_I2S_TX_CNT_REG 0x28 81 #define SUN4I_I2S_RX_CNT_REG 0x2c 82 83 #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 84 #define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0) 85 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0) 86 87 #define SUN4I_I2S_TX_CHAN_MAP_REG 0x34 88 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2)) 89 90 #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38 91 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c 92 93 /* Defines required for sun8i-h3 support */ 94 #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) 95 #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17) 96 97 #define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4) 98 #define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4) 99 #define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4) 100 #define SUN8I_I2S_CTRL_MODE_PCM (0 << 4) 101 102 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19) 103 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 19) 104 #define SUN8I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 19) 105 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) 106 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8) 107 #define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7) 108 #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) 109 #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7) 110 111 #define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5, 4) 112 #define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4) 113 114 #define SUN8I_I2S_INT_STA_REG 0x0c 115 #define SUN8I_I2S_FIFO_TX_REG 0x20 116 117 #define SUN8I_I2S_CHAN_CFG_REG 0x30 118 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(7, 4) 119 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4) 120 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(3, 0) 121 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1) 122 123 #define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 124 #define SUN8I_I2S_TX_CHAN_SEL_REG 0x34 125 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12) 126 #define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) 127 #define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) 128 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4) 129 130 #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 131 #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 132 133 /* Defines required for sun50i-h6 support */ 134 #define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20) 135 #define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20) 136 #define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16) 137 #define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16) 138 #define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0) 139 #define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1)) 140 141 #define SUN50I_H6_I2S_TX_CHAN_SEL_REG(pin) (0x34 + 4 * (pin)) 142 #define SUN50I_H6_I2S_TX_CHAN_MAP0_REG(pin) (0x44 + 8 * (pin)) 143 #define SUN50I_H6_I2S_TX_CHAN_MAP1_REG(pin) (0x48 + 8 * (pin)) 144 145 #define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64 146 #define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68 147 #define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C 148 149 #define SUN50I_R329_I2S_RX_CHAN_MAP0_REG 0x68 150 #define SUN50I_R329_I2S_RX_CHAN_MAP1_REG 0x6c 151 #define SUN50I_R329_I2S_RX_CHAN_MAP2_REG 0x70 152 #define SUN50I_R329_I2S_RX_CHAN_MAP3_REG 0x74 153 154 struct sun4i_i2s; 155 156 /** 157 * struct sun4i_i2s_quirks - Differences between SoC variants. 158 * @has_reset: SoC needs reset deasserted. 159 * @pcm_formats: available PCM formats. 160 * @reg_offset_txdata: offset of the tx fifo. 161 * @sun4i_i2s_regmap: regmap config to use. 162 * @field_clkdiv_mclk_en: regmap field to enable mclk output. 163 * @field_fmt_wss: regmap field to set word select size. 164 * @field_fmt_sr: regmap field to set sample resolution. 165 * @num_din_pins: input pins 166 * @num_dout_pins: output pins (currently set but unused) 167 * @bclk_dividers: bit clock dividers array 168 * @num_bclk_dividers: number of bit clock dividers 169 * @mclk_dividers: mclk dividers array 170 * @num_mclk_dividers: number of mclk dividers 171 * @get_bclk_parent_rate: callback to get bclk parent rate 172 * @get_sr: callback to get sample resolution 173 * @get_wss: callback to get word select size 174 * @set_chan_cfg: callback to set channel configuration 175 * @set_fmt: callback to set format 176 */ 177 struct sun4i_i2s_quirks { 178 bool has_reset; 179 u64 pcm_formats; 180 unsigned int reg_offset_txdata; /* TX FIFO */ 181 const struct regmap_config *sun4i_i2s_regmap; 182 183 /* Register fields for i2s */ 184 struct reg_field field_clkdiv_mclk_en; 185 struct reg_field field_fmt_wss; 186 struct reg_field field_fmt_sr; 187 188 unsigned int num_din_pins; 189 unsigned int num_dout_pins; 190 191 const struct sun4i_i2s_clk_div *bclk_dividers; 192 unsigned int num_bclk_dividers; 193 const struct sun4i_i2s_clk_div *mclk_dividers; 194 unsigned int num_mclk_dividers; 195 196 unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s); 197 int (*get_sr)(unsigned int width); 198 int (*get_wss)(unsigned int width); 199 200 /* 201 * In the set_chan_cfg() function pointer: 202 * @slots: channels per frame + padding slots, regardless of format 203 * @slot_width: bits per sample + padding bits, regardless of format 204 */ 205 int (*set_chan_cfg)(const struct sun4i_i2s *i2s, 206 unsigned int channels, unsigned int slots, 207 unsigned int slot_width); 208 int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt); 209 }; 210 211 struct sun4i_i2s { 212 struct clk *bus_clk; 213 struct clk *mod_clk; 214 struct regmap *regmap; 215 struct reset_control *rst; 216 217 unsigned int format; 218 unsigned int mclk_freq; 219 unsigned int slots; 220 unsigned int slot_width; 221 222 struct snd_dmaengine_dai_dma_data capture_dma_data; 223 struct snd_dmaengine_dai_dma_data playback_dma_data; 224 225 /* Register fields for i2s */ 226 struct regmap_field *field_clkdiv_mclk_en; 227 struct regmap_field *field_fmt_wss; 228 struct regmap_field *field_fmt_sr; 229 230 const struct sun4i_i2s_quirks *variant; 231 }; 232 233 struct sun4i_i2s_clk_div { 234 u8 div; 235 u8 val; 236 }; 237 238 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = { 239 { .div = 2, .val = 0 }, 240 { .div = 4, .val = 1 }, 241 { .div = 6, .val = 2 }, 242 { .div = 8, .val = 3 }, 243 { .div = 12, .val = 4 }, 244 { .div = 16, .val = 5 }, 245 /* TODO - extend divide ratio supported by newer SoCs */ 246 }; 247 248 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = { 249 { .div = 1, .val = 0 }, 250 { .div = 2, .val = 1 }, 251 { .div = 4, .val = 2 }, 252 { .div = 6, .val = 3 }, 253 { .div = 8, .val = 4 }, 254 { .div = 12, .val = 5 }, 255 { .div = 16, .val = 6 }, 256 { .div = 24, .val = 7 }, 257 /* TODO - extend divide ratio supported by newer SoCs */ 258 }; 259 260 static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = { 261 { .div = 1, .val = 1 }, 262 { .div = 2, .val = 2 }, 263 { .div = 4, .val = 3 }, 264 { .div = 6, .val = 4 }, 265 { .div = 8, .val = 5 }, 266 { .div = 12, .val = 6 }, 267 { .div = 16, .val = 7 }, 268 { .div = 24, .val = 8 }, 269 { .div = 32, .val = 9 }, 270 { .div = 48, .val = 10 }, 271 { .div = 64, .val = 11 }, 272 { .div = 96, .val = 12 }, 273 { .div = 128, .val = 13 }, 274 { .div = 176, .val = 14 }, 275 { .div = 192, .val = 15 }, 276 }; 277 278 static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) 279 { 280 return i2s->mclk_freq; 281 } 282 283 static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) 284 { 285 return clk_get_rate(i2s->mod_clk); 286 } 287 288 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, 289 unsigned long parent_rate, 290 unsigned int sampling_rate, 291 unsigned int channels, 292 unsigned int word_size) 293 { 294 const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers; 295 int div = parent_rate / sampling_rate / word_size / channels; 296 int i; 297 298 for (i = 0; i < i2s->variant->num_bclk_dividers; i++) { 299 const struct sun4i_i2s_clk_div *bdiv = ÷rs[i]; 300 301 if (bdiv->div == div) 302 return bdiv->val; 303 } 304 305 return -EINVAL; 306 } 307 308 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, 309 unsigned long parent_rate, 310 unsigned long mclk_rate) 311 { 312 const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers; 313 int div = parent_rate / mclk_rate; 314 int i; 315 316 for (i = 0; i < i2s->variant->num_mclk_dividers; i++) { 317 const struct sun4i_i2s_clk_div *mdiv = ÷rs[i]; 318 319 if (mdiv->div == div) 320 return mdiv->val; 321 } 322 323 return -EINVAL; 324 } 325 326 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 }; 327 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample) 328 { 329 int i; 330 331 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++) 332 if (sun4i_i2s_oversample_rates[i] == oversample) 333 return true; 334 335 return false; 336 } 337 338 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, 339 unsigned int rate, 340 unsigned int slots, 341 unsigned int slot_width) 342 { 343 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 344 unsigned int oversample_rate, clk_rate, bclk_parent_rate; 345 int bclk_div, mclk_div; 346 int ret; 347 348 switch (rate) { 349 case 176400: 350 case 88200: 351 case 44100: 352 case 22050: 353 case 11025: 354 clk_rate = 22579200; 355 break; 356 357 case 192000: 358 case 128000: 359 case 96000: 360 case 64000: 361 case 48000: 362 case 32000: 363 case 24000: 364 case 16000: 365 case 12000: 366 case 8000: 367 clk_rate = 24576000; 368 break; 369 370 default: 371 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); 372 return -EINVAL; 373 } 374 375 ret = clk_set_rate(i2s->mod_clk, clk_rate); 376 if (ret) 377 return ret; 378 379 oversample_rate = i2s->mclk_freq / rate; 380 if (!sun4i_i2s_oversample_is_valid(oversample_rate)) { 381 dev_err(dai->dev, "Unsupported oversample rate: %d\n", 382 oversample_rate); 383 return -EINVAL; 384 } 385 386 bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); 387 bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate, 388 rate, slots, slot_width); 389 if (bclk_div < 0) { 390 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); 391 return -EINVAL; 392 } 393 394 mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq); 395 if (mclk_div < 0) { 396 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); 397 return -EINVAL; 398 } 399 400 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, 401 SUN4I_I2S_CLK_DIV_BCLK(bclk_div) | 402 SUN4I_I2S_CLK_DIV_MCLK(mclk_div)); 403 404 regmap_field_write(i2s->field_clkdiv_mclk_en, 1); 405 406 return 0; 407 } 408 409 static int sun4i_i2s_get_sr(unsigned int width) 410 { 411 switch (width) { 412 case 16: 413 return 0; 414 case 20: 415 return 1; 416 case 24: 417 return 2; 418 } 419 420 return -EINVAL; 421 } 422 423 static int sun4i_i2s_get_wss(unsigned int width) 424 { 425 switch (width) { 426 case 16: 427 return 0; 428 case 20: 429 return 1; 430 case 24: 431 return 2; 432 case 32: 433 return 3; 434 } 435 436 return -EINVAL; 437 } 438 439 static int sun8i_i2s_get_sr_wss(unsigned int width) 440 { 441 switch (width) { 442 case 8: 443 return 1; 444 case 12: 445 return 2; 446 case 16: 447 return 3; 448 case 20: 449 return 4; 450 case 24: 451 return 5; 452 case 28: 453 return 6; 454 case 32: 455 return 7; 456 } 457 458 return -EINVAL; 459 } 460 461 static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, 462 unsigned int channels, unsigned int slots, 463 unsigned int slot_width) 464 { 465 /* Map the channels for playback and capture */ 466 regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); 467 regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); 468 469 /* Configure the channels */ 470 regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG, 471 SUN4I_I2S_CHAN_SEL_MASK, 472 SUN4I_I2S_CHAN_SEL(channels)); 473 regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG, 474 SUN4I_I2S_CHAN_SEL_MASK, 475 SUN4I_I2S_CHAN_SEL(channels)); 476 477 return 0; 478 } 479 480 static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, 481 unsigned int channels, unsigned int slots, 482 unsigned int slot_width) 483 { 484 unsigned int lrck_period; 485 486 /* Map the channels for playback and capture */ 487 regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); 488 regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); 489 490 /* Configure the channels */ 491 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 492 SUN4I_I2S_CHAN_SEL_MASK, 493 SUN4I_I2S_CHAN_SEL(channels)); 494 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, 495 SUN4I_I2S_CHAN_SEL_MASK, 496 SUN4I_I2S_CHAN_SEL(channels)); 497 498 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 499 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, 500 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); 501 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 502 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, 503 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); 504 505 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { 506 case SND_SOC_DAIFMT_DSP_A: 507 case SND_SOC_DAIFMT_DSP_B: 508 lrck_period = slot_width * slots; 509 break; 510 511 case SND_SOC_DAIFMT_LEFT_J: 512 case SND_SOC_DAIFMT_RIGHT_J: 513 case SND_SOC_DAIFMT_I2S: 514 lrck_period = slot_width; 515 break; 516 517 default: 518 return -EINVAL; 519 } 520 521 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 522 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, 523 SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period)); 524 525 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 526 SUN8I_I2S_TX_CHAN_EN_MASK, 527 SUN8I_I2S_TX_CHAN_EN(channels)); 528 529 return 0; 530 } 531 532 static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, 533 unsigned int channels, unsigned int slots, 534 unsigned int slot_width) 535 { 536 unsigned int lrck_period; 537 538 /* Map the channels for playback and capture */ 539 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98); 540 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210); 541 if (i2s->variant->num_din_pins > 1) { 542 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP0_REG, 0x0F0E0D0C); 543 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP1_REG, 0x0B0A0908); 544 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP2_REG, 0x07060504); 545 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 0x03020100); 546 } else { 547 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98); 548 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210); 549 } 550 551 /* Configure the channels */ 552 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), 553 SUN50I_H6_I2S_TX_CHAN_SEL_MASK, 554 SUN50I_H6_I2S_TX_CHAN_SEL(channels)); 555 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, 556 SUN50I_H6_I2S_TX_CHAN_SEL_MASK, 557 SUN50I_H6_I2S_TX_CHAN_SEL(channels)); 558 559 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 560 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, 561 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); 562 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 563 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, 564 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); 565 566 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { 567 case SND_SOC_DAIFMT_DSP_A: 568 case SND_SOC_DAIFMT_DSP_B: 569 lrck_period = slot_width * slots; 570 break; 571 572 case SND_SOC_DAIFMT_LEFT_J: 573 case SND_SOC_DAIFMT_RIGHT_J: 574 case SND_SOC_DAIFMT_I2S: 575 lrck_period = slot_width; 576 break; 577 578 default: 579 return -EINVAL; 580 } 581 582 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 583 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, 584 SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period)); 585 586 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), 587 SUN50I_H6_I2S_TX_CHAN_EN_MASK, 588 SUN50I_H6_I2S_TX_CHAN_EN(channels)); 589 590 return 0; 591 } 592 593 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, 594 struct snd_pcm_hw_params *params, 595 struct snd_soc_dai *dai) 596 { 597 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 598 unsigned int word_size = params_width(params); 599 unsigned int slot_width = params_physical_width(params); 600 unsigned int channels = params_channels(params); 601 602 unsigned int slots = channels; 603 604 int ret, sr, wss; 605 u32 width; 606 607 if (i2s->slots) 608 slots = i2s->slots; 609 610 if (i2s->slot_width) 611 slot_width = i2s->slot_width; 612 613 ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width); 614 if (ret < 0) { 615 dev_err(dai->dev, "Invalid channel configuration\n"); 616 return ret; 617 } 618 619 /* Set significant bits in our FIFOs */ 620 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 621 SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | 622 SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, 623 SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | 624 SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); 625 626 switch (params_physical_width(params)) { 627 case 16: 628 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 629 break; 630 case 32: 631 width = DMA_SLAVE_BUSWIDTH_4_BYTES; 632 break; 633 default: 634 dev_err(dai->dev, "Unsupported physical sample width: %d\n", 635 params_physical_width(params)); 636 return -EINVAL; 637 } 638 i2s->playback_dma_data.addr_width = width; 639 640 sr = i2s->variant->get_sr(word_size); 641 if (sr < 0) 642 return -EINVAL; 643 644 wss = i2s->variant->get_wss(slot_width); 645 if (wss < 0) 646 return -EINVAL; 647 648 regmap_field_write(i2s->field_fmt_wss, wss); 649 regmap_field_write(i2s->field_fmt_sr, sr); 650 651 return sun4i_i2s_set_clk_rate(dai, params_rate(params), 652 slots, slot_width); 653 } 654 655 static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, 656 unsigned int fmt) 657 { 658 u32 val; 659 660 /* DAI clock polarity */ 661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 662 case SND_SOC_DAIFMT_IB_IF: 663 /* Invert both clocks */ 664 val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED | 665 SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 666 break; 667 case SND_SOC_DAIFMT_IB_NF: 668 /* Invert bit clock */ 669 val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED; 670 break; 671 case SND_SOC_DAIFMT_NB_IF: 672 /* Invert frame clock */ 673 val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 674 break; 675 case SND_SOC_DAIFMT_NB_NF: 676 val = 0; 677 break; 678 default: 679 return -EINVAL; 680 } 681 682 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 683 SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK | 684 SUN4I_I2S_FMT0_BCLK_POLARITY_MASK, 685 val); 686 687 /* DAI Mode */ 688 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 689 case SND_SOC_DAIFMT_I2S: 690 val = SUN4I_I2S_FMT0_FMT_I2S; 691 break; 692 693 case SND_SOC_DAIFMT_LEFT_J: 694 val = SUN4I_I2S_FMT0_FMT_LEFT_J; 695 break; 696 697 case SND_SOC_DAIFMT_RIGHT_J: 698 val = SUN4I_I2S_FMT0_FMT_RIGHT_J; 699 break; 700 701 default: 702 return -EINVAL; 703 } 704 705 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 706 SUN4I_I2S_FMT0_FMT_MASK, val); 707 708 /* DAI clock master masks */ 709 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 710 case SND_SOC_DAIFMT_BP_FP: 711 /* BCLK and LRCLK master */ 712 val = SUN4I_I2S_CTRL_MODE_MASTER; 713 break; 714 715 case SND_SOC_DAIFMT_BC_FC: 716 /* BCLK and LRCLK slave */ 717 val = SUN4I_I2S_CTRL_MODE_SLAVE; 718 break; 719 720 default: 721 return -EINVAL; 722 } 723 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 724 SUN4I_I2S_CTRL_MODE_MASK, val); 725 726 return 0; 727 } 728 729 static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, 730 unsigned int fmt) 731 { 732 u32 mode, val; 733 u8 offset; 734 735 /* 736 * DAI clock polarity 737 * 738 * The setup for LRCK contradicts the datasheet, but under a 739 * scope it's clear that the LRCK polarity is reversed 740 * compared to the expected polarity on the bus. 741 */ 742 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 743 case SND_SOC_DAIFMT_IB_IF: 744 /* Invert both clocks */ 745 val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; 746 break; 747 case SND_SOC_DAIFMT_IB_NF: 748 /* Invert bit clock */ 749 val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | 750 SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 751 break; 752 case SND_SOC_DAIFMT_NB_IF: 753 /* Invert frame clock */ 754 val = 0; 755 break; 756 case SND_SOC_DAIFMT_NB_NF: 757 val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 758 break; 759 default: 760 return -EINVAL; 761 } 762 763 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 764 SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK | 765 SUN8I_I2S_FMT0_BCLK_POLARITY_MASK, 766 val); 767 768 /* DAI Mode */ 769 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 770 case SND_SOC_DAIFMT_DSP_A: 771 mode = SUN8I_I2S_CTRL_MODE_PCM; 772 offset = 1; 773 break; 774 775 case SND_SOC_DAIFMT_DSP_B: 776 mode = SUN8I_I2S_CTRL_MODE_PCM; 777 offset = 0; 778 break; 779 780 case SND_SOC_DAIFMT_I2S: 781 mode = SUN8I_I2S_CTRL_MODE_LEFT; 782 offset = 1; 783 break; 784 785 case SND_SOC_DAIFMT_LEFT_J: 786 mode = SUN8I_I2S_CTRL_MODE_LEFT; 787 offset = 0; 788 break; 789 790 case SND_SOC_DAIFMT_RIGHT_J: 791 mode = SUN8I_I2S_CTRL_MODE_RIGHT; 792 offset = 0; 793 break; 794 795 default: 796 return -EINVAL; 797 } 798 799 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 800 SUN8I_I2S_CTRL_MODE_MASK, mode); 801 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 802 SUN8I_I2S_TX_CHAN_OFFSET_MASK, 803 SUN8I_I2S_TX_CHAN_OFFSET(offset)); 804 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, 805 SUN8I_I2S_TX_CHAN_OFFSET_MASK, 806 SUN8I_I2S_TX_CHAN_OFFSET(offset)); 807 808 /* DAI clock master masks */ 809 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 810 case SND_SOC_DAIFMT_BP_FP: 811 /* BCLK and LRCLK master */ 812 val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT; 813 break; 814 815 case SND_SOC_DAIFMT_BC_FC: 816 /* BCLK and LRCLK slave */ 817 val = 0; 818 break; 819 820 default: 821 return -EINVAL; 822 } 823 824 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 825 SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, 826 val); 827 828 /* Set sign extension to pad out LSB with 0 */ 829 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, 830 SUN8I_I2S_FMT1_REG_SEXT_MASK, 831 SUN8I_I2S_FMT1_REG_SEXT(0)); 832 833 return 0; 834 } 835 836 static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, 837 unsigned int fmt) 838 { 839 u32 mode, val; 840 u8 offset; 841 842 /* 843 * DAI clock polarity 844 * 845 * The setup for LRCK contradicts the datasheet, but under a 846 * scope it's clear that the LRCK polarity is reversed 847 * compared to the expected polarity on the bus. 848 */ 849 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 850 case SND_SOC_DAIFMT_IB_IF: 851 /* Invert both clocks */ 852 val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; 853 break; 854 case SND_SOC_DAIFMT_IB_NF: 855 /* Invert bit clock */ 856 val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | 857 SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 858 break; 859 case SND_SOC_DAIFMT_NB_IF: 860 /* Invert frame clock */ 861 val = 0; 862 break; 863 case SND_SOC_DAIFMT_NB_NF: 864 val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 865 break; 866 default: 867 return -EINVAL; 868 } 869 870 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 871 SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK | 872 SUN8I_I2S_FMT0_BCLK_POLARITY_MASK, 873 val); 874 875 /* DAI Mode */ 876 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 877 case SND_SOC_DAIFMT_DSP_A: 878 mode = SUN8I_I2S_CTRL_MODE_PCM; 879 offset = 1; 880 break; 881 882 case SND_SOC_DAIFMT_DSP_B: 883 mode = SUN8I_I2S_CTRL_MODE_PCM; 884 offset = 0; 885 break; 886 887 case SND_SOC_DAIFMT_I2S: 888 mode = SUN8I_I2S_CTRL_MODE_LEFT; 889 offset = 1; 890 break; 891 892 case SND_SOC_DAIFMT_LEFT_J: 893 mode = SUN8I_I2S_CTRL_MODE_LEFT; 894 offset = 0; 895 break; 896 897 case SND_SOC_DAIFMT_RIGHT_J: 898 mode = SUN8I_I2S_CTRL_MODE_RIGHT; 899 offset = 0; 900 break; 901 902 default: 903 return -EINVAL; 904 } 905 906 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 907 SUN8I_I2S_CTRL_MODE_MASK, mode); 908 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 909 SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK, 910 SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset)); 911 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, 912 SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK, 913 SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset)); 914 915 /* DAI clock master masks */ 916 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 917 case SND_SOC_DAIFMT_BP_FP: 918 /* BCLK and LRCLK master */ 919 val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT; 920 break; 921 922 case SND_SOC_DAIFMT_BC_FC: 923 /* BCLK and LRCLK slave */ 924 val = 0; 925 break; 926 927 default: 928 return -EINVAL; 929 } 930 931 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 932 SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, 933 val); 934 935 /* Set sign extension to pad out LSB with 0 */ 936 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, 937 SUN8I_I2S_FMT1_REG_SEXT_MASK, 938 SUN8I_I2S_FMT1_REG_SEXT(0)); 939 940 return 0; 941 } 942 943 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 944 { 945 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 946 int ret; 947 948 ret = i2s->variant->set_fmt(i2s, fmt); 949 if (ret) { 950 dev_err(dai->dev, "Unsupported format configuration\n"); 951 return ret; 952 } 953 954 i2s->format = fmt; 955 956 return 0; 957 } 958 959 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s) 960 { 961 /* Flush RX FIFO */ 962 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 963 SUN4I_I2S_FIFO_CTRL_FLUSH_RX, 964 SUN4I_I2S_FIFO_CTRL_FLUSH_RX); 965 966 /* Clear RX counter */ 967 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); 968 969 /* Enable RX Block */ 970 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 971 SUN4I_I2S_CTRL_RX_EN, 972 SUN4I_I2S_CTRL_RX_EN); 973 974 /* Enable RX DRQ */ 975 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 976 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 977 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN); 978 } 979 980 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s) 981 { 982 /* Flush TX FIFO */ 983 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 984 SUN4I_I2S_FIFO_CTRL_FLUSH_TX, 985 SUN4I_I2S_FIFO_CTRL_FLUSH_TX); 986 987 /* Clear TX counter */ 988 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); 989 990 /* Enable TX Block */ 991 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 992 SUN4I_I2S_CTRL_TX_EN, 993 SUN4I_I2S_CTRL_TX_EN); 994 995 /* Enable TX DRQ */ 996 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 997 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 998 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN); 999 } 1000 1001 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s) 1002 { 1003 /* Disable RX Block */ 1004 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1005 SUN4I_I2S_CTRL_RX_EN, 1006 0); 1007 1008 /* Disable RX DRQ */ 1009 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 1010 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 1011 0); 1012 } 1013 1014 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s) 1015 { 1016 /* Disable TX Block */ 1017 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1018 SUN4I_I2S_CTRL_TX_EN, 1019 0); 1020 1021 /* Disable TX DRQ */ 1022 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 1023 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 1024 0); 1025 } 1026 1027 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 1028 struct snd_soc_dai *dai) 1029 { 1030 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 1031 1032 switch (cmd) { 1033 case SNDRV_PCM_TRIGGER_START: 1034 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1035 case SNDRV_PCM_TRIGGER_RESUME: 1036 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1037 sun4i_i2s_start_playback(i2s); 1038 else 1039 sun4i_i2s_start_capture(i2s); 1040 break; 1041 1042 case SNDRV_PCM_TRIGGER_STOP: 1043 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1044 case SNDRV_PCM_TRIGGER_SUSPEND: 1045 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1046 sun4i_i2s_stop_playback(i2s); 1047 else 1048 sun4i_i2s_stop_capture(i2s); 1049 break; 1050 1051 default: 1052 return -EINVAL; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 1059 unsigned int freq, int dir) 1060 { 1061 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 1062 1063 if (clk_id != 0) 1064 return -EINVAL; 1065 1066 i2s->mclk_freq = freq; 1067 1068 return 0; 1069 } 1070 1071 static int sun4i_i2s_set_tdm_slot(struct snd_soc_dai *dai, 1072 unsigned int tx_mask, unsigned int rx_mask, 1073 int slots, int slot_width) 1074 { 1075 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 1076 1077 if (slots > 8) 1078 return -EINVAL; 1079 1080 i2s->slots = slots; 1081 i2s->slot_width = slot_width; 1082 1083 return 0; 1084 } 1085 1086 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai) 1087 { 1088 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 1089 1090 snd_soc_dai_init_dma_data(dai, 1091 &i2s->playback_dma_data, 1092 &i2s->capture_dma_data); 1093 1094 return 0; 1095 } 1096 1097 static int sun4i_i2s_dai_startup(struct snd_pcm_substream *sub, struct snd_soc_dai *dai) 1098 { 1099 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 1100 struct snd_pcm_runtime *runtime = sub->runtime; 1101 1102 return snd_pcm_hw_constraint_mask64(runtime, SNDRV_PCM_HW_PARAM_FORMAT, 1103 i2s->variant->pcm_formats); 1104 } 1105 1106 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { 1107 .probe = sun4i_i2s_dai_probe, 1108 .startup = sun4i_i2s_dai_startup, 1109 .hw_params = sun4i_i2s_hw_params, 1110 .set_fmt = sun4i_i2s_set_fmt, 1111 .set_sysclk = sun4i_i2s_set_sysclk, 1112 .set_tdm_slot = sun4i_i2s_set_tdm_slot, 1113 .trigger = sun4i_i2s_trigger, 1114 }; 1115 1116 #define SUN4I_FORMATS_ALL (SNDRV_PCM_FMTBIT_S16_LE | \ 1117 SNDRV_PCM_FMTBIT_S20_LE | \ 1118 SNDRV_PCM_FMTBIT_S24_LE | \ 1119 SNDRV_PCM_FMTBIT_S32_LE) 1120 1121 static struct snd_soc_dai_driver sun4i_i2s_dai = { 1122 .capture = { 1123 .stream_name = "Capture", 1124 .channels_min = 1, 1125 .channels_max = 8, 1126 .rates = SNDRV_PCM_RATE_8000_192000, 1127 .formats = SUN4I_FORMATS_ALL, 1128 }, 1129 .playback = { 1130 .stream_name = "Playback", 1131 .channels_min = 1, 1132 .channels_max = 8, 1133 .rates = SNDRV_PCM_RATE_8000_192000, 1134 .formats = SUN4I_FORMATS_ALL, 1135 }, 1136 .ops = &sun4i_i2s_dai_ops, 1137 .symmetric_rate = 1, 1138 }; 1139 1140 static const struct snd_soc_component_driver sun4i_i2s_component = { 1141 .name = "sun4i-dai", 1142 .legacy_dai_naming = 1, 1143 }; 1144 1145 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg) 1146 { 1147 switch (reg) { 1148 case SUN4I_I2S_FIFO_TX_REG: 1149 return false; 1150 1151 default: 1152 return true; 1153 } 1154 } 1155 1156 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg) 1157 { 1158 switch (reg) { 1159 case SUN4I_I2S_FIFO_RX_REG: 1160 case SUN4I_I2S_FIFO_STA_REG: 1161 return false; 1162 1163 default: 1164 return true; 1165 } 1166 } 1167 1168 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg) 1169 { 1170 switch (reg) { 1171 case SUN4I_I2S_FIFO_RX_REG: 1172 case SUN4I_I2S_INT_STA_REG: 1173 case SUN4I_I2S_RX_CNT_REG: 1174 case SUN4I_I2S_TX_CNT_REG: 1175 return true; 1176 1177 default: 1178 return false; 1179 } 1180 } 1181 1182 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg) 1183 { 1184 switch (reg) { 1185 case SUN8I_I2S_FIFO_TX_REG: 1186 return false; 1187 1188 default: 1189 return true; 1190 } 1191 } 1192 1193 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) 1194 { 1195 switch (reg) { 1196 case SUN4I_I2S_FIFO_CTRL_REG: 1197 case SUN4I_I2S_FIFO_RX_REG: 1198 case SUN4I_I2S_FIFO_STA_REG: 1199 case SUN4I_I2S_RX_CNT_REG: 1200 case SUN4I_I2S_TX_CNT_REG: 1201 case SUN8I_I2S_FIFO_TX_REG: 1202 case SUN8I_I2S_INT_STA_REG: 1203 return true; 1204 1205 default: 1206 return false; 1207 } 1208 } 1209 1210 static const struct reg_default sun4i_i2s_reg_defaults[] = { 1211 { SUN4I_I2S_CTRL_REG, 0x00000000 }, 1212 { SUN4I_I2S_FMT0_REG, 0x0000000c }, 1213 { SUN4I_I2S_FMT1_REG, 0x00004020 }, 1214 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 1215 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 1216 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 1217 { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 }, 1218 { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 }, 1219 { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 }, 1220 { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 }, 1221 }; 1222 1223 static const struct reg_default sun8i_i2s_reg_defaults[] = { 1224 { SUN4I_I2S_CTRL_REG, 0x00060000 }, 1225 { SUN4I_I2S_FMT0_REG, 0x00000033 }, 1226 { SUN4I_I2S_FMT1_REG, 0x00000030 }, 1227 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 1228 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 1229 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 1230 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, 1231 { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 }, 1232 { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 }, 1233 { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 }, 1234 { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 }, 1235 }; 1236 1237 static const struct reg_default sun50i_h6_i2s_reg_defaults[] = { 1238 { SUN4I_I2S_CTRL_REG, 0x00060000 }, 1239 { SUN4I_I2S_FMT0_REG, 0x00000033 }, 1240 { SUN4I_I2S_FMT1_REG, 0x00000030 }, 1241 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 1242 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 1243 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 1244 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, 1245 { SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), 0x00000000 }, 1246 { SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0x00000000 }, 1247 { SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x00000000 }, 1248 { SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 }, 1249 { SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 }, 1250 { SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 }, 1251 }; 1252 1253 static const struct regmap_config sun4i_i2s_regmap_config = { 1254 .reg_bits = 32, 1255 .reg_stride = 4, 1256 .val_bits = 32, 1257 .max_register = SUN4I_I2S_RX_CHAN_MAP_REG, 1258 1259 .cache_type = REGCACHE_FLAT, 1260 .reg_defaults = sun4i_i2s_reg_defaults, 1261 .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults), 1262 .writeable_reg = sun4i_i2s_wr_reg, 1263 .readable_reg = sun4i_i2s_rd_reg, 1264 .volatile_reg = sun4i_i2s_volatile_reg, 1265 }; 1266 1267 static const struct regmap_config sun8i_i2s_regmap_config = { 1268 .reg_bits = 32, 1269 .reg_stride = 4, 1270 .val_bits = 32, 1271 .max_register = SUN8I_I2S_RX_CHAN_MAP_REG, 1272 .cache_type = REGCACHE_FLAT, 1273 .reg_defaults = sun8i_i2s_reg_defaults, 1274 .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults), 1275 .writeable_reg = sun4i_i2s_wr_reg, 1276 .readable_reg = sun8i_i2s_rd_reg, 1277 .volatile_reg = sun8i_i2s_volatile_reg, 1278 }; 1279 1280 static const struct regmap_config sun50i_h6_i2s_regmap_config = { 1281 .reg_bits = 32, 1282 .reg_stride = 4, 1283 .val_bits = 32, 1284 .max_register = SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 1285 .cache_type = REGCACHE_FLAT, 1286 .reg_defaults = sun50i_h6_i2s_reg_defaults, 1287 .num_reg_defaults = ARRAY_SIZE(sun50i_h6_i2s_reg_defaults), 1288 .writeable_reg = sun4i_i2s_wr_reg, 1289 .readable_reg = sun8i_i2s_rd_reg, 1290 .volatile_reg = sun8i_i2s_volatile_reg, 1291 }; 1292 1293 static int sun4i_i2s_runtime_resume(struct device *dev) 1294 { 1295 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 1296 int ret; 1297 1298 ret = clk_prepare_enable(i2s->bus_clk); 1299 if (ret) { 1300 dev_err(dev, "Failed to enable bus clock\n"); 1301 return ret; 1302 } 1303 1304 regcache_cache_only(i2s->regmap, false); 1305 regcache_mark_dirty(i2s->regmap); 1306 1307 ret = regcache_sync(i2s->regmap); 1308 if (ret) { 1309 dev_err(dev, "Failed to sync regmap cache\n"); 1310 goto err_disable_clk; 1311 } 1312 1313 /* Enable the whole hardware block */ 1314 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1315 SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN); 1316 1317 /* Enable the first output line */ 1318 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1319 SUN4I_I2S_CTRL_SDO_EN_MASK, 1320 SUN4I_I2S_CTRL_SDO_EN(0)); 1321 1322 ret = clk_prepare_enable(i2s->mod_clk); 1323 if (ret) { 1324 dev_err(dev, "Failed to enable module clock\n"); 1325 goto err_disable_clk; 1326 } 1327 1328 return 0; 1329 1330 err_disable_clk: 1331 clk_disable_unprepare(i2s->bus_clk); 1332 return ret; 1333 } 1334 1335 static int sun4i_i2s_runtime_suspend(struct device *dev) 1336 { 1337 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 1338 1339 clk_disable_unprepare(i2s->mod_clk); 1340 1341 /* Disable our output lines */ 1342 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1343 SUN4I_I2S_CTRL_SDO_EN_MASK, 0); 1344 1345 /* Disable the whole hardware block */ 1346 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1347 SUN4I_I2S_CTRL_GL_EN, 0); 1348 1349 regcache_cache_only(i2s->regmap, true); 1350 1351 clk_disable_unprepare(i2s->bus_clk); 1352 1353 return 0; 1354 } 1355 1356 #define SUN4I_FORMATS_A10 (SUN4I_FORMATS_ALL & ~SNDRV_PCM_FMTBIT_S32_LE) 1357 #define SUN4I_FORMATS_H3 SUN4I_FORMATS_ALL 1358 1359 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { 1360 .has_reset = false, 1361 .pcm_formats = SUN4I_FORMATS_A10, 1362 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 1363 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 1364 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 1365 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 1366 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 1367 .bclk_dividers = sun4i_i2s_bclk_div, 1368 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), 1369 .mclk_dividers = sun4i_i2s_mclk_div, 1370 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), 1371 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, 1372 .get_sr = sun4i_i2s_get_sr, 1373 .get_wss = sun4i_i2s_get_wss, 1374 .set_chan_cfg = sun4i_i2s_set_chan_cfg, 1375 .set_fmt = sun4i_i2s_set_soc_fmt, 1376 }; 1377 1378 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { 1379 .has_reset = true, 1380 .pcm_formats = SUN4I_FORMATS_A10, 1381 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 1382 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 1383 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 1384 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 1385 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 1386 .bclk_dividers = sun4i_i2s_bclk_div, 1387 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), 1388 .mclk_dividers = sun4i_i2s_mclk_div, 1389 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), 1390 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, 1391 .get_sr = sun4i_i2s_get_sr, 1392 .get_wss = sun4i_i2s_get_wss, 1393 .set_chan_cfg = sun4i_i2s_set_chan_cfg, 1394 .set_fmt = sun4i_i2s_set_soc_fmt, 1395 }; 1396 1397 /* 1398 * This doesn't describe the TDM controller documented in the A83t 1399 * datasheet, but the three undocumented I2S controller that use the 1400 * older design. 1401 */ 1402 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { 1403 .has_reset = true, 1404 .pcm_formats = SUN4I_FORMATS_A10, 1405 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 1406 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 1407 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 1408 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 1409 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 1410 .bclk_dividers = sun4i_i2s_bclk_div, 1411 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), 1412 .mclk_dividers = sun4i_i2s_mclk_div, 1413 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), 1414 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, 1415 .get_sr = sun4i_i2s_get_sr, 1416 .get_wss = sun4i_i2s_get_wss, 1417 .set_chan_cfg = sun4i_i2s_set_chan_cfg, 1418 .set_fmt = sun4i_i2s_set_soc_fmt, 1419 }; 1420 1421 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { 1422 .has_reset = true, 1423 .pcm_formats = SUN4I_FORMATS_H3, 1424 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 1425 .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, 1426 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), 1427 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), 1428 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), 1429 .bclk_dividers = sun8i_i2s_clk_div, 1430 .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), 1431 .mclk_dividers = sun8i_i2s_clk_div, 1432 .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), 1433 .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, 1434 .get_sr = sun8i_i2s_get_sr_wss, 1435 .get_wss = sun8i_i2s_get_sr_wss, 1436 .set_chan_cfg = sun8i_i2s_set_chan_cfg, 1437 .set_fmt = sun8i_i2s_set_soc_fmt, 1438 }; 1439 1440 static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { 1441 .has_reset = true, 1442 .pcm_formats = SUN4I_FORMATS_H3, 1443 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 1444 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 1445 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 1446 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 1447 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 1448 .bclk_dividers = sun4i_i2s_bclk_div, 1449 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), 1450 .mclk_dividers = sun4i_i2s_mclk_div, 1451 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), 1452 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, 1453 .get_sr = sun4i_i2s_get_sr, 1454 .get_wss = sun4i_i2s_get_wss, 1455 .set_chan_cfg = sun4i_i2s_set_chan_cfg, 1456 .set_fmt = sun4i_i2s_set_soc_fmt, 1457 }; 1458 1459 static const struct sun4i_i2s_quirks sun50i_h6_i2s_quirks = { 1460 .has_reset = true, 1461 .pcm_formats = SUN4I_FORMATS_H3, 1462 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 1463 .sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config, 1464 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), 1465 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), 1466 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), 1467 .bclk_dividers = sun8i_i2s_clk_div, 1468 .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), 1469 .mclk_dividers = sun8i_i2s_clk_div, 1470 .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), 1471 .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, 1472 .get_sr = sun8i_i2s_get_sr_wss, 1473 .get_wss = sun8i_i2s_get_sr_wss, 1474 .set_chan_cfg = sun50i_h6_i2s_set_chan_cfg, 1475 .set_fmt = sun50i_h6_i2s_set_soc_fmt, 1476 }; 1477 1478 static const struct sun4i_i2s_quirks sun50i_r329_i2s_quirks = { 1479 .has_reset = true, 1480 .pcm_formats = SUN4I_FORMATS_H3, 1481 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 1482 .sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config, 1483 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), 1484 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), 1485 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), 1486 .num_din_pins = 4, 1487 .num_dout_pins = 4, 1488 .bclk_dividers = sun8i_i2s_clk_div, 1489 .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), 1490 .mclk_dividers = sun8i_i2s_clk_div, 1491 .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), 1492 .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, 1493 .get_sr = sun8i_i2s_get_sr_wss, 1494 .get_wss = sun8i_i2s_get_sr_wss, 1495 .set_chan_cfg = sun50i_h6_i2s_set_chan_cfg, 1496 .set_fmt = sun50i_h6_i2s_set_soc_fmt, 1497 }; 1498 1499 static int sun4i_i2s_init_regmap_fields(struct device *dev, 1500 struct sun4i_i2s *i2s) 1501 { 1502 i2s->field_clkdiv_mclk_en = 1503 devm_regmap_field_alloc(dev, i2s->regmap, 1504 i2s->variant->field_clkdiv_mclk_en); 1505 if (IS_ERR(i2s->field_clkdiv_mclk_en)) 1506 return PTR_ERR(i2s->field_clkdiv_mclk_en); 1507 1508 i2s->field_fmt_wss = 1509 devm_regmap_field_alloc(dev, i2s->regmap, 1510 i2s->variant->field_fmt_wss); 1511 if (IS_ERR(i2s->field_fmt_wss)) 1512 return PTR_ERR(i2s->field_fmt_wss); 1513 1514 i2s->field_fmt_sr = 1515 devm_regmap_field_alloc(dev, i2s->regmap, 1516 i2s->variant->field_fmt_sr); 1517 if (IS_ERR(i2s->field_fmt_sr)) 1518 return PTR_ERR(i2s->field_fmt_sr); 1519 1520 return 0; 1521 } 1522 1523 static int sun4i_i2s_probe(struct platform_device *pdev) 1524 { 1525 struct sun4i_i2s *i2s; 1526 struct resource *res; 1527 void __iomem *regs; 1528 int irq, ret; 1529 1530 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 1531 if (!i2s) 1532 return -ENOMEM; 1533 platform_set_drvdata(pdev, i2s); 1534 1535 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1536 if (IS_ERR(regs)) 1537 return PTR_ERR(regs); 1538 1539 irq = platform_get_irq(pdev, 0); 1540 if (irq < 0) 1541 return irq; 1542 1543 i2s->variant = of_device_get_match_data(&pdev->dev); 1544 if (!i2s->variant) { 1545 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); 1546 return -ENODEV; 1547 } 1548 1549 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb"); 1550 if (IS_ERR(i2s->bus_clk)) { 1551 dev_err(&pdev->dev, "Can't get our bus clock\n"); 1552 return PTR_ERR(i2s->bus_clk); 1553 } 1554 1555 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1556 i2s->variant->sun4i_i2s_regmap); 1557 if (IS_ERR(i2s->regmap)) { 1558 dev_err(&pdev->dev, "Regmap initialisation failed\n"); 1559 return PTR_ERR(i2s->regmap); 1560 } 1561 1562 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod"); 1563 if (IS_ERR(i2s->mod_clk)) { 1564 dev_err(&pdev->dev, "Can't get our mod clock\n"); 1565 return PTR_ERR(i2s->mod_clk); 1566 } 1567 1568 if (i2s->variant->has_reset) { 1569 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1570 if (IS_ERR(i2s->rst)) { 1571 dev_err(&pdev->dev, "Failed to get reset control\n"); 1572 return PTR_ERR(i2s->rst); 1573 } 1574 } 1575 1576 if (!IS_ERR(i2s->rst)) { 1577 ret = reset_control_deassert(i2s->rst); 1578 if (ret) { 1579 dev_err(&pdev->dev, 1580 "Failed to deassert the reset control\n"); 1581 return -EINVAL; 1582 } 1583 } 1584 1585 i2s->playback_dma_data.addr = res->start + 1586 i2s->variant->reg_offset_txdata; 1587 i2s->playback_dma_data.maxburst = 8; 1588 1589 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; 1590 i2s->capture_dma_data.maxburst = 8; 1591 1592 pm_runtime_enable(&pdev->dev); 1593 if (!pm_runtime_enabled(&pdev->dev)) { 1594 ret = sun4i_i2s_runtime_resume(&pdev->dev); 1595 if (ret) 1596 goto err_pm_disable; 1597 } 1598 1599 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); 1600 if (ret) { 1601 dev_err(&pdev->dev, "Could not initialise regmap fields\n"); 1602 goto err_suspend; 1603 } 1604 1605 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1606 if (ret) { 1607 dev_err(&pdev->dev, "Could not register PCM\n"); 1608 goto err_suspend; 1609 } 1610 1611 ret = devm_snd_soc_register_component(&pdev->dev, 1612 &sun4i_i2s_component, 1613 &sun4i_i2s_dai, 1); 1614 if (ret) { 1615 dev_err(&pdev->dev, "Could not register DAI\n"); 1616 goto err_suspend; 1617 } 1618 1619 return 0; 1620 1621 err_suspend: 1622 if (!pm_runtime_status_suspended(&pdev->dev)) 1623 sun4i_i2s_runtime_suspend(&pdev->dev); 1624 err_pm_disable: 1625 pm_runtime_disable(&pdev->dev); 1626 if (!IS_ERR(i2s->rst)) 1627 reset_control_assert(i2s->rst); 1628 1629 return ret; 1630 } 1631 1632 static void sun4i_i2s_remove(struct platform_device *pdev) 1633 { 1634 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); 1635 1636 pm_runtime_disable(&pdev->dev); 1637 if (!pm_runtime_status_suspended(&pdev->dev)) 1638 sun4i_i2s_runtime_suspend(&pdev->dev); 1639 1640 if (!IS_ERR(i2s->rst)) 1641 reset_control_assert(i2s->rst); 1642 } 1643 1644 static const struct of_device_id sun4i_i2s_match[] = { 1645 { 1646 .compatible = "allwinner,sun4i-a10-i2s", 1647 .data = &sun4i_a10_i2s_quirks, 1648 }, 1649 { 1650 .compatible = "allwinner,sun6i-a31-i2s", 1651 .data = &sun6i_a31_i2s_quirks, 1652 }, 1653 { 1654 .compatible = "allwinner,sun8i-a83t-i2s", 1655 .data = &sun8i_a83t_i2s_quirks, 1656 }, 1657 { 1658 .compatible = "allwinner,sun8i-h3-i2s", 1659 .data = &sun8i_h3_i2s_quirks, 1660 }, 1661 { 1662 .compatible = "allwinner,sun50i-a64-codec-i2s", 1663 .data = &sun50i_a64_codec_i2s_quirks, 1664 }, 1665 { 1666 .compatible = "allwinner,sun50i-h6-i2s", 1667 .data = &sun50i_h6_i2s_quirks, 1668 }, 1669 { 1670 .compatible = "allwinner,sun50i-r329-i2s", 1671 .data = &sun50i_r329_i2s_quirks, 1672 }, 1673 {} 1674 }; 1675 MODULE_DEVICE_TABLE(of, sun4i_i2s_match); 1676 1677 static const struct dev_pm_ops sun4i_i2s_pm_ops = { 1678 .runtime_resume = sun4i_i2s_runtime_resume, 1679 .runtime_suspend = sun4i_i2s_runtime_suspend, 1680 }; 1681 1682 static struct platform_driver sun4i_i2s_driver = { 1683 .probe = sun4i_i2s_probe, 1684 .remove_new = sun4i_i2s_remove, 1685 .driver = { 1686 .name = "sun4i-i2s", 1687 .of_match_table = sun4i_i2s_match, 1688 .pm = &sun4i_i2s_pm_ops, 1689 }, 1690 }; 1691 module_platform_driver(sun4i_i2s_driver); 1692 1693 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>"); 1694 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1695 MODULE_DESCRIPTION("Allwinner A10 I2S driver"); 1696 MODULE_LICENSE("GPL"); 1697