1 /* 2 * Copyright 2014 Emilio López <emilio@elopez.com.ar> 3 * Copyright 2014 Jon Smirl <jonsmirl@gmail.com> 4 * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com> 5 * Copyright 2015 Adam Sampson <ats@offog.org> 6 * Copyright 2016 Chen-Yu Tsai <wens@csie.org> 7 * 8 * Based on the Allwinner SDK driver, released under the GPL. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/of.h> 28 #include <linux/of_address.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/clk.h> 32 #include <linux/regmap.h> 33 #include <linux/reset.h> 34 #include <linux/gpio/consumer.h> 35 36 #include <sound/core.h> 37 #include <sound/pcm.h> 38 #include <sound/pcm_params.h> 39 #include <sound/soc.h> 40 #include <sound/tlv.h> 41 #include <sound/initval.h> 42 #include <sound/dmaengine_pcm.h> 43 44 /* Codec DAC digital controls and FIFO registers */ 45 #define SUN4I_CODEC_DAC_DPC (0x00) 46 #define SUN4I_CODEC_DAC_DPC_EN_DA (31) 47 #define SUN4I_CODEC_DAC_DPC_DVOL (12) 48 #define SUN4I_CODEC_DAC_FIFOC (0x04) 49 #define SUN4I_CODEC_DAC_FIFOC_DAC_FS (29) 50 #define SUN4I_CODEC_DAC_FIFOC_FIR_VERSION (28) 51 #define SUN4I_CODEC_DAC_FIFOC_SEND_LASAT (26) 52 #define SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE (24) 53 #define SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT (21) 54 #define SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL (8) 55 #define SUN4I_CODEC_DAC_FIFOC_MONO_EN (6) 56 #define SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS (5) 57 #define SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN (4) 58 #define SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH (0) 59 #define SUN4I_CODEC_DAC_FIFOS (0x08) 60 #define SUN4I_CODEC_DAC_TXDATA (0x0c) 61 62 /* Codec DAC side analog signal controls */ 63 #define SUN4I_CODEC_DAC_ACTL (0x10) 64 #define SUN4I_CODEC_DAC_ACTL_DACAENR (31) 65 #define SUN4I_CODEC_DAC_ACTL_DACAENL (30) 66 #define SUN4I_CODEC_DAC_ACTL_MIXEN (29) 67 #define SUN4I_CODEC_DAC_ACTL_LDACLMIXS (15) 68 #define SUN4I_CODEC_DAC_ACTL_RDACRMIXS (14) 69 #define SUN4I_CODEC_DAC_ACTL_LDACRMIXS (13) 70 #define SUN4I_CODEC_DAC_ACTL_DACPAS (8) 71 #define SUN4I_CODEC_DAC_ACTL_MIXPAS (7) 72 #define SUN4I_CODEC_DAC_ACTL_PA_MUTE (6) 73 #define SUN4I_CODEC_DAC_ACTL_PA_VOL (0) 74 #define SUN4I_CODEC_DAC_TUNE (0x14) 75 #define SUN4I_CODEC_DAC_DEBUG (0x18) 76 77 /* Codec ADC digital controls and FIFO registers */ 78 #define SUN4I_CODEC_ADC_FIFOC (0x1c) 79 #define SUN4I_CODEC_ADC_FIFOC_ADC_FS (29) 80 #define SUN4I_CODEC_ADC_FIFOC_EN_AD (28) 81 #define SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE (24) 82 #define SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (8) 83 #define SUN4I_CODEC_ADC_FIFOC_MONO_EN (7) 84 #define SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (6) 85 #define SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN (4) 86 #define SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH (0) 87 #define SUN4I_CODEC_ADC_FIFOS (0x20) 88 #define SUN4I_CODEC_ADC_RXDATA (0x24) 89 90 /* Codec ADC side analog signal controls */ 91 #define SUN4I_CODEC_ADC_ACTL (0x28) 92 #define SUN4I_CODEC_ADC_ACTL_ADC_R_EN (31) 93 #define SUN4I_CODEC_ADC_ACTL_ADC_L_EN (30) 94 #define SUN4I_CODEC_ADC_ACTL_PREG1EN (29) 95 #define SUN4I_CODEC_ADC_ACTL_PREG2EN (28) 96 #define SUN4I_CODEC_ADC_ACTL_VMICEN (27) 97 #define SUN4I_CODEC_ADC_ACTL_VADCG (20) 98 #define SUN4I_CODEC_ADC_ACTL_ADCIS (17) 99 #define SUN4I_CODEC_ADC_ACTL_PA_EN (4) 100 #define SUN4I_CODEC_ADC_ACTL_DDE (3) 101 #define SUN4I_CODEC_ADC_DEBUG (0x2c) 102 103 /* FIFO counters */ 104 #define SUN4I_CODEC_DAC_TXCNT (0x30) 105 #define SUN4I_CODEC_ADC_RXCNT (0x34) 106 107 /* Calibration register (sun7i only) */ 108 #define SUN7I_CODEC_AC_DAC_CAL (0x38) 109 110 /* Microphone controls (sun7i only) */ 111 #define SUN7I_CODEC_AC_MIC_PHONE_CAL (0x3c) 112 113 /* 114 * sun6i specific registers 115 * 116 * sun6i shares the same digital control and FIFO registers as sun4i, 117 * but only the DAC digital controls are at the same offset. The others 118 * have been moved around to accommodate extra analog controls. 119 */ 120 121 /* Codec DAC digital controls and FIFO registers */ 122 #define SUN6I_CODEC_ADC_FIFOC (0x10) 123 #define SUN6I_CODEC_ADC_FIFOC_EN_AD (28) 124 #define SUN6I_CODEC_ADC_FIFOS (0x14) 125 #define SUN6I_CODEC_ADC_RXDATA (0x18) 126 127 /* Output mixer and gain controls */ 128 #define SUN6I_CODEC_OM_DACA_CTRL (0x20) 129 #define SUN6I_CODEC_OM_DACA_CTRL_DACAREN (31) 130 #define SUN6I_CODEC_OM_DACA_CTRL_DACALEN (30) 131 #define SUN6I_CODEC_OM_DACA_CTRL_RMIXEN (29) 132 #define SUN6I_CODEC_OM_DACA_CTRL_LMIXEN (28) 133 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1 (23) 134 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2 (22) 135 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONE (21) 136 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONEP (20) 137 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR (19) 138 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR (18) 139 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL (17) 140 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1 (16) 141 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2 (15) 142 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONE (14) 143 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONEN (13) 144 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL (12) 145 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL (11) 146 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR (10) 147 #define SUN6I_CODEC_OM_DACA_CTRL_RHPIS (9) 148 #define SUN6I_CODEC_OM_DACA_CTRL_LHPIS (8) 149 #define SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE (7) 150 #define SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE (6) 151 #define SUN6I_CODEC_OM_DACA_CTRL_HPVOL (0) 152 #define SUN6I_CODEC_OM_PA_CTRL (0x24) 153 #define SUN6I_CODEC_OM_PA_CTRL_HPPAEN (31) 154 #define SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL (29) 155 #define SUN6I_CODEC_OM_PA_CTRL_COMPTEN (28) 156 #define SUN6I_CODEC_OM_PA_CTRL_MIC1G (15) 157 #define SUN6I_CODEC_OM_PA_CTRL_MIC2G (12) 158 #define SUN6I_CODEC_OM_PA_CTRL_LINEING (9) 159 #define SUN6I_CODEC_OM_PA_CTRL_PHONEG (6) 160 #define SUN6I_CODEC_OM_PA_CTRL_PHONEPG (3) 161 #define SUN6I_CODEC_OM_PA_CTRL_PHONENG (0) 162 163 /* Microphone, line out and phone out controls */ 164 #define SUN6I_CODEC_MIC_CTRL (0x28) 165 #define SUN6I_CODEC_MIC_CTRL_HBIASEN (31) 166 #define SUN6I_CODEC_MIC_CTRL_MBIASEN (30) 167 #define SUN6I_CODEC_MIC_CTRL_MIC1AMPEN (28) 168 #define SUN6I_CODEC_MIC_CTRL_MIC1BOOST (25) 169 #define SUN6I_CODEC_MIC_CTRL_MIC2AMPEN (24) 170 #define SUN6I_CODEC_MIC_CTRL_MIC2BOOST (21) 171 #define SUN6I_CODEC_MIC_CTRL_MIC2SLT (20) 172 #define SUN6I_CODEC_MIC_CTRL_LINEOUTLEN (19) 173 #define SUN6I_CODEC_MIC_CTRL_LINEOUTREN (18) 174 #define SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC (17) 175 #define SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC (16) 176 #define SUN6I_CODEC_MIC_CTRL_LINEOUTVC (11) 177 #define SUN6I_CODEC_MIC_CTRL_PHONEPREG (8) 178 179 /* ADC mixer controls */ 180 #define SUN6I_CODEC_ADC_ACTL (0x2c) 181 #define SUN6I_CODEC_ADC_ACTL_ADCREN (31) 182 #define SUN6I_CODEC_ADC_ACTL_ADCLEN (30) 183 #define SUN6I_CODEC_ADC_ACTL_ADCRG (27) 184 #define SUN6I_CODEC_ADC_ACTL_ADCLG (24) 185 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1 (13) 186 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2 (12) 187 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONE (11) 188 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONEP (10) 189 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR (9) 190 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR (8) 191 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL (7) 192 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1 (6) 193 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2 (5) 194 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONE (4) 195 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONEN (3) 196 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL (2) 197 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL (1) 198 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR (0) 199 200 /* Analog performance tuning controls */ 201 #define SUN6I_CODEC_ADDA_TUNE (0x30) 202 203 /* Calibration controls */ 204 #define SUN6I_CODEC_CALIBRATION (0x34) 205 206 /* FIFO counters */ 207 #define SUN6I_CODEC_DAC_TXCNT (0x40) 208 #define SUN6I_CODEC_ADC_RXCNT (0x44) 209 210 /* headset jack detection and button support registers */ 211 #define SUN6I_CODEC_HMIC_CTL (0x50) 212 #define SUN6I_CODEC_HMIC_DATA (0x54) 213 214 /* TODO sun6i DAP (Digital Audio Processing) bits */ 215 216 /* FIFO counters moved on A23 */ 217 #define SUN8I_A23_CODEC_DAC_TXCNT (0x1c) 218 #define SUN8I_A23_CODEC_ADC_RXCNT (0x20) 219 220 /* TX FIFO moved on H3 */ 221 #define SUN8I_H3_CODEC_DAC_TXDATA (0x20) 222 #define SUN8I_H3_CODEC_DAC_DBG (0x48) 223 #define SUN8I_H3_CODEC_ADC_DBG (0x4c) 224 225 /* TODO H3 DAP (Digital Audio Processing) bits */ 226 227 struct sun4i_codec { 228 struct device *dev; 229 struct regmap *regmap; 230 struct clk *clk_apb; 231 struct clk *clk_module; 232 struct reset_control *rst; 233 struct gpio_desc *gpio_pa; 234 235 /* ADC_FIFOC register is at different offset on different SoCs */ 236 struct regmap_field *reg_adc_fifoc; 237 238 struct snd_dmaengine_dai_dma_data capture_dma_data; 239 struct snd_dmaengine_dai_dma_data playback_dma_data; 240 }; 241 242 static void sun4i_codec_start_playback(struct sun4i_codec *scodec) 243 { 244 /* Flush TX FIFO */ 245 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 246 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH), 247 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); 248 249 /* Enable DAC DRQ */ 250 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 251 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN), 252 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); 253 } 254 255 static void sun4i_codec_stop_playback(struct sun4i_codec *scodec) 256 { 257 /* Disable DAC DRQ */ 258 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 259 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN), 260 0); 261 } 262 263 static void sun4i_codec_start_capture(struct sun4i_codec *scodec) 264 { 265 /* Enable ADC DRQ */ 266 regmap_field_update_bits(scodec->reg_adc_fifoc, 267 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN), 268 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN)); 269 } 270 271 static void sun4i_codec_stop_capture(struct sun4i_codec *scodec) 272 { 273 /* Disable ADC DRQ */ 274 regmap_field_update_bits(scodec->reg_adc_fifoc, 275 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN), 0); 276 } 277 278 static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd, 279 struct snd_soc_dai *dai) 280 { 281 struct snd_soc_pcm_runtime *rtd = substream->private_data; 282 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 283 284 switch (cmd) { 285 case SNDRV_PCM_TRIGGER_START: 286 case SNDRV_PCM_TRIGGER_RESUME: 287 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 288 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 289 sun4i_codec_start_playback(scodec); 290 else 291 sun4i_codec_start_capture(scodec); 292 break; 293 294 case SNDRV_PCM_TRIGGER_STOP: 295 case SNDRV_PCM_TRIGGER_SUSPEND: 296 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 297 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 298 sun4i_codec_stop_playback(scodec); 299 else 300 sun4i_codec_stop_capture(scodec); 301 break; 302 303 default: 304 return -EINVAL; 305 } 306 307 return 0; 308 } 309 310 static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream, 311 struct snd_soc_dai *dai) 312 { 313 struct snd_soc_pcm_runtime *rtd = substream->private_data; 314 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 315 316 317 /* Flush RX FIFO */ 318 regmap_field_update_bits(scodec->reg_adc_fifoc, 319 BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH), 320 BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH)); 321 322 323 /* Set RX FIFO trigger level */ 324 regmap_field_update_bits(scodec->reg_adc_fifoc, 325 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, 326 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL); 327 328 /* 329 * FIXME: Undocumented in the datasheet, but 330 * Allwinner's code mentions that it is related 331 * related to microphone gain 332 */ 333 if (of_device_is_compatible(scodec->dev->of_node, 334 "allwinner,sun4i-a10-codec") || 335 of_device_is_compatible(scodec->dev->of_node, 336 "allwinner,sun7i-a20-codec")) { 337 regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL, 338 0x3 << 25, 339 0x1 << 25); 340 } 341 342 if (of_device_is_compatible(scodec->dev->of_node, 343 "allwinner,sun7i-a20-codec")) 344 /* FIXME: Undocumented bits */ 345 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_TUNE, 346 0x3 << 8, 347 0x1 << 8); 348 349 return 0; 350 } 351 352 static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream, 353 struct snd_soc_dai *dai) 354 { 355 struct snd_soc_pcm_runtime *rtd = substream->private_data; 356 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 357 u32 val; 358 359 /* Flush the TX FIFO */ 360 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 361 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH), 362 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); 363 364 /* Set TX FIFO Empty Trigger Level */ 365 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 366 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL, 367 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL); 368 369 if (substream->runtime->rate > 32000) 370 /* Use 64 bits FIR filter */ 371 val = 0; 372 else 373 /* Use 32 bits FIR filter */ 374 val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION); 375 376 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 377 BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION), 378 val); 379 380 /* Send zeros when we have an underrun */ 381 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 382 BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT), 383 0); 384 385 return 0; 386 }; 387 388 static int sun4i_codec_prepare(struct snd_pcm_substream *substream, 389 struct snd_soc_dai *dai) 390 { 391 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 392 return sun4i_codec_prepare_playback(substream, dai); 393 394 return sun4i_codec_prepare_capture(substream, dai); 395 } 396 397 static unsigned long sun4i_codec_get_mod_freq(struct snd_pcm_hw_params *params) 398 { 399 unsigned int rate = params_rate(params); 400 401 switch (rate) { 402 case 176400: 403 case 88200: 404 case 44100: 405 case 33075: 406 case 22050: 407 case 14700: 408 case 11025: 409 case 7350: 410 return 22579200; 411 412 case 192000: 413 case 96000: 414 case 48000: 415 case 32000: 416 case 24000: 417 case 16000: 418 case 12000: 419 case 8000: 420 return 24576000; 421 422 default: 423 return 0; 424 } 425 } 426 427 static int sun4i_codec_get_hw_rate(struct snd_pcm_hw_params *params) 428 { 429 unsigned int rate = params_rate(params); 430 431 switch (rate) { 432 case 192000: 433 case 176400: 434 return 6; 435 436 case 96000: 437 case 88200: 438 return 7; 439 440 case 48000: 441 case 44100: 442 return 0; 443 444 case 32000: 445 case 33075: 446 return 1; 447 448 case 24000: 449 case 22050: 450 return 2; 451 452 case 16000: 453 case 14700: 454 return 3; 455 456 case 12000: 457 case 11025: 458 return 4; 459 460 case 8000: 461 case 7350: 462 return 5; 463 464 default: 465 return -EINVAL; 466 } 467 } 468 469 static int sun4i_codec_hw_params_capture(struct sun4i_codec *scodec, 470 struct snd_pcm_hw_params *params, 471 unsigned int hwrate) 472 { 473 /* Set ADC sample rate */ 474 regmap_field_update_bits(scodec->reg_adc_fifoc, 475 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS, 476 hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS); 477 478 /* Set the number of channels we want to use */ 479 if (params_channels(params) == 1) 480 regmap_field_update_bits(scodec->reg_adc_fifoc, 481 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN), 482 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); 483 else 484 regmap_field_update_bits(scodec->reg_adc_fifoc, 485 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN), 486 0); 487 488 /* Set the number of sample bits to either 16 or 24 bits */ 489 if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) { 490 regmap_field_update_bits(scodec->reg_adc_fifoc, 491 BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS), 492 BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS)); 493 494 regmap_field_update_bits(scodec->reg_adc_fifoc, 495 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE), 496 0); 497 498 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 499 } else { 500 regmap_field_update_bits(scodec->reg_adc_fifoc, 501 BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS), 502 0); 503 504 /* Fill most significant bits with valid data MSB */ 505 regmap_field_update_bits(scodec->reg_adc_fifoc, 506 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE), 507 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); 508 509 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 510 } 511 512 return 0; 513 } 514 515 static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec, 516 struct snd_pcm_hw_params *params, 517 unsigned int hwrate) 518 { 519 u32 val; 520 521 /* Set DAC sample rate */ 522 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 523 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS, 524 hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS); 525 526 /* Set the number of channels we want to use */ 527 if (params_channels(params) == 1) 528 val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN); 529 else 530 val = 0; 531 532 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 533 BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN), 534 val); 535 536 /* Set the number of sample bits to either 16 or 24 bits */ 537 if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) { 538 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 539 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS), 540 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); 541 542 /* Set TX FIFO mode to padding the LSBs with 0 */ 543 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 544 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE), 545 0); 546 547 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 548 } else { 549 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 550 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS), 551 0); 552 553 /* Set TX FIFO mode to repeat the MSB */ 554 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 555 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE), 556 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); 557 558 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 559 } 560 561 return 0; 562 } 563 564 static int sun4i_codec_hw_params(struct snd_pcm_substream *substream, 565 struct snd_pcm_hw_params *params, 566 struct snd_soc_dai *dai) 567 { 568 struct snd_soc_pcm_runtime *rtd = substream->private_data; 569 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 570 unsigned long clk_freq; 571 int ret, hwrate; 572 573 clk_freq = sun4i_codec_get_mod_freq(params); 574 if (!clk_freq) 575 return -EINVAL; 576 577 ret = clk_set_rate(scodec->clk_module, clk_freq); 578 if (ret) 579 return ret; 580 581 hwrate = sun4i_codec_get_hw_rate(params); 582 if (hwrate < 0) 583 return hwrate; 584 585 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 586 return sun4i_codec_hw_params_playback(scodec, params, 587 hwrate); 588 589 return sun4i_codec_hw_params_capture(scodec, params, 590 hwrate); 591 } 592 593 static int sun4i_codec_startup(struct snd_pcm_substream *substream, 594 struct snd_soc_dai *dai) 595 { 596 struct snd_soc_pcm_runtime *rtd = substream->private_data; 597 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 598 599 /* 600 * Stop issuing DRQ when we have room for less than 16 samples 601 * in our TX FIFO 602 */ 603 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, 604 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT, 605 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT); 606 607 return clk_prepare_enable(scodec->clk_module); 608 } 609 610 static void sun4i_codec_shutdown(struct snd_pcm_substream *substream, 611 struct snd_soc_dai *dai) 612 { 613 struct snd_soc_pcm_runtime *rtd = substream->private_data; 614 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); 615 616 clk_disable_unprepare(scodec->clk_module); 617 } 618 619 static const struct snd_soc_dai_ops sun4i_codec_dai_ops = { 620 .startup = sun4i_codec_startup, 621 .shutdown = sun4i_codec_shutdown, 622 .trigger = sun4i_codec_trigger, 623 .hw_params = sun4i_codec_hw_params, 624 .prepare = sun4i_codec_prepare, 625 }; 626 627 static struct snd_soc_dai_driver sun4i_codec_dai = { 628 .name = "Codec", 629 .ops = &sun4i_codec_dai_ops, 630 .playback = { 631 .stream_name = "Codec Playback", 632 .channels_min = 1, 633 .channels_max = 2, 634 .rate_min = 8000, 635 .rate_max = 192000, 636 .rates = SNDRV_PCM_RATE_8000_48000 | 637 SNDRV_PCM_RATE_96000 | 638 SNDRV_PCM_RATE_192000, 639 .formats = SNDRV_PCM_FMTBIT_S16_LE | 640 SNDRV_PCM_FMTBIT_S32_LE, 641 .sig_bits = 24, 642 }, 643 .capture = { 644 .stream_name = "Codec Capture", 645 .channels_min = 1, 646 .channels_max = 2, 647 .rate_min = 8000, 648 .rate_max = 192000, 649 .rates = SNDRV_PCM_RATE_8000_48000 | 650 SNDRV_PCM_RATE_96000 | 651 SNDRV_PCM_RATE_192000 | 652 SNDRV_PCM_RATE_KNOT, 653 .formats = SNDRV_PCM_FMTBIT_S16_LE | 654 SNDRV_PCM_FMTBIT_S32_LE, 655 .sig_bits = 24, 656 }, 657 }; 658 659 /*** sun4i Codec ***/ 660 static const struct snd_kcontrol_new sun4i_codec_pa_mute = 661 SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL, 662 SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0); 663 664 static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1); 665 666 static const struct snd_kcontrol_new sun4i_codec_controls[] = { 667 SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL, 668 SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0, 669 sun4i_codec_pa_volume_scale), 670 }; 671 672 static const struct snd_kcontrol_new sun4i_codec_left_mixer_controls[] = { 673 SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL, 674 SUN4I_CODEC_DAC_ACTL_LDACLMIXS, 1, 0), 675 }; 676 677 static const struct snd_kcontrol_new sun4i_codec_right_mixer_controls[] = { 678 SOC_DAPM_SINGLE("Right DAC Playback Switch", SUN4I_CODEC_DAC_ACTL, 679 SUN4I_CODEC_DAC_ACTL_RDACRMIXS, 1, 0), 680 SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL, 681 SUN4I_CODEC_DAC_ACTL_LDACRMIXS, 1, 0), 682 }; 683 684 static const struct snd_kcontrol_new sun4i_codec_pa_mixer_controls[] = { 685 SOC_DAPM_SINGLE("DAC Playback Switch", SUN4I_CODEC_DAC_ACTL, 686 SUN4I_CODEC_DAC_ACTL_DACPAS, 1, 0), 687 SOC_DAPM_SINGLE("Mixer Playback Switch", SUN4I_CODEC_DAC_ACTL, 688 SUN4I_CODEC_DAC_ACTL_MIXPAS, 1, 0), 689 }; 690 691 static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = { 692 /* Digital parts of the ADCs */ 693 SND_SOC_DAPM_SUPPLY("ADC", SUN4I_CODEC_ADC_FIFOC, 694 SUN4I_CODEC_ADC_FIFOC_EN_AD, 0, 695 NULL, 0), 696 697 /* Digital parts of the DACs */ 698 SND_SOC_DAPM_SUPPLY("DAC", SUN4I_CODEC_DAC_DPC, 699 SUN4I_CODEC_DAC_DPC_EN_DA, 0, 700 NULL, 0), 701 702 /* Analog parts of the ADCs */ 703 SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL, 704 SUN4I_CODEC_ADC_ACTL_ADC_L_EN, 0), 705 SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL, 706 SUN4I_CODEC_ADC_ACTL_ADC_R_EN, 0), 707 708 /* Analog parts of the DACs */ 709 SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL, 710 SUN4I_CODEC_DAC_ACTL_DACAENL, 0), 711 SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL, 712 SUN4I_CODEC_DAC_ACTL_DACAENR, 0), 713 714 /* Mixers */ 715 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, 716 sun4i_codec_left_mixer_controls, 717 ARRAY_SIZE(sun4i_codec_left_mixer_controls)), 718 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, 719 sun4i_codec_right_mixer_controls, 720 ARRAY_SIZE(sun4i_codec_right_mixer_controls)), 721 722 /* Global Mixer Enable */ 723 SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL, 724 SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0), 725 726 /* VMIC */ 727 SND_SOC_DAPM_SUPPLY("VMIC", SUN4I_CODEC_ADC_ACTL, 728 SUN4I_CODEC_ADC_ACTL_VMICEN, 0, NULL, 0), 729 730 /* Mic Pre-Amplifiers */ 731 SND_SOC_DAPM_PGA("MIC1 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL, 732 SUN4I_CODEC_ADC_ACTL_PREG1EN, 0, NULL, 0), 733 734 /* Power Amplifier */ 735 SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL, 736 SUN4I_CODEC_ADC_ACTL_PA_EN, 0, 737 sun4i_codec_pa_mixer_controls, 738 ARRAY_SIZE(sun4i_codec_pa_mixer_controls)), 739 SND_SOC_DAPM_SWITCH("Power Amplifier Mute", SND_SOC_NOPM, 0, 0, 740 &sun4i_codec_pa_mute), 741 742 SND_SOC_DAPM_INPUT("Mic1"), 743 744 SND_SOC_DAPM_OUTPUT("HP Right"), 745 SND_SOC_DAPM_OUTPUT("HP Left"), 746 }; 747 748 static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = { 749 /* Left ADC / DAC Routes */ 750 { "Left ADC", NULL, "ADC" }, 751 { "Left DAC", NULL, "DAC" }, 752 753 /* Right ADC / DAC Routes */ 754 { "Right ADC", NULL, "ADC" }, 755 { "Right DAC", NULL, "DAC" }, 756 757 /* Right Mixer Routes */ 758 { "Right Mixer", NULL, "Mixer Enable" }, 759 { "Right Mixer", "Left DAC Playback Switch", "Left DAC" }, 760 { "Right Mixer", "Right DAC Playback Switch", "Right DAC" }, 761 762 /* Left Mixer Routes */ 763 { "Left Mixer", NULL, "Mixer Enable" }, 764 { "Left Mixer", "Left DAC Playback Switch", "Left DAC" }, 765 766 /* Power Amplifier Routes */ 767 { "Power Amplifier", "Mixer Playback Switch", "Left Mixer" }, 768 { "Power Amplifier", "Mixer Playback Switch", "Right Mixer" }, 769 { "Power Amplifier", "DAC Playback Switch", "Left DAC" }, 770 { "Power Amplifier", "DAC Playback Switch", "Right DAC" }, 771 772 /* Headphone Output Routes */ 773 { "Power Amplifier Mute", "Switch", "Power Amplifier" }, 774 { "HP Right", NULL, "Power Amplifier Mute" }, 775 { "HP Left", NULL, "Power Amplifier Mute" }, 776 777 /* Mic1 Routes */ 778 { "Left ADC", NULL, "MIC1 Pre-Amplifier" }, 779 { "Right ADC", NULL, "MIC1 Pre-Amplifier" }, 780 { "MIC1 Pre-Amplifier", NULL, "Mic1"}, 781 { "Mic1", NULL, "VMIC" }, 782 }; 783 784 static const struct snd_soc_codec_driver sun4i_codec_codec = { 785 .component_driver = { 786 .controls = sun4i_codec_controls, 787 .num_controls = ARRAY_SIZE(sun4i_codec_controls), 788 .dapm_widgets = sun4i_codec_codec_dapm_widgets, 789 .num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets), 790 .dapm_routes = sun4i_codec_codec_dapm_routes, 791 .num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes), 792 }, 793 }; 794 795 /*** sun6i Codec ***/ 796 797 /* mixer controls */ 798 static const struct snd_kcontrol_new sun6i_codec_mixer_controls[] = { 799 SOC_DAPM_DOUBLE("DAC Playback Switch", 800 SUN6I_CODEC_OM_DACA_CTRL, 801 SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL, 802 SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR, 1, 0), 803 SOC_DAPM_DOUBLE("DAC Reversed Playback Switch", 804 SUN6I_CODEC_OM_DACA_CTRL, 805 SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR, 806 SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL, 1, 0), 807 SOC_DAPM_DOUBLE("Line In Playback Switch", 808 SUN6I_CODEC_OM_DACA_CTRL, 809 SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL, 810 SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR, 1, 0), 811 SOC_DAPM_DOUBLE("Mic1 Playback Switch", 812 SUN6I_CODEC_OM_DACA_CTRL, 813 SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1, 814 SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1, 1, 0), 815 SOC_DAPM_DOUBLE("Mic2 Playback Switch", 816 SUN6I_CODEC_OM_DACA_CTRL, 817 SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2, 818 SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2, 1, 0), 819 }; 820 821 /* ADC mixer controls */ 822 static const struct snd_kcontrol_new sun6i_codec_adc_mixer_controls[] = { 823 SOC_DAPM_DOUBLE("Mixer Capture Switch", 824 SUN6I_CODEC_ADC_ACTL, 825 SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL, 826 SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR, 1, 0), 827 SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch", 828 SUN6I_CODEC_ADC_ACTL, 829 SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR, 830 SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL, 1, 0), 831 SOC_DAPM_DOUBLE("Line In Capture Switch", 832 SUN6I_CODEC_ADC_ACTL, 833 SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL, 834 SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR, 1, 0), 835 SOC_DAPM_DOUBLE("Mic1 Capture Switch", 836 SUN6I_CODEC_ADC_ACTL, 837 SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1, 838 SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1, 1, 0), 839 SOC_DAPM_DOUBLE("Mic2 Capture Switch", 840 SUN6I_CODEC_ADC_ACTL, 841 SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2, 842 SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2, 1, 0), 843 }; 844 845 /* headphone controls */ 846 static const char * const sun6i_codec_hp_src_enum_text[] = { 847 "DAC", "Mixer", 848 }; 849 850 static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum, 851 SUN6I_CODEC_OM_DACA_CTRL, 852 SUN6I_CODEC_OM_DACA_CTRL_LHPIS, 853 SUN6I_CODEC_OM_DACA_CTRL_RHPIS, 854 sun6i_codec_hp_src_enum_text); 855 856 static const struct snd_kcontrol_new sun6i_codec_hp_src[] = { 857 SOC_DAPM_ENUM("Headphone Source Playback Route", 858 sun6i_codec_hp_src_enum), 859 }; 860 861 /* microphone controls */ 862 static const char * const sun6i_codec_mic2_src_enum_text[] = { 863 "Mic2", "Mic3", 864 }; 865 866 static SOC_ENUM_SINGLE_DECL(sun6i_codec_mic2_src_enum, 867 SUN6I_CODEC_MIC_CTRL, 868 SUN6I_CODEC_MIC_CTRL_MIC2SLT, 869 sun6i_codec_mic2_src_enum_text); 870 871 static const struct snd_kcontrol_new sun6i_codec_mic2_src[] = { 872 SOC_DAPM_ENUM("Mic2 Amplifier Source Route", 873 sun6i_codec_mic2_src_enum), 874 }; 875 876 /* line out controls */ 877 static const char * const sun6i_codec_lineout_src_enum_text[] = { 878 "Stereo", "Mono Differential", 879 }; 880 881 static SOC_ENUM_DOUBLE_DECL(sun6i_codec_lineout_src_enum, 882 SUN6I_CODEC_MIC_CTRL, 883 SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC, 884 SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC, 885 sun6i_codec_lineout_src_enum_text); 886 887 static const struct snd_kcontrol_new sun6i_codec_lineout_src[] = { 888 SOC_DAPM_ENUM("Line Out Source Playback Route", 889 sun6i_codec_lineout_src_enum), 890 }; 891 892 /* volume / mute controls */ 893 static const DECLARE_TLV_DB_SCALE(sun6i_codec_dvol_scale, -7308, 116, 0); 894 static const DECLARE_TLV_DB_SCALE(sun6i_codec_hp_vol_scale, -6300, 100, 1); 895 static const DECLARE_TLV_DB_SCALE(sun6i_codec_out_mixer_pregain_scale, 896 -450, 150, 0); 897 static const DECLARE_TLV_DB_RANGE(sun6i_codec_lineout_vol_scale, 898 0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 899 2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0), 900 ); 901 static const DECLARE_TLV_DB_RANGE(sun6i_codec_mic_gain_scale, 902 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 903 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0), 904 ); 905 906 static const struct snd_kcontrol_new sun6i_codec_codec_widgets[] = { 907 SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC, 908 SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1, 909 sun6i_codec_dvol_scale), 910 SOC_SINGLE_TLV("Headphone Playback Volume", 911 SUN6I_CODEC_OM_DACA_CTRL, 912 SUN6I_CODEC_OM_DACA_CTRL_HPVOL, 0x3f, 0, 913 sun6i_codec_hp_vol_scale), 914 SOC_SINGLE_TLV("Line Out Playback Volume", 915 SUN6I_CODEC_MIC_CTRL, 916 SUN6I_CODEC_MIC_CTRL_LINEOUTVC, 0x1f, 0, 917 sun6i_codec_lineout_vol_scale), 918 SOC_DOUBLE("Headphone Playback Switch", 919 SUN6I_CODEC_OM_DACA_CTRL, 920 SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE, 921 SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE, 1, 0), 922 SOC_DOUBLE("Line Out Playback Switch", 923 SUN6I_CODEC_MIC_CTRL, 924 SUN6I_CODEC_MIC_CTRL_LINEOUTLEN, 925 SUN6I_CODEC_MIC_CTRL_LINEOUTREN, 1, 0), 926 /* Mixer pre-gains */ 927 SOC_SINGLE_TLV("Line In Playback Volume", 928 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_LINEING, 929 0x7, 0, sun6i_codec_out_mixer_pregain_scale), 930 SOC_SINGLE_TLV("Mic1 Playback Volume", 931 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC1G, 932 0x7, 0, sun6i_codec_out_mixer_pregain_scale), 933 SOC_SINGLE_TLV("Mic2 Playback Volume", 934 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC2G, 935 0x7, 0, sun6i_codec_out_mixer_pregain_scale), 936 937 /* Microphone Amp boost gains */ 938 SOC_SINGLE_TLV("Mic1 Boost Volume", SUN6I_CODEC_MIC_CTRL, 939 SUN6I_CODEC_MIC_CTRL_MIC1BOOST, 0x7, 0, 940 sun6i_codec_mic_gain_scale), 941 SOC_SINGLE_TLV("Mic2 Boost Volume", SUN6I_CODEC_MIC_CTRL, 942 SUN6I_CODEC_MIC_CTRL_MIC2BOOST, 0x7, 0, 943 sun6i_codec_mic_gain_scale), 944 SOC_DOUBLE_TLV("ADC Capture Volume", 945 SUN6I_CODEC_ADC_ACTL, SUN6I_CODEC_ADC_ACTL_ADCLG, 946 SUN6I_CODEC_ADC_ACTL_ADCRG, 0x7, 0, 947 sun6i_codec_out_mixer_pregain_scale), 948 }; 949 950 static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = { 951 /* Microphone inputs */ 952 SND_SOC_DAPM_INPUT("MIC1"), 953 SND_SOC_DAPM_INPUT("MIC2"), 954 SND_SOC_DAPM_INPUT("MIC3"), 955 956 /* Microphone Bias */ 957 SND_SOC_DAPM_SUPPLY("HBIAS", SUN6I_CODEC_MIC_CTRL, 958 SUN6I_CODEC_MIC_CTRL_HBIASEN, 0, NULL, 0), 959 SND_SOC_DAPM_SUPPLY("MBIAS", SUN6I_CODEC_MIC_CTRL, 960 SUN6I_CODEC_MIC_CTRL_MBIASEN, 0, NULL, 0), 961 962 /* Mic input path */ 963 SND_SOC_DAPM_MUX("Mic2 Amplifier Source Route", 964 SND_SOC_NOPM, 0, 0, sun6i_codec_mic2_src), 965 SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN6I_CODEC_MIC_CTRL, 966 SUN6I_CODEC_MIC_CTRL_MIC1AMPEN, 0, NULL, 0), 967 SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN6I_CODEC_MIC_CTRL, 968 SUN6I_CODEC_MIC_CTRL_MIC2AMPEN, 0, NULL, 0), 969 970 /* Line In */ 971 SND_SOC_DAPM_INPUT("LINEIN"), 972 973 /* Digital parts of the ADCs */ 974 SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC, 975 SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, 976 NULL, 0), 977 978 /* Analog parts of the ADCs */ 979 SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL, 980 SUN6I_CODEC_ADC_ACTL_ADCLEN, 0), 981 SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL, 982 SUN6I_CODEC_ADC_ACTL_ADCREN, 0), 983 984 /* ADC Mixers */ 985 SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 986 sun6i_codec_adc_mixer_controls), 987 SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 988 sun6i_codec_adc_mixer_controls), 989 990 /* Digital parts of the DACs */ 991 SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC, 992 SUN4I_CODEC_DAC_DPC_EN_DA, 0, 993 NULL, 0), 994 995 /* Analog parts of the DACs */ 996 SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", 997 SUN6I_CODEC_OM_DACA_CTRL, 998 SUN6I_CODEC_OM_DACA_CTRL_DACALEN, 0), 999 SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", 1000 SUN6I_CODEC_OM_DACA_CTRL, 1001 SUN6I_CODEC_OM_DACA_CTRL_DACAREN, 0), 1002 1003 /* Mixers */ 1004 SOC_MIXER_ARRAY("Left Mixer", SUN6I_CODEC_OM_DACA_CTRL, 1005 SUN6I_CODEC_OM_DACA_CTRL_LMIXEN, 0, 1006 sun6i_codec_mixer_controls), 1007 SOC_MIXER_ARRAY("Right Mixer", SUN6I_CODEC_OM_DACA_CTRL, 1008 SUN6I_CODEC_OM_DACA_CTRL_RMIXEN, 0, 1009 sun6i_codec_mixer_controls), 1010 1011 /* Headphone output path */ 1012 SND_SOC_DAPM_MUX("Headphone Source Playback Route", 1013 SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src), 1014 SND_SOC_DAPM_OUT_DRV("Headphone Amp", SUN6I_CODEC_OM_PA_CTRL, 1015 SUN6I_CODEC_OM_PA_CTRL_HPPAEN, 0, NULL, 0), 1016 SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN6I_CODEC_OM_PA_CTRL, 1017 SUN6I_CODEC_OM_PA_CTRL_COMPTEN, 0, NULL, 0), 1018 SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN6I_CODEC_OM_PA_CTRL, 1019 SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL, 0x3, 0x3, 0), 1020 SND_SOC_DAPM_OUTPUT("HP"), 1021 1022 /* Line Out path */ 1023 SND_SOC_DAPM_MUX("Line Out Source Playback Route", 1024 SND_SOC_NOPM, 0, 0, sun6i_codec_lineout_src), 1025 SND_SOC_DAPM_OUTPUT("LINEOUT"), 1026 }; 1027 1028 static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = { 1029 /* DAC Routes */ 1030 { "Left DAC", NULL, "DAC Enable" }, 1031 { "Right DAC", NULL, "DAC Enable" }, 1032 1033 /* Microphone Routes */ 1034 { "Mic1 Amplifier", NULL, "MIC1"}, 1035 { "Mic2 Amplifier Source Route", "Mic2", "MIC2" }, 1036 { "Mic2 Amplifier Source Route", "Mic3", "MIC3" }, 1037 { "Mic2 Amplifier", NULL, "Mic2 Amplifier Source Route"}, 1038 1039 /* Left Mixer Routes */ 1040 { "Left Mixer", "DAC Playback Switch", "Left DAC" }, 1041 { "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" }, 1042 { "Left Mixer", "Line In Playback Switch", "LINEIN" }, 1043 { "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" }, 1044 { "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" }, 1045 1046 /* Right Mixer Routes */ 1047 { "Right Mixer", "DAC Playback Switch", "Right DAC" }, 1048 { "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" }, 1049 { "Right Mixer", "Line In Playback Switch", "LINEIN" }, 1050 { "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" }, 1051 { "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" }, 1052 1053 /* Left ADC Mixer Routes */ 1054 { "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" }, 1055 { "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" }, 1056 { "Left ADC Mixer", "Line In Capture Switch", "LINEIN" }, 1057 { "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" }, 1058 { "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" }, 1059 1060 /* Right ADC Mixer Routes */ 1061 { "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" }, 1062 { "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" }, 1063 { "Right ADC Mixer", "Line In Capture Switch", "LINEIN" }, 1064 { "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" }, 1065 { "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" }, 1066 1067 /* Headphone Routes */ 1068 { "Headphone Source Playback Route", "DAC", "Left DAC" }, 1069 { "Headphone Source Playback Route", "DAC", "Right DAC" }, 1070 { "Headphone Source Playback Route", "Mixer", "Left Mixer" }, 1071 { "Headphone Source Playback Route", "Mixer", "Right Mixer" }, 1072 { "Headphone Amp", NULL, "Headphone Source Playback Route" }, 1073 { "HP", NULL, "Headphone Amp" }, 1074 { "HPCOM", NULL, "HPCOM Protection" }, 1075 1076 /* Line Out Routes */ 1077 { "Line Out Source Playback Route", "Stereo", "Left Mixer" }, 1078 { "Line Out Source Playback Route", "Stereo", "Right Mixer" }, 1079 { "Line Out Source Playback Route", "Mono Differential", "Left Mixer" }, 1080 { "Line Out Source Playback Route", "Mono Differential", "Right Mixer" }, 1081 { "LINEOUT", NULL, "Line Out Source Playback Route" }, 1082 1083 /* ADC Routes */ 1084 { "Left ADC", NULL, "ADC Enable" }, 1085 { "Right ADC", NULL, "ADC Enable" }, 1086 { "Left ADC", NULL, "Left ADC Mixer" }, 1087 { "Right ADC", NULL, "Right ADC Mixer" }, 1088 }; 1089 1090 static const struct snd_soc_codec_driver sun6i_codec_codec = { 1091 .component_driver = { 1092 .controls = sun6i_codec_codec_widgets, 1093 .num_controls = ARRAY_SIZE(sun6i_codec_codec_widgets), 1094 .dapm_widgets = sun6i_codec_codec_dapm_widgets, 1095 .num_dapm_widgets = ARRAY_SIZE(sun6i_codec_codec_dapm_widgets), 1096 .dapm_routes = sun6i_codec_codec_dapm_routes, 1097 .num_dapm_routes = ARRAY_SIZE(sun6i_codec_codec_dapm_routes), 1098 }, 1099 }; 1100 1101 /* sun8i A23 codec */ 1102 static const struct snd_kcontrol_new sun8i_a23_codec_codec_controls[] = { 1103 SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC, 1104 SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1, 1105 sun6i_codec_dvol_scale), 1106 }; 1107 1108 static const struct snd_soc_dapm_widget sun8i_a23_codec_codec_widgets[] = { 1109 /* Digital parts of the ADCs */ 1110 SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC, 1111 SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0), 1112 /* Digital parts of the DACs */ 1113 SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC, 1114 SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0), 1115 1116 }; 1117 1118 static const struct snd_soc_codec_driver sun8i_a23_codec_codec = { 1119 .component_driver = { 1120 .controls = sun8i_a23_codec_codec_controls, 1121 .num_controls = ARRAY_SIZE(sun8i_a23_codec_codec_controls), 1122 .dapm_widgets = sun8i_a23_codec_codec_widgets, 1123 .num_dapm_widgets = ARRAY_SIZE(sun8i_a23_codec_codec_widgets), 1124 }, 1125 }; 1126 1127 static const struct snd_soc_component_driver sun4i_codec_component = { 1128 .name = "sun4i-codec", 1129 }; 1130 1131 #define SUN4I_CODEC_RATES SNDRV_PCM_RATE_8000_192000 1132 #define SUN4I_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 1133 SNDRV_PCM_FMTBIT_S32_LE) 1134 1135 static int sun4i_codec_dai_probe(struct snd_soc_dai *dai) 1136 { 1137 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1138 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card); 1139 1140 snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data, 1141 &scodec->capture_dma_data); 1142 1143 return 0; 1144 } 1145 1146 static struct snd_soc_dai_driver dummy_cpu_dai = { 1147 .name = "sun4i-codec-cpu-dai", 1148 .probe = sun4i_codec_dai_probe, 1149 .playback = { 1150 .stream_name = "Playback", 1151 .channels_min = 1, 1152 .channels_max = 2, 1153 .rates = SUN4I_CODEC_RATES, 1154 .formats = SUN4I_CODEC_FORMATS, 1155 .sig_bits = 24, 1156 }, 1157 .capture = { 1158 .stream_name = "Capture", 1159 .channels_min = 1, 1160 .channels_max = 2, 1161 .rates = SUN4I_CODEC_RATES, 1162 .formats = SUN4I_CODEC_FORMATS, 1163 .sig_bits = 24, 1164 }, 1165 }; 1166 1167 static struct snd_soc_dai_link *sun4i_codec_create_link(struct device *dev, 1168 int *num_links) 1169 { 1170 struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link), 1171 GFP_KERNEL); 1172 if (!link) 1173 return NULL; 1174 1175 link->name = "cdc"; 1176 link->stream_name = "CDC PCM"; 1177 link->codec_dai_name = "Codec"; 1178 link->cpu_dai_name = dev_name(dev); 1179 link->codec_name = dev_name(dev); 1180 link->platform_name = dev_name(dev); 1181 link->dai_fmt = SND_SOC_DAIFMT_I2S; 1182 1183 *num_links = 1; 1184 1185 return link; 1186 }; 1187 1188 static int sun4i_codec_spk_event(struct snd_soc_dapm_widget *w, 1189 struct snd_kcontrol *k, int event) 1190 { 1191 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card); 1192 1193 gpiod_set_value_cansleep(scodec->gpio_pa, 1194 !!SND_SOC_DAPM_EVENT_ON(event)); 1195 1196 return 0; 1197 } 1198 1199 static const struct snd_soc_dapm_widget sun4i_codec_card_dapm_widgets[] = { 1200 SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event), 1201 }; 1202 1203 static const struct snd_soc_dapm_route sun4i_codec_card_dapm_routes[] = { 1204 { "Speaker", NULL, "HP Right" }, 1205 { "Speaker", NULL, "HP Left" }, 1206 }; 1207 1208 static struct snd_soc_card *sun4i_codec_create_card(struct device *dev) 1209 { 1210 struct snd_soc_card *card; 1211 1212 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1213 if (!card) 1214 return ERR_PTR(-ENOMEM); 1215 1216 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1217 if (!card->dai_link) 1218 return ERR_PTR(-ENOMEM); 1219 1220 card->dev = dev; 1221 card->name = "sun4i-codec"; 1222 card->dapm_widgets = sun4i_codec_card_dapm_widgets; 1223 card->num_dapm_widgets = ARRAY_SIZE(sun4i_codec_card_dapm_widgets); 1224 card->dapm_routes = sun4i_codec_card_dapm_routes; 1225 card->num_dapm_routes = ARRAY_SIZE(sun4i_codec_card_dapm_routes); 1226 1227 return card; 1228 }; 1229 1230 static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = { 1231 SND_SOC_DAPM_HP("Headphone", NULL), 1232 SND_SOC_DAPM_LINE("Line In", NULL), 1233 SND_SOC_DAPM_LINE("Line Out", NULL), 1234 SND_SOC_DAPM_MIC("Headset Mic", NULL), 1235 SND_SOC_DAPM_MIC("Mic", NULL), 1236 SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event), 1237 }; 1238 1239 static struct snd_soc_card *sun6i_codec_create_card(struct device *dev) 1240 { 1241 struct snd_soc_card *card; 1242 int ret; 1243 1244 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1245 if (!card) 1246 return ERR_PTR(-ENOMEM); 1247 1248 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1249 if (!card->dai_link) 1250 return ERR_PTR(-ENOMEM); 1251 1252 card->dev = dev; 1253 card->name = "A31 Audio Codec"; 1254 card->dapm_widgets = sun6i_codec_card_dapm_widgets; 1255 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); 1256 card->fully_routed = true; 1257 1258 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); 1259 if (ret) 1260 dev_warn(dev, "failed to parse audio-routing: %d\n", ret); 1261 1262 return card; 1263 }; 1264 1265 /* Connect digital side enables to analog side widgets */ 1266 static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = { 1267 /* ADC Routes */ 1268 { "Left ADC", NULL, "ADC Enable" }, 1269 { "Right ADC", NULL, "ADC Enable" }, 1270 { "Codec Capture", NULL, "Left ADC" }, 1271 { "Codec Capture", NULL, "Right ADC" }, 1272 1273 /* DAC Routes */ 1274 { "Left DAC", NULL, "DAC Enable" }, 1275 { "Right DAC", NULL, "DAC Enable" }, 1276 { "Left DAC", NULL, "Codec Playback" }, 1277 { "Right DAC", NULL, "Codec Playback" }, 1278 }; 1279 1280 static struct snd_soc_aux_dev aux_dev = { 1281 .name = "Codec Analog Controls", 1282 }; 1283 1284 static struct snd_soc_card *sun8i_a23_codec_create_card(struct device *dev) 1285 { 1286 struct snd_soc_card *card; 1287 int ret; 1288 1289 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1290 if (!card) 1291 return ERR_PTR(-ENOMEM); 1292 1293 aux_dev.codec_of_node = of_parse_phandle(dev->of_node, 1294 "allwinner,codec-analog-controls", 1295 0); 1296 if (!aux_dev.codec_of_node) { 1297 dev_err(dev, "Can't find analog controls for codec.\n"); 1298 return ERR_PTR(-EINVAL); 1299 }; 1300 1301 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1302 if (!card->dai_link) 1303 return ERR_PTR(-ENOMEM); 1304 1305 card->dev = dev; 1306 card->name = "A23 Audio Codec"; 1307 card->dapm_widgets = sun6i_codec_card_dapm_widgets; 1308 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); 1309 card->dapm_routes = sun8i_codec_card_routes; 1310 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes); 1311 card->aux_dev = &aux_dev; 1312 card->num_aux_devs = 1; 1313 card->fully_routed = true; 1314 1315 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); 1316 if (ret) 1317 dev_warn(dev, "failed to parse audio-routing: %d\n", ret); 1318 1319 return card; 1320 }; 1321 1322 static struct snd_soc_card *sun8i_h3_codec_create_card(struct device *dev) 1323 { 1324 struct snd_soc_card *card; 1325 int ret; 1326 1327 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1328 if (!card) 1329 return ERR_PTR(-ENOMEM); 1330 1331 aux_dev.codec_of_node = of_parse_phandle(dev->of_node, 1332 "allwinner,codec-analog-controls", 1333 0); 1334 if (!aux_dev.codec_of_node) { 1335 dev_err(dev, "Can't find analog controls for codec.\n"); 1336 return ERR_PTR(-EINVAL); 1337 }; 1338 1339 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1340 if (!card->dai_link) 1341 return ERR_PTR(-ENOMEM); 1342 1343 card->dev = dev; 1344 card->name = "H3 Audio Codec"; 1345 card->dapm_widgets = sun6i_codec_card_dapm_widgets; 1346 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); 1347 card->dapm_routes = sun8i_codec_card_routes; 1348 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes); 1349 card->aux_dev = &aux_dev; 1350 card->num_aux_devs = 1; 1351 card->fully_routed = true; 1352 1353 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); 1354 if (ret) 1355 dev_warn(dev, "failed to parse audio-routing: %d\n", ret); 1356 1357 return card; 1358 }; 1359 1360 static struct snd_soc_card *sun8i_v3s_codec_create_card(struct device *dev) 1361 { 1362 struct snd_soc_card *card; 1363 int ret; 1364 1365 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); 1366 if (!card) 1367 return ERR_PTR(-ENOMEM); 1368 1369 aux_dev.codec_of_node = of_parse_phandle(dev->of_node, 1370 "allwinner,codec-analog-controls", 1371 0); 1372 if (!aux_dev.codec_of_node) { 1373 dev_err(dev, "Can't find analog controls for codec.\n"); 1374 return ERR_PTR(-EINVAL); 1375 }; 1376 1377 card->dai_link = sun4i_codec_create_link(dev, &card->num_links); 1378 if (!card->dai_link) 1379 return ERR_PTR(-ENOMEM); 1380 1381 card->dev = dev; 1382 card->name = "V3s Audio Codec"; 1383 card->dapm_widgets = sun6i_codec_card_dapm_widgets; 1384 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); 1385 card->dapm_routes = sun8i_codec_card_routes; 1386 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes); 1387 card->aux_dev = &aux_dev; 1388 card->num_aux_devs = 1; 1389 card->fully_routed = true; 1390 1391 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); 1392 if (ret) 1393 dev_warn(dev, "failed to parse audio-routing: %d\n", ret); 1394 1395 return card; 1396 }; 1397 1398 static const struct regmap_config sun4i_codec_regmap_config = { 1399 .reg_bits = 32, 1400 .reg_stride = 4, 1401 .val_bits = 32, 1402 .max_register = SUN4I_CODEC_ADC_RXCNT, 1403 }; 1404 1405 static const struct regmap_config sun6i_codec_regmap_config = { 1406 .reg_bits = 32, 1407 .reg_stride = 4, 1408 .val_bits = 32, 1409 .max_register = SUN6I_CODEC_HMIC_DATA, 1410 }; 1411 1412 static const struct regmap_config sun7i_codec_regmap_config = { 1413 .reg_bits = 32, 1414 .reg_stride = 4, 1415 .val_bits = 32, 1416 .max_register = SUN7I_CODEC_AC_MIC_PHONE_CAL, 1417 }; 1418 1419 static const struct regmap_config sun8i_a23_codec_regmap_config = { 1420 .reg_bits = 32, 1421 .reg_stride = 4, 1422 .val_bits = 32, 1423 .max_register = SUN8I_A23_CODEC_ADC_RXCNT, 1424 }; 1425 1426 static const struct regmap_config sun8i_h3_codec_regmap_config = { 1427 .reg_bits = 32, 1428 .reg_stride = 4, 1429 .val_bits = 32, 1430 .max_register = SUN8I_H3_CODEC_ADC_DBG, 1431 }; 1432 1433 static const struct regmap_config sun8i_v3s_codec_regmap_config = { 1434 .reg_bits = 32, 1435 .reg_stride = 4, 1436 .val_bits = 32, 1437 .max_register = SUN8I_H3_CODEC_ADC_DBG, 1438 }; 1439 1440 struct sun4i_codec_quirks { 1441 const struct regmap_config *regmap_config; 1442 const struct snd_soc_codec_driver *codec; 1443 struct snd_soc_card * (*create_card)(struct device *dev); 1444 struct reg_field reg_adc_fifoc; /* used for regmap_field */ 1445 unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */ 1446 unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */ 1447 bool has_reset; 1448 }; 1449 1450 static const struct sun4i_codec_quirks sun4i_codec_quirks = { 1451 .regmap_config = &sun4i_codec_regmap_config, 1452 .codec = &sun4i_codec_codec, 1453 .create_card = sun4i_codec_create_card, 1454 .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31), 1455 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, 1456 .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, 1457 }; 1458 1459 static const struct sun4i_codec_quirks sun6i_a31_codec_quirks = { 1460 .regmap_config = &sun6i_codec_regmap_config, 1461 .codec = &sun6i_codec_codec, 1462 .create_card = sun6i_codec_create_card, 1463 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), 1464 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, 1465 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, 1466 .has_reset = true, 1467 }; 1468 1469 static const struct sun4i_codec_quirks sun7i_codec_quirks = { 1470 .regmap_config = &sun7i_codec_regmap_config, 1471 .codec = &sun4i_codec_codec, 1472 .create_card = sun4i_codec_create_card, 1473 .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31), 1474 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, 1475 .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, 1476 }; 1477 1478 static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = { 1479 .regmap_config = &sun8i_a23_codec_regmap_config, 1480 .codec = &sun8i_a23_codec_codec, 1481 .create_card = sun8i_a23_codec_create_card, 1482 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), 1483 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, 1484 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, 1485 .has_reset = true, 1486 }; 1487 1488 static const struct sun4i_codec_quirks sun8i_h3_codec_quirks = { 1489 .regmap_config = &sun8i_h3_codec_regmap_config, 1490 /* 1491 * TODO Share the codec structure with A23 for now. 1492 * This should be split out when adding digital audio 1493 * processing support for the H3. 1494 */ 1495 .codec = &sun8i_a23_codec_codec, 1496 .create_card = sun8i_h3_codec_create_card, 1497 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), 1498 .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, 1499 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, 1500 .has_reset = true, 1501 }; 1502 1503 static const struct sun4i_codec_quirks sun8i_v3s_codec_quirks = { 1504 .regmap_config = &sun8i_v3s_codec_regmap_config, 1505 /* 1506 * TODO The codec structure should be split out, like 1507 * H3, when adding digital audio processing support. 1508 */ 1509 .codec = &sun8i_a23_codec_codec, 1510 .create_card = sun8i_v3s_codec_create_card, 1511 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), 1512 .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, 1513 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, 1514 .has_reset = true, 1515 }; 1516 1517 static const struct of_device_id sun4i_codec_of_match[] = { 1518 { 1519 .compatible = "allwinner,sun4i-a10-codec", 1520 .data = &sun4i_codec_quirks, 1521 }, 1522 { 1523 .compatible = "allwinner,sun6i-a31-codec", 1524 .data = &sun6i_a31_codec_quirks, 1525 }, 1526 { 1527 .compatible = "allwinner,sun7i-a20-codec", 1528 .data = &sun7i_codec_quirks, 1529 }, 1530 { 1531 .compatible = "allwinner,sun8i-a23-codec", 1532 .data = &sun8i_a23_codec_quirks, 1533 }, 1534 { 1535 .compatible = "allwinner,sun8i-h3-codec", 1536 .data = &sun8i_h3_codec_quirks, 1537 }, 1538 { 1539 .compatible = "allwinner,sun8i-v3s-codec", 1540 .data = &sun8i_v3s_codec_quirks, 1541 }, 1542 {} 1543 }; 1544 MODULE_DEVICE_TABLE(of, sun4i_codec_of_match); 1545 1546 static int sun4i_codec_probe(struct platform_device *pdev) 1547 { 1548 struct snd_soc_card *card; 1549 struct sun4i_codec *scodec; 1550 const struct sun4i_codec_quirks *quirks; 1551 struct resource *res; 1552 void __iomem *base; 1553 int ret; 1554 1555 scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL); 1556 if (!scodec) 1557 return -ENOMEM; 1558 1559 scodec->dev = &pdev->dev; 1560 1561 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1562 base = devm_ioremap_resource(&pdev->dev, res); 1563 if (IS_ERR(base)) { 1564 dev_err(&pdev->dev, "Failed to map the registers\n"); 1565 return PTR_ERR(base); 1566 } 1567 1568 quirks = of_device_get_match_data(&pdev->dev); 1569 if (quirks == NULL) { 1570 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); 1571 return -ENODEV; 1572 } 1573 1574 scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1575 quirks->regmap_config); 1576 if (IS_ERR(scodec->regmap)) { 1577 dev_err(&pdev->dev, "Failed to create our regmap\n"); 1578 return PTR_ERR(scodec->regmap); 1579 } 1580 1581 /* Get the clocks from the DT */ 1582 scodec->clk_apb = devm_clk_get(&pdev->dev, "apb"); 1583 if (IS_ERR(scodec->clk_apb)) { 1584 dev_err(&pdev->dev, "Failed to get the APB clock\n"); 1585 return PTR_ERR(scodec->clk_apb); 1586 } 1587 1588 scodec->clk_module = devm_clk_get(&pdev->dev, "codec"); 1589 if (IS_ERR(scodec->clk_module)) { 1590 dev_err(&pdev->dev, "Failed to get the module clock\n"); 1591 return PTR_ERR(scodec->clk_module); 1592 } 1593 1594 if (quirks->has_reset) { 1595 scodec->rst = devm_reset_control_get_exclusive(&pdev->dev, 1596 NULL); 1597 if (IS_ERR(scodec->rst)) { 1598 dev_err(&pdev->dev, "Failed to get reset control\n"); 1599 return PTR_ERR(scodec->rst); 1600 } 1601 } 1602 1603 scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa", 1604 GPIOD_OUT_LOW); 1605 if (IS_ERR(scodec->gpio_pa)) { 1606 ret = PTR_ERR(scodec->gpio_pa); 1607 if (ret != -EPROBE_DEFER) 1608 dev_err(&pdev->dev, "Failed to get pa gpio: %d\n", ret); 1609 return ret; 1610 } 1611 1612 /* reg_field setup */ 1613 scodec->reg_adc_fifoc = devm_regmap_field_alloc(&pdev->dev, 1614 scodec->regmap, 1615 quirks->reg_adc_fifoc); 1616 if (IS_ERR(scodec->reg_adc_fifoc)) { 1617 ret = PTR_ERR(scodec->reg_adc_fifoc); 1618 dev_err(&pdev->dev, "Failed to create regmap fields: %d\n", 1619 ret); 1620 return ret; 1621 } 1622 1623 /* Enable the bus clock */ 1624 if (clk_prepare_enable(scodec->clk_apb)) { 1625 dev_err(&pdev->dev, "Failed to enable the APB clock\n"); 1626 return -EINVAL; 1627 } 1628 1629 /* Deassert the reset control */ 1630 if (scodec->rst) { 1631 ret = reset_control_deassert(scodec->rst); 1632 if (ret) { 1633 dev_err(&pdev->dev, 1634 "Failed to deassert the reset control\n"); 1635 goto err_clk_disable; 1636 } 1637 } 1638 1639 /* DMA configuration for TX FIFO */ 1640 scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata; 1641 scodec->playback_dma_data.maxburst = 8; 1642 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1643 1644 /* DMA configuration for RX FIFO */ 1645 scodec->capture_dma_data.addr = res->start + quirks->reg_adc_rxdata; 1646 scodec->capture_dma_data.maxburst = 8; 1647 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1648 1649 ret = snd_soc_register_codec(&pdev->dev, quirks->codec, 1650 &sun4i_codec_dai, 1); 1651 if (ret) { 1652 dev_err(&pdev->dev, "Failed to register our codec\n"); 1653 goto err_assert_reset; 1654 } 1655 1656 ret = devm_snd_soc_register_component(&pdev->dev, 1657 &sun4i_codec_component, 1658 &dummy_cpu_dai, 1); 1659 if (ret) { 1660 dev_err(&pdev->dev, "Failed to register our DAI\n"); 1661 goto err_unregister_codec; 1662 } 1663 1664 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1665 if (ret) { 1666 dev_err(&pdev->dev, "Failed to register against DMAEngine\n"); 1667 goto err_unregister_codec; 1668 } 1669 1670 card = quirks->create_card(&pdev->dev); 1671 if (IS_ERR(card)) { 1672 ret = PTR_ERR(card); 1673 dev_err(&pdev->dev, "Failed to create our card\n"); 1674 goto err_unregister_codec; 1675 } 1676 1677 snd_soc_card_set_drvdata(card, scodec); 1678 1679 ret = snd_soc_register_card(card); 1680 if (ret) { 1681 dev_err(&pdev->dev, "Failed to register our card\n"); 1682 goto err_unregister_codec; 1683 } 1684 1685 return 0; 1686 1687 err_unregister_codec: 1688 snd_soc_unregister_codec(&pdev->dev); 1689 err_assert_reset: 1690 if (scodec->rst) 1691 reset_control_assert(scodec->rst); 1692 err_clk_disable: 1693 clk_disable_unprepare(scodec->clk_apb); 1694 return ret; 1695 } 1696 1697 static int sun4i_codec_remove(struct platform_device *pdev) 1698 { 1699 struct snd_soc_card *card = platform_get_drvdata(pdev); 1700 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card); 1701 1702 snd_soc_unregister_card(card); 1703 snd_soc_unregister_codec(&pdev->dev); 1704 if (scodec->rst) 1705 reset_control_assert(scodec->rst); 1706 clk_disable_unprepare(scodec->clk_apb); 1707 1708 return 0; 1709 } 1710 1711 static struct platform_driver sun4i_codec_driver = { 1712 .driver = { 1713 .name = "sun4i-codec", 1714 .of_match_table = sun4i_codec_of_match, 1715 }, 1716 .probe = sun4i_codec_probe, 1717 .remove = sun4i_codec_remove, 1718 }; 1719 module_platform_driver(sun4i_codec_driver); 1720 1721 MODULE_DESCRIPTION("Allwinner A10 codec driver"); 1722 MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>"); 1723 MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>"); 1724 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1725 MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>"); 1726 MODULE_LICENSE("GPL"); 1727