1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver. 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 22 /* SPDIF-rx Register Map */ 23 #define STM32_SPDIFRX_CR 0x00 24 #define STM32_SPDIFRX_IMR 0x04 25 #define STM32_SPDIFRX_SR 0x08 26 #define STM32_SPDIFRX_IFCR 0x0C 27 #define STM32_SPDIFRX_DR 0x10 28 #define STM32_SPDIFRX_CSR 0x14 29 #define STM32_SPDIFRX_DIR 0x18 30 #define STM32_SPDIFRX_VERR 0x3F4 31 #define STM32_SPDIFRX_IDR 0x3F8 32 #define STM32_SPDIFRX_SIDR 0x3FC 33 34 /* Bit definition for SPDIF_CR register */ 35 #define SPDIFRX_CR_SPDIFEN_SHIFT 0 36 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT) 37 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT) 38 39 #define SPDIFRX_CR_RXDMAEN BIT(2) 40 #define SPDIFRX_CR_RXSTEO BIT(3) 41 42 #define SPDIFRX_CR_DRFMT_SHIFT 4 43 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT) 44 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT) 45 46 #define SPDIFRX_CR_PMSK BIT(6) 47 #define SPDIFRX_CR_VMSK BIT(7) 48 #define SPDIFRX_CR_CUMSK BIT(8) 49 #define SPDIFRX_CR_PTMSK BIT(9) 50 #define SPDIFRX_CR_CBDMAEN BIT(10) 51 #define SPDIFRX_CR_CHSEL_SHIFT 11 52 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT) 53 54 #define SPDIFRX_CR_NBTR_SHIFT 12 55 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT) 56 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT) 57 58 #define SPDIFRX_CR_WFA BIT(14) 59 60 #define SPDIFRX_CR_INSEL_SHIFT 16 61 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT) 62 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT) 63 64 #define SPDIFRX_CR_CKSEN_SHIFT 20 65 #define SPDIFRX_CR_CKSEN BIT(20) 66 #define SPDIFRX_CR_CKSBKPEN BIT(21) 67 68 /* Bit definition for SPDIFRX_IMR register */ 69 #define SPDIFRX_IMR_RXNEI BIT(0) 70 #define SPDIFRX_IMR_CSRNEIE BIT(1) 71 #define SPDIFRX_IMR_PERRIE BIT(2) 72 #define SPDIFRX_IMR_OVRIE BIT(3) 73 #define SPDIFRX_IMR_SBLKIE BIT(4) 74 #define SPDIFRX_IMR_SYNCDIE BIT(5) 75 #define SPDIFRX_IMR_IFEIE BIT(6) 76 77 #define SPDIFRX_XIMR_MASK GENMASK(6, 0) 78 79 /* Bit definition for SPDIFRX_SR register */ 80 #define SPDIFRX_SR_RXNE BIT(0) 81 #define SPDIFRX_SR_CSRNE BIT(1) 82 #define SPDIFRX_SR_PERR BIT(2) 83 #define SPDIFRX_SR_OVR BIT(3) 84 #define SPDIFRX_SR_SBD BIT(4) 85 #define SPDIFRX_SR_SYNCD BIT(5) 86 #define SPDIFRX_SR_FERR BIT(6) 87 #define SPDIFRX_SR_SERR BIT(7) 88 #define SPDIFRX_SR_TERR BIT(8) 89 90 #define SPDIFRX_SR_WIDTH5_SHIFT 16 91 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT) 92 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT) 93 94 /* Bit definition for SPDIFRX_IFCR register */ 95 #define SPDIFRX_IFCR_PERRCF BIT(2) 96 #define SPDIFRX_IFCR_OVRCF BIT(3) 97 #define SPDIFRX_IFCR_SBDCF BIT(4) 98 #define SPDIFRX_IFCR_SYNCDCF BIT(5) 99 100 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2) 101 102 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */ 103 #define SPDIFRX_DR0_DR_SHIFT 0 104 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT) 105 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT) 106 107 #define SPDIFRX_DR0_PE BIT(24) 108 109 #define SPDIFRX_DR0_V BIT(25) 110 #define SPDIFRX_DR0_U BIT(26) 111 #define SPDIFRX_DR0_C BIT(27) 112 113 #define SPDIFRX_DR0_PT_SHIFT 28 114 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT) 115 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT) 116 117 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */ 118 #define SPDIFRX_DR1_PE BIT(0) 119 #define SPDIFRX_DR1_V BIT(1) 120 #define SPDIFRX_DR1_U BIT(2) 121 #define SPDIFRX_DR1_C BIT(3) 122 123 #define SPDIFRX_DR1_PT_SHIFT 4 124 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT) 125 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT) 126 127 #define SPDIFRX_DR1_DR_SHIFT 8 128 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT) 129 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT) 130 131 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */ 132 #define SPDIFRX_DR1_DRNL1_SHIFT 0 133 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT) 134 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT) 135 136 #define SPDIFRX_DR1_DRNL2_SHIFT 16 137 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT) 138 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT) 139 140 /* Bit definition for SPDIFRX_CSR register */ 141 #define SPDIFRX_CSR_USR_SHIFT 0 142 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT) 143 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\ 144 >> SPDIFRX_CSR_USR_SHIFT) 145 146 #define SPDIFRX_CSR_CS_SHIFT 16 147 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT) 148 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\ 149 >> SPDIFRX_CSR_CS_SHIFT) 150 151 #define SPDIFRX_CSR_SOB BIT(24) 152 153 /* Bit definition for SPDIFRX_DIR register */ 154 #define SPDIFRX_DIR_THI_SHIFT 0 155 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT) 156 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT) 157 158 #define SPDIFRX_DIR_TLO_SHIFT 16 159 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT) 160 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT) 161 162 #define SPDIFRX_SPDIFEN_DISABLE 0x0 163 #define SPDIFRX_SPDIFEN_SYNC 0x1 164 #define SPDIFRX_SPDIFEN_ENABLE 0x3 165 166 /* Bit definition for SPDIFRX_VERR register */ 167 #define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0) 168 #define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4) 169 170 /* Bit definition for SPDIFRX_IDR register */ 171 #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0) 172 173 /* Bit definition for SPDIFRX_SIDR register */ 174 #define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0) 175 176 #define SPDIFRX_IPIDR_NUMBER 0x00130041 177 178 #define SPDIFRX_IN1 0x1 179 #define SPDIFRX_IN2 0x2 180 #define SPDIFRX_IN3 0x3 181 #define SPDIFRX_IN4 0x4 182 #define SPDIFRX_IN5 0x5 183 #define SPDIFRX_IN6 0x6 184 #define SPDIFRX_IN7 0x7 185 #define SPDIFRX_IN8 0x8 186 187 #define SPDIFRX_NBTR_NONE 0x0 188 #define SPDIFRX_NBTR_3 0x1 189 #define SPDIFRX_NBTR_15 0x2 190 #define SPDIFRX_NBTR_63 0x3 191 192 #define SPDIFRX_DRFMT_RIGHT 0x0 193 #define SPDIFRX_DRFMT_LEFT 0x1 194 #define SPDIFRX_DRFMT_PACKED 0x2 195 196 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */ 197 #define SPDIFRX_CS_BYTES_NB 24 198 #define SPDIFRX_UB_BYTES_NB 48 199 200 /* 201 * CSR register is retrieved as a 32 bits word 202 * It contains 1 channel status byte and 2 user data bytes 203 * 2 S/PDIF frames are acquired to get all CS/UB bits 204 */ 205 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2) 206 207 /** 208 * struct stm32_spdifrx_data - private data of SPDIFRX 209 * @pdev: device data pointer 210 * @base: mmio register base virtual address 211 * @regmap: SPDIFRX register map pointer 212 * @regmap_conf: SPDIFRX register map configuration pointer 213 * @cs_completion: channel status retrieving completion 214 * @kclk: kernel clock feeding the SPDIFRX clock generator 215 * @dma_params: dma configuration data for rx channel 216 * @substream: PCM substream data pointer 217 * @dmab: dma buffer info pointer 218 * @ctrl_chan: dma channel for S/PDIF control bits 219 * @desc:dma async transaction descriptor 220 * @slave_config: dma slave channel runtime config pointer 221 * @phys_addr: SPDIFRX registers physical base address 222 * @lock: synchronization enabling lock 223 * @irq_lock: prevent race condition with IRQ on stream state 224 * @cs: channel status buffer 225 * @ub: user data buffer 226 * @irq: SPDIFRX interrupt line 227 * @refcount: keep count of opened DMA channels 228 */ 229 struct stm32_spdifrx_data { 230 struct platform_device *pdev; 231 void __iomem *base; 232 struct regmap *regmap; 233 const struct regmap_config *regmap_conf; 234 struct completion cs_completion; 235 struct clk *kclk; 236 struct snd_dmaengine_dai_dma_data dma_params; 237 struct snd_pcm_substream *substream; 238 struct snd_dma_buffer *dmab; 239 struct dma_chan *ctrl_chan; 240 struct dma_async_tx_descriptor *desc; 241 struct dma_slave_config slave_config; 242 dma_addr_t phys_addr; 243 spinlock_t lock; /* Sync enabling lock */ 244 spinlock_t irq_lock; /* Prevent race condition on stream state */ 245 unsigned char cs[SPDIFRX_CS_BYTES_NB]; 246 unsigned char ub[SPDIFRX_UB_BYTES_NB]; 247 int irq; 248 int refcount; 249 }; 250 251 static void stm32_spdifrx_dma_complete(void *data) 252 { 253 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data; 254 struct platform_device *pdev = spdifrx->pdev; 255 u32 *p_start = (u32 *)spdifrx->dmab->area; 256 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1; 257 u32 *ptr = p_start; 258 u16 *ub_ptr = (short *)spdifrx->ub; 259 int i = 0; 260 261 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 262 SPDIFRX_CR_CBDMAEN, 263 (unsigned int)~SPDIFRX_CR_CBDMAEN); 264 265 if (!spdifrx->dmab->area) 266 return; 267 268 while (ptr <= p_end) { 269 if (*ptr & SPDIFRX_CSR_SOB) 270 break; 271 ptr++; 272 } 273 274 if (ptr > p_end) { 275 dev_err(&pdev->dev, "Start of S/PDIF block not found\n"); 276 return; 277 } 278 279 while (i < SPDIFRX_CS_BYTES_NB) { 280 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr); 281 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++); 282 if (ptr > p_end) { 283 dev_err(&pdev->dev, "Failed to get channel status\n"); 284 return; 285 } 286 i++; 287 } 288 289 complete(&spdifrx->cs_completion); 290 } 291 292 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx) 293 { 294 dma_cookie_t cookie; 295 int err; 296 297 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan, 298 spdifrx->dmab->addr, 299 SPDIFRX_CSR_BUF_LENGTH, 300 DMA_DEV_TO_MEM, 301 DMA_CTRL_ACK); 302 if (!spdifrx->desc) 303 return -EINVAL; 304 305 spdifrx->desc->callback = stm32_spdifrx_dma_complete; 306 spdifrx->desc->callback_param = spdifrx; 307 cookie = dmaengine_submit(spdifrx->desc); 308 err = dma_submit_error(cookie); 309 if (err) 310 return -EINVAL; 311 312 dma_async_issue_pending(spdifrx->ctrl_chan); 313 314 return 0; 315 } 316 317 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx) 318 { 319 dmaengine_terminate_async(spdifrx->ctrl_chan); 320 } 321 322 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx) 323 { 324 int cr, cr_mask, imr, ret; 325 unsigned long flags; 326 327 /* Enable IRQs */ 328 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE; 329 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr); 330 if (ret) 331 return ret; 332 333 spin_lock_irqsave(&spdifrx->lock, flags); 334 335 spdifrx->refcount++; 336 337 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 338 339 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) { 340 /* 341 * Start sync if SPDIFRX is still in idle state. 342 * SPDIFRX reception enabled when sync done 343 */ 344 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n"); 345 346 /* 347 * SPDIFRX configuration: 348 * Wait for activity before starting sync process. This avoid 349 * to issue sync errors when spdif signal is missing on input. 350 * Preamble, CS, user, validity and parity error bits not copied 351 * to DR register. 352 */ 353 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK | 354 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO; 355 cr_mask = cr; 356 357 cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63); 358 cr_mask |= SPDIFRX_CR_NBTR_MASK; 359 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 360 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK; 361 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 362 cr_mask, cr); 363 if (ret < 0) 364 dev_err(&spdifrx->pdev->dev, 365 "Failed to start synchronization\n"); 366 } 367 368 spin_unlock_irqrestore(&spdifrx->lock, flags); 369 370 return ret; 371 } 372 373 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx) 374 { 375 int cr, cr_mask, reg; 376 unsigned long flags; 377 378 spin_lock_irqsave(&spdifrx->lock, flags); 379 380 if (--spdifrx->refcount) { 381 spin_unlock_irqrestore(&spdifrx->lock, flags); 382 return; 383 } 384 385 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 386 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN; 387 388 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr); 389 390 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 391 SPDIFRX_XIMR_MASK, 0); 392 393 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 394 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK); 395 396 /* dummy read to clear CSRNE and RXNE in status register */ 397 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®); 398 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®); 399 400 spin_unlock_irqrestore(&spdifrx->lock, flags); 401 } 402 403 static int stm32_spdifrx_dma_ctrl_register(struct device *dev, 404 struct stm32_spdifrx_data *spdifrx) 405 { 406 int ret; 407 408 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl"); 409 if (IS_ERR(spdifrx->ctrl_chan)) { 410 if (PTR_ERR(spdifrx->ctrl_chan) != -EPROBE_DEFER) 411 dev_err(dev, "dma_request_slave_channel error %ld\n", 412 PTR_ERR(spdifrx->ctrl_chan)); 413 return PTR_ERR(spdifrx->ctrl_chan); 414 } 415 416 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer), 417 GFP_KERNEL); 418 if (!spdifrx->dmab) 419 return -ENOMEM; 420 421 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM; 422 spdifrx->dmab->dev.dev = dev; 423 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev, 424 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab); 425 if (ret < 0) { 426 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret); 427 return ret; 428 } 429 430 spdifrx->slave_config.direction = DMA_DEV_TO_MEM; 431 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr + 432 STM32_SPDIFRX_CSR); 433 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr; 434 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 435 spdifrx->slave_config.src_maxburst = 1; 436 437 ret = dmaengine_slave_config(spdifrx->ctrl_chan, 438 &spdifrx->slave_config); 439 if (ret < 0) { 440 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret); 441 spdifrx->ctrl_chan = NULL; 442 } 443 444 return ret; 445 }; 446 447 static const char * const spdifrx_enum_input[] = { 448 "in0", "in1", "in2", "in3" 449 }; 450 451 /* By default CS bits are retrieved from channel A */ 452 static const char * const spdifrx_enum_cs_channel[] = { 453 "A", "B" 454 }; 455 456 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input, 457 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT, 458 spdifrx_enum_input); 459 460 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel, 461 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT, 462 spdifrx_enum_cs_channel); 463 464 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol, 465 struct snd_ctl_elem_info *uinfo) 466 { 467 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 468 uinfo->count = 1; 469 470 return 0; 471 } 472 473 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol, 474 struct snd_ctl_elem_info *uinfo) 475 { 476 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 477 uinfo->count = 1; 478 479 return 0; 480 } 481 482 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx) 483 { 484 int ret = 0; 485 486 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB); 487 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB); 488 489 ret = stm32_spdifrx_dma_ctrl_start(spdifrx); 490 if (ret < 0) 491 return ret; 492 493 ret = clk_prepare_enable(spdifrx->kclk); 494 if (ret) { 495 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 496 return ret; 497 } 498 499 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 500 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN); 501 if (ret < 0) 502 goto end; 503 504 ret = stm32_spdifrx_start_sync(spdifrx); 505 if (ret < 0) 506 goto end; 507 508 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion, 509 msecs_to_jiffies(100)) 510 <= 0) { 511 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n"); 512 ret = -EAGAIN; 513 } 514 515 stm32_spdifrx_stop(spdifrx); 516 stm32_spdifrx_dma_ctrl_stop(spdifrx); 517 518 end: 519 clk_disable_unprepare(spdifrx->kclk); 520 521 return ret; 522 } 523 524 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol, 525 struct snd_ctl_elem_value *ucontrol) 526 { 527 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 528 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 529 530 stm32_spdifrx_get_ctrl_data(spdifrx); 531 532 ucontrol->value.iec958.status[0] = spdifrx->cs[0]; 533 ucontrol->value.iec958.status[1] = spdifrx->cs[1]; 534 ucontrol->value.iec958.status[2] = spdifrx->cs[2]; 535 ucontrol->value.iec958.status[3] = spdifrx->cs[3]; 536 ucontrol->value.iec958.status[4] = spdifrx->cs[4]; 537 538 return 0; 539 } 540 541 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol, 542 struct snd_ctl_elem_value *ucontrol) 543 { 544 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 545 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 546 547 stm32_spdifrx_get_ctrl_data(spdifrx); 548 549 ucontrol->value.iec958.status[0] = spdifrx->ub[0]; 550 ucontrol->value.iec958.status[1] = spdifrx->ub[1]; 551 ucontrol->value.iec958.status[2] = spdifrx->ub[2]; 552 ucontrol->value.iec958.status[3] = spdifrx->ub[3]; 553 ucontrol->value.iec958.status[4] = spdifrx->ub[4]; 554 555 return 0; 556 } 557 558 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = { 559 /* Channel status control */ 560 { 561 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 562 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 563 .access = SNDRV_CTL_ELEM_ACCESS_READ | 564 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 565 .info = stm32_spdifrx_info, 566 .get = stm32_spdifrx_capture_get, 567 }, 568 /* User bits control */ 569 { 570 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 571 .name = "IEC958 User Bit Capture Default", 572 .access = SNDRV_CTL_ELEM_ACCESS_READ | 573 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 574 .info = stm32_spdifrx_ub_info, 575 .get = stm32_spdif_user_bits_get, 576 }, 577 }; 578 579 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = { 580 SOC_ENUM("SPDIFRX input", ctrl_enum_input), 581 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel), 582 }; 583 584 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai) 585 { 586 int ret; 587 588 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls, 589 ARRAY_SIZE(stm32_spdifrx_iec_ctrls)); 590 if (ret < 0) 591 return ret; 592 593 return snd_soc_add_component_controls(cpu_dai->component, 594 stm32_spdifrx_ctrls, 595 ARRAY_SIZE(stm32_spdifrx_ctrls)); 596 } 597 598 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai) 599 { 600 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev); 601 602 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr + 603 STM32_SPDIFRX_DR); 604 spdifrx->dma_params.maxburst = 1; 605 606 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 607 608 return stm32_spdifrx_dai_register_ctrls(cpu_dai); 609 } 610 611 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg) 612 { 613 switch (reg) { 614 case STM32_SPDIFRX_CR: 615 case STM32_SPDIFRX_IMR: 616 case STM32_SPDIFRX_SR: 617 case STM32_SPDIFRX_IFCR: 618 case STM32_SPDIFRX_DR: 619 case STM32_SPDIFRX_CSR: 620 case STM32_SPDIFRX_DIR: 621 case STM32_SPDIFRX_VERR: 622 case STM32_SPDIFRX_IDR: 623 case STM32_SPDIFRX_SIDR: 624 return true; 625 default: 626 return false; 627 } 628 } 629 630 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 631 { 632 switch (reg) { 633 case STM32_SPDIFRX_DR: 634 case STM32_SPDIFRX_CSR: 635 case STM32_SPDIFRX_SR: 636 case STM32_SPDIFRX_DIR: 637 return true; 638 default: 639 return false; 640 } 641 } 642 643 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 644 { 645 switch (reg) { 646 case STM32_SPDIFRX_CR: 647 case STM32_SPDIFRX_IMR: 648 case STM32_SPDIFRX_IFCR: 649 return true; 650 default: 651 return false; 652 } 653 } 654 655 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = { 656 .reg_bits = 32, 657 .reg_stride = 4, 658 .val_bits = 32, 659 .max_register = STM32_SPDIFRX_SIDR, 660 .readable_reg = stm32_spdifrx_readable_reg, 661 .volatile_reg = stm32_spdifrx_volatile_reg, 662 .writeable_reg = stm32_spdifrx_writeable_reg, 663 .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1, 664 .fast_io = true, 665 .cache_type = REGCACHE_FLAT, 666 }; 667 668 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid) 669 { 670 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid; 671 struct platform_device *pdev = spdifrx->pdev; 672 unsigned int cr, mask, sr, imr; 673 unsigned int flags, sync_state; 674 int err = 0, err_xrun = 0; 675 676 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr); 677 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr); 678 679 mask = imr & SPDIFRX_XIMR_MASK; 680 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */ 681 if (mask & SPDIFRX_IMR_IFEIE) 682 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2); 683 684 flags = sr & mask; 685 if (!flags) { 686 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n", 687 sr, imr); 688 return IRQ_NONE; 689 } 690 691 /* Clear IRQs */ 692 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 693 SPDIFRX_XIFCR_MASK, flags); 694 695 if (flags & SPDIFRX_SR_PERR) { 696 dev_dbg(&pdev->dev, "Parity error\n"); 697 err_xrun = 1; 698 } 699 700 if (flags & SPDIFRX_SR_OVR) { 701 dev_dbg(&pdev->dev, "Overrun error\n"); 702 err_xrun = 1; 703 } 704 705 if (flags & SPDIFRX_SR_SBD) 706 dev_dbg(&pdev->dev, "Synchronization block detected\n"); 707 708 if (flags & SPDIFRX_SR_SYNCD) { 709 dev_dbg(&pdev->dev, "Synchronization done\n"); 710 711 /* Enable spdifrx */ 712 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE); 713 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 714 SPDIFRX_CR_SPDIFEN_MASK, cr); 715 } 716 717 if (flags & SPDIFRX_SR_FERR) { 718 dev_dbg(&pdev->dev, "Frame error\n"); 719 err = 1; 720 } 721 722 if (flags & SPDIFRX_SR_SERR) { 723 dev_dbg(&pdev->dev, "Synchronization error\n"); 724 err = 1; 725 } 726 727 if (flags & SPDIFRX_SR_TERR) { 728 dev_dbg(&pdev->dev, "Timeout error\n"); 729 err = 1; 730 } 731 732 if (err) { 733 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 734 sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) && 735 SPDIFRX_SPDIFEN_SYNC; 736 737 /* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */ 738 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 739 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 740 SPDIFRX_CR_SPDIFEN_MASK, cr); 741 742 /* If SPDIFRX was in STATE_SYNC, retry synchro */ 743 if (sync_state) { 744 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 745 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 746 SPDIFRX_CR_SPDIFEN_MASK, cr); 747 return IRQ_HANDLED; 748 } 749 750 spin_lock(&spdifrx->irq_lock); 751 if (spdifrx->substream) 752 snd_pcm_stop(spdifrx->substream, 753 SNDRV_PCM_STATE_DISCONNECTED); 754 spin_unlock(&spdifrx->irq_lock); 755 756 return IRQ_HANDLED; 757 } 758 759 spin_lock(&spdifrx->irq_lock); 760 if (err_xrun && spdifrx->substream) 761 snd_pcm_stop_xrun(spdifrx->substream); 762 spin_unlock(&spdifrx->irq_lock); 763 764 return IRQ_HANDLED; 765 } 766 767 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream, 768 struct snd_soc_dai *cpu_dai) 769 { 770 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 771 unsigned long flags; 772 int ret; 773 774 spin_lock_irqsave(&spdifrx->irq_lock, flags); 775 spdifrx->substream = substream; 776 spin_unlock_irqrestore(&spdifrx->irq_lock, flags); 777 778 ret = clk_prepare_enable(spdifrx->kclk); 779 if (ret) 780 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 781 782 return ret; 783 } 784 785 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream, 786 struct snd_pcm_hw_params *params, 787 struct snd_soc_dai *cpu_dai) 788 { 789 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 790 int data_size = params_width(params); 791 int fmt; 792 793 switch (data_size) { 794 case 16: 795 fmt = SPDIFRX_DRFMT_PACKED; 796 break; 797 case 32: 798 fmt = SPDIFRX_DRFMT_LEFT; 799 break; 800 default: 801 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n"); 802 return -EINVAL; 803 } 804 805 /* 806 * Set buswidth to 4 bytes for all data formats. 807 * Packed format: transfer 2 x 2 bytes samples 808 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte 809 */ 810 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 811 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 812 813 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 814 SPDIFRX_CR_DRFMT_MASK, 815 SPDIFRX_CR_DRFMTSET(fmt)); 816 } 817 818 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 819 struct snd_soc_dai *cpu_dai) 820 { 821 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 822 int ret = 0; 823 824 switch (cmd) { 825 case SNDRV_PCM_TRIGGER_START: 826 case SNDRV_PCM_TRIGGER_RESUME: 827 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 828 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 829 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE); 830 831 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 832 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN); 833 834 ret = stm32_spdifrx_start_sync(spdifrx); 835 break; 836 case SNDRV_PCM_TRIGGER_SUSPEND: 837 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 838 case SNDRV_PCM_TRIGGER_STOP: 839 stm32_spdifrx_stop(spdifrx); 840 break; 841 default: 842 return -EINVAL; 843 } 844 845 return ret; 846 } 847 848 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream, 849 struct snd_soc_dai *cpu_dai) 850 { 851 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 852 unsigned long flags; 853 854 spin_lock_irqsave(&spdifrx->irq_lock, flags); 855 spdifrx->substream = NULL; 856 spin_unlock_irqrestore(&spdifrx->irq_lock, flags); 857 858 clk_disable_unprepare(spdifrx->kclk); 859 } 860 861 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = { 862 .startup = stm32_spdifrx_startup, 863 .hw_params = stm32_spdifrx_hw_params, 864 .trigger = stm32_spdifrx_trigger, 865 .shutdown = stm32_spdifrx_shutdown, 866 }; 867 868 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = { 869 { 870 .probe = stm32_spdifrx_dai_probe, 871 .capture = { 872 .stream_name = "CPU-Capture", 873 .channels_min = 1, 874 .channels_max = 2, 875 .rates = SNDRV_PCM_RATE_8000_192000, 876 .formats = SNDRV_PCM_FMTBIT_S32_LE | 877 SNDRV_PCM_FMTBIT_S16_LE, 878 }, 879 .ops = &stm32_spdifrx_pcm_dai_ops, 880 } 881 }; 882 883 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = { 884 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 885 .buffer_bytes_max = 8 * PAGE_SIZE, 886 .period_bytes_min = 1024, 887 .period_bytes_max = 4 * PAGE_SIZE, 888 .periods_min = 2, 889 .periods_max = 8, 890 }; 891 892 static const struct snd_soc_component_driver stm32_spdifrx_component = { 893 .name = "stm32-spdifrx", 894 }; 895 896 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = { 897 .pcm_hardware = &stm32_spdifrx_pcm_hw, 898 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 899 }; 900 901 static const struct of_device_id stm32_spdifrx_ids[] = { 902 { 903 .compatible = "st,stm32h7-spdifrx", 904 .data = &stm32_h7_spdifrx_regmap_conf 905 }, 906 {} 907 }; 908 909 static int stm32_spdifrx_parse_of(struct platform_device *pdev, 910 struct stm32_spdifrx_data *spdifrx) 911 { 912 struct device_node *np = pdev->dev.of_node; 913 const struct of_device_id *of_id; 914 struct resource *res; 915 916 if (!np) 917 return -ENODEV; 918 919 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev); 920 if (of_id) 921 spdifrx->regmap_conf = 922 (const struct regmap_config *)of_id->data; 923 else 924 return -EINVAL; 925 926 spdifrx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 927 if (IS_ERR(spdifrx->base)) 928 return PTR_ERR(spdifrx->base); 929 930 spdifrx->phys_addr = res->start; 931 932 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk"); 933 if (IS_ERR(spdifrx->kclk)) { 934 if (PTR_ERR(spdifrx->kclk) != -EPROBE_DEFER) 935 dev_err(&pdev->dev, "Could not get kclk: %ld\n", 936 PTR_ERR(spdifrx->kclk)); 937 return PTR_ERR(spdifrx->kclk); 938 } 939 940 spdifrx->irq = platform_get_irq(pdev, 0); 941 if (spdifrx->irq < 0) 942 return spdifrx->irq; 943 944 return 0; 945 } 946 947 static int stm32_spdifrx_remove(struct platform_device *pdev) 948 { 949 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev); 950 951 if (spdifrx->ctrl_chan) 952 dma_release_channel(spdifrx->ctrl_chan); 953 954 if (spdifrx->dmab) 955 snd_dma_free_pages(spdifrx->dmab); 956 957 snd_dmaengine_pcm_unregister(&pdev->dev); 958 snd_soc_unregister_component(&pdev->dev); 959 pm_runtime_disable(&pdev->dev); 960 961 return 0; 962 } 963 964 static int stm32_spdifrx_probe(struct platform_device *pdev) 965 { 966 struct stm32_spdifrx_data *spdifrx; 967 struct reset_control *rst; 968 const struct snd_dmaengine_pcm_config *pcm_config = NULL; 969 u32 ver, idr; 970 int ret; 971 972 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL); 973 if (!spdifrx) 974 return -ENOMEM; 975 976 spdifrx->pdev = pdev; 977 init_completion(&spdifrx->cs_completion); 978 spin_lock_init(&spdifrx->lock); 979 spin_lock_init(&spdifrx->irq_lock); 980 981 platform_set_drvdata(pdev, spdifrx); 982 983 ret = stm32_spdifrx_parse_of(pdev, spdifrx); 984 if (ret) 985 return ret; 986 987 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk", 988 spdifrx->base, 989 spdifrx->regmap_conf); 990 if (IS_ERR(spdifrx->regmap)) { 991 if (PTR_ERR(spdifrx->regmap) != -EPROBE_DEFER) 992 dev_err(&pdev->dev, "Regmap init error %ld\n", 993 PTR_ERR(spdifrx->regmap)); 994 return PTR_ERR(spdifrx->regmap); 995 } 996 997 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0, 998 dev_name(&pdev->dev), spdifrx); 999 if (ret) { 1000 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1001 return ret; 1002 } 1003 1004 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1005 if (IS_ERR(rst)) { 1006 if (PTR_ERR(rst) != -EPROBE_DEFER) 1007 dev_err(&pdev->dev, "Reset controller error %ld\n", 1008 PTR_ERR(rst)); 1009 return PTR_ERR(rst); 1010 } 1011 reset_control_assert(rst); 1012 udelay(2); 1013 reset_control_deassert(rst); 1014 1015 pm_runtime_enable(&pdev->dev); 1016 1017 pcm_config = &stm32_spdifrx_pcm_config; 1018 ret = snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0); 1019 if (ret) { 1020 if (ret != -EPROBE_DEFER) 1021 dev_err(&pdev->dev, "PCM DMA register error %d\n", ret); 1022 return ret; 1023 } 1024 1025 ret = snd_soc_register_component(&pdev->dev, 1026 &stm32_spdifrx_component, 1027 stm32_spdifrx_dai, 1028 ARRAY_SIZE(stm32_spdifrx_dai)); 1029 if (ret) { 1030 snd_dmaengine_pcm_unregister(&pdev->dev); 1031 return ret; 1032 } 1033 1034 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx); 1035 if (ret) 1036 goto error; 1037 1038 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr); 1039 if (ret) 1040 goto error; 1041 1042 if (idr == SPDIFRX_IPIDR_NUMBER) { 1043 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver); 1044 if (ret) 1045 goto error; 1046 1047 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n", 1048 FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver), 1049 FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver)); 1050 } 1051 1052 return ret; 1053 1054 error: 1055 stm32_spdifrx_remove(pdev); 1056 1057 return ret; 1058 } 1059 1060 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids); 1061 1062 #ifdef CONFIG_PM_SLEEP 1063 static int stm32_spdifrx_suspend(struct device *dev) 1064 { 1065 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1066 1067 regcache_cache_only(spdifrx->regmap, true); 1068 regcache_mark_dirty(spdifrx->regmap); 1069 1070 return 0; 1071 } 1072 1073 static int stm32_spdifrx_resume(struct device *dev) 1074 { 1075 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1076 1077 regcache_cache_only(spdifrx->regmap, false); 1078 1079 return regcache_sync(spdifrx->regmap); 1080 } 1081 #endif /* CONFIG_PM_SLEEP */ 1082 1083 static const struct dev_pm_ops stm32_spdifrx_pm_ops = { 1084 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume) 1085 }; 1086 1087 static struct platform_driver stm32_spdifrx_driver = { 1088 .driver = { 1089 .name = "st,stm32-spdifrx", 1090 .of_match_table = stm32_spdifrx_ids, 1091 .pm = &stm32_spdifrx_pm_ops, 1092 }, 1093 .probe = stm32_spdifrx_probe, 1094 .remove = stm32_spdifrx_remove, 1095 }; 1096 1097 module_platform_driver(stm32_spdifrx_driver); 1098 1099 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface"); 1100 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 1101 MODULE_ALIAS("platform:stm32-spdifrx"); 1102 MODULE_LICENSE("GPL v2"); 1103