1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver. 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of_platform.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 22 /* SPDIF-rx Register Map */ 23 #define STM32_SPDIFRX_CR 0x00 24 #define STM32_SPDIFRX_IMR 0x04 25 #define STM32_SPDIFRX_SR 0x08 26 #define STM32_SPDIFRX_IFCR 0x0C 27 #define STM32_SPDIFRX_DR 0x10 28 #define STM32_SPDIFRX_CSR 0x14 29 #define STM32_SPDIFRX_DIR 0x18 30 #define STM32_SPDIFRX_VERR 0x3F4 31 #define STM32_SPDIFRX_IDR 0x3F8 32 #define STM32_SPDIFRX_SIDR 0x3FC 33 34 /* Bit definition for SPDIF_CR register */ 35 #define SPDIFRX_CR_SPDIFEN_SHIFT 0 36 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT) 37 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT) 38 39 #define SPDIFRX_CR_RXDMAEN BIT(2) 40 #define SPDIFRX_CR_RXSTEO BIT(3) 41 42 #define SPDIFRX_CR_DRFMT_SHIFT 4 43 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT) 44 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT) 45 46 #define SPDIFRX_CR_PMSK BIT(6) 47 #define SPDIFRX_CR_VMSK BIT(7) 48 #define SPDIFRX_CR_CUMSK BIT(8) 49 #define SPDIFRX_CR_PTMSK BIT(9) 50 #define SPDIFRX_CR_CBDMAEN BIT(10) 51 #define SPDIFRX_CR_CHSEL_SHIFT 11 52 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT) 53 54 #define SPDIFRX_CR_NBTR_SHIFT 12 55 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT) 56 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT) 57 58 #define SPDIFRX_CR_WFA BIT(14) 59 60 #define SPDIFRX_CR_INSEL_SHIFT 16 61 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT) 62 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT) 63 64 #define SPDIFRX_CR_CKSEN_SHIFT 20 65 #define SPDIFRX_CR_CKSEN BIT(20) 66 #define SPDIFRX_CR_CKSBKPEN BIT(21) 67 68 /* Bit definition for SPDIFRX_IMR register */ 69 #define SPDIFRX_IMR_RXNEI BIT(0) 70 #define SPDIFRX_IMR_CSRNEIE BIT(1) 71 #define SPDIFRX_IMR_PERRIE BIT(2) 72 #define SPDIFRX_IMR_OVRIE BIT(3) 73 #define SPDIFRX_IMR_SBLKIE BIT(4) 74 #define SPDIFRX_IMR_SYNCDIE BIT(5) 75 #define SPDIFRX_IMR_IFEIE BIT(6) 76 77 #define SPDIFRX_XIMR_MASK GENMASK(6, 0) 78 79 /* Bit definition for SPDIFRX_SR register */ 80 #define SPDIFRX_SR_RXNE BIT(0) 81 #define SPDIFRX_SR_CSRNE BIT(1) 82 #define SPDIFRX_SR_PERR BIT(2) 83 #define SPDIFRX_SR_OVR BIT(3) 84 #define SPDIFRX_SR_SBD BIT(4) 85 #define SPDIFRX_SR_SYNCD BIT(5) 86 #define SPDIFRX_SR_FERR BIT(6) 87 #define SPDIFRX_SR_SERR BIT(7) 88 #define SPDIFRX_SR_TERR BIT(8) 89 90 #define SPDIFRX_SR_WIDTH5_SHIFT 16 91 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT) 92 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT) 93 94 /* Bit definition for SPDIFRX_IFCR register */ 95 #define SPDIFRX_IFCR_PERRCF BIT(2) 96 #define SPDIFRX_IFCR_OVRCF BIT(3) 97 #define SPDIFRX_IFCR_SBDCF BIT(4) 98 #define SPDIFRX_IFCR_SYNCDCF BIT(5) 99 100 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2) 101 102 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */ 103 #define SPDIFRX_DR0_DR_SHIFT 0 104 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT) 105 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT) 106 107 #define SPDIFRX_DR0_PE BIT(24) 108 109 #define SPDIFRX_DR0_V BIT(25) 110 #define SPDIFRX_DR0_U BIT(26) 111 #define SPDIFRX_DR0_C BIT(27) 112 113 #define SPDIFRX_DR0_PT_SHIFT 28 114 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT) 115 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT) 116 117 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */ 118 #define SPDIFRX_DR1_PE BIT(0) 119 #define SPDIFRX_DR1_V BIT(1) 120 #define SPDIFRX_DR1_U BIT(2) 121 #define SPDIFRX_DR1_C BIT(3) 122 123 #define SPDIFRX_DR1_PT_SHIFT 4 124 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT) 125 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT) 126 127 #define SPDIFRX_DR1_DR_SHIFT 8 128 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT) 129 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT) 130 131 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */ 132 #define SPDIFRX_DR1_DRNL1_SHIFT 0 133 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT) 134 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT) 135 136 #define SPDIFRX_DR1_DRNL2_SHIFT 16 137 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT) 138 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT) 139 140 /* Bit definition for SPDIFRX_CSR register */ 141 #define SPDIFRX_CSR_USR_SHIFT 0 142 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT) 143 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\ 144 >> SPDIFRX_CSR_USR_SHIFT) 145 146 #define SPDIFRX_CSR_CS_SHIFT 16 147 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT) 148 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\ 149 >> SPDIFRX_CSR_CS_SHIFT) 150 151 #define SPDIFRX_CSR_SOB BIT(24) 152 153 /* Bit definition for SPDIFRX_DIR register */ 154 #define SPDIFRX_DIR_THI_SHIFT 0 155 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT) 156 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT) 157 158 #define SPDIFRX_DIR_TLO_SHIFT 16 159 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT) 160 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT) 161 162 #define SPDIFRX_SPDIFEN_DISABLE 0x0 163 #define SPDIFRX_SPDIFEN_SYNC 0x1 164 #define SPDIFRX_SPDIFEN_ENABLE 0x3 165 166 /* Bit definition for SPDIFRX_VERR register */ 167 #define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0) 168 #define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4) 169 170 /* Bit definition for SPDIFRX_IDR register */ 171 #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0) 172 173 /* Bit definition for SPDIFRX_SIDR register */ 174 #define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0) 175 176 #define SPDIFRX_IPIDR_NUMBER 0x00130041 177 178 #define SPDIFRX_IN1 0x1 179 #define SPDIFRX_IN2 0x2 180 #define SPDIFRX_IN3 0x3 181 #define SPDIFRX_IN4 0x4 182 #define SPDIFRX_IN5 0x5 183 #define SPDIFRX_IN6 0x6 184 #define SPDIFRX_IN7 0x7 185 #define SPDIFRX_IN8 0x8 186 187 #define SPDIFRX_NBTR_NONE 0x0 188 #define SPDIFRX_NBTR_3 0x1 189 #define SPDIFRX_NBTR_15 0x2 190 #define SPDIFRX_NBTR_63 0x3 191 192 #define SPDIFRX_DRFMT_RIGHT 0x0 193 #define SPDIFRX_DRFMT_LEFT 0x1 194 #define SPDIFRX_DRFMT_PACKED 0x2 195 196 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */ 197 #define SPDIFRX_CS_BYTES_NB 24 198 #define SPDIFRX_UB_BYTES_NB 48 199 200 /* 201 * CSR register is retrieved as a 32 bits word 202 * It contains 1 channel status byte and 2 user data bytes 203 * 2 S/PDIF frames are acquired to get all CS/UB bits 204 */ 205 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2) 206 207 /** 208 * struct stm32_spdifrx_data - private data of SPDIFRX 209 * @pdev: device data pointer 210 * @base: mmio register base virtual address 211 * @regmap: SPDIFRX register map pointer 212 * @regmap_conf: SPDIFRX register map configuration pointer 213 * @cs_completion: channel status retrieving completion 214 * @kclk: kernel clock feeding the SPDIFRX clock generator 215 * @dma_params: dma configuration data for rx channel 216 * @substream: PCM substream data pointer 217 * @dmab: dma buffer info pointer 218 * @ctrl_chan: dma channel for S/PDIF control bits 219 * @desc:dma async transaction descriptor 220 * @slave_config: dma slave channel runtime config pointer 221 * @phys_addr: SPDIFRX registers physical base address 222 * @lock: synchronization enabling lock 223 * @cs: channel status buffer 224 * @ub: user data buffer 225 * @irq: SPDIFRX interrupt line 226 * @refcount: keep count of opened DMA channels 227 */ 228 struct stm32_spdifrx_data { 229 struct platform_device *pdev; 230 void __iomem *base; 231 struct regmap *regmap; 232 const struct regmap_config *regmap_conf; 233 struct completion cs_completion; 234 struct clk *kclk; 235 struct snd_dmaengine_dai_dma_data dma_params; 236 struct snd_pcm_substream *substream; 237 struct snd_dma_buffer *dmab; 238 struct dma_chan *ctrl_chan; 239 struct dma_async_tx_descriptor *desc; 240 struct dma_slave_config slave_config; 241 dma_addr_t phys_addr; 242 spinlock_t lock; /* Sync enabling lock */ 243 unsigned char cs[SPDIFRX_CS_BYTES_NB]; 244 unsigned char ub[SPDIFRX_UB_BYTES_NB]; 245 int irq; 246 int refcount; 247 }; 248 249 static void stm32_spdifrx_dma_complete(void *data) 250 { 251 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data; 252 struct platform_device *pdev = spdifrx->pdev; 253 u32 *p_start = (u32 *)spdifrx->dmab->area; 254 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1; 255 u32 *ptr = p_start; 256 u16 *ub_ptr = (short *)spdifrx->ub; 257 int i = 0; 258 259 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 260 SPDIFRX_CR_CBDMAEN, 261 (unsigned int)~SPDIFRX_CR_CBDMAEN); 262 263 if (!spdifrx->dmab->area) 264 return; 265 266 while (ptr <= p_end) { 267 if (*ptr & SPDIFRX_CSR_SOB) 268 break; 269 ptr++; 270 } 271 272 if (ptr > p_end) { 273 dev_err(&pdev->dev, "Start of S/PDIF block not found\n"); 274 return; 275 } 276 277 while (i < SPDIFRX_CS_BYTES_NB) { 278 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr); 279 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++); 280 if (ptr > p_end) { 281 dev_err(&pdev->dev, "Failed to get channel status\n"); 282 return; 283 } 284 i++; 285 } 286 287 complete(&spdifrx->cs_completion); 288 } 289 290 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx) 291 { 292 dma_cookie_t cookie; 293 int err; 294 295 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan, 296 spdifrx->dmab->addr, 297 SPDIFRX_CSR_BUF_LENGTH, 298 DMA_DEV_TO_MEM, 299 DMA_CTRL_ACK); 300 if (!spdifrx->desc) 301 return -EINVAL; 302 303 spdifrx->desc->callback = stm32_spdifrx_dma_complete; 304 spdifrx->desc->callback_param = spdifrx; 305 cookie = dmaengine_submit(spdifrx->desc); 306 err = dma_submit_error(cookie); 307 if (err) 308 return -EINVAL; 309 310 dma_async_issue_pending(spdifrx->ctrl_chan); 311 312 return 0; 313 } 314 315 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx) 316 { 317 dmaengine_terminate_async(spdifrx->ctrl_chan); 318 } 319 320 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx) 321 { 322 int cr, cr_mask, imr, ret; 323 324 /* Enable IRQs */ 325 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE; 326 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr); 327 if (ret) 328 return ret; 329 330 spin_lock(&spdifrx->lock); 331 332 spdifrx->refcount++; 333 334 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 335 336 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) { 337 /* 338 * Start sync if SPDIFRX is still in idle state. 339 * SPDIFRX reception enabled when sync done 340 */ 341 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n"); 342 343 /* 344 * SPDIFRX configuration: 345 * Wait for activity before starting sync process. This avoid 346 * to issue sync errors when spdif signal is missing on input. 347 * Preamble, CS, user, validity and parity error bits not copied 348 * to DR register. 349 */ 350 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK | 351 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO; 352 cr_mask = cr; 353 354 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 355 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK; 356 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 357 cr_mask, cr); 358 if (ret < 0) 359 dev_err(&spdifrx->pdev->dev, 360 "Failed to start synchronization\n"); 361 } 362 363 spin_unlock(&spdifrx->lock); 364 365 return ret; 366 } 367 368 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx) 369 { 370 int cr, cr_mask, reg; 371 372 spin_lock(&spdifrx->lock); 373 374 if (--spdifrx->refcount) { 375 spin_unlock(&spdifrx->lock); 376 return; 377 } 378 379 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 380 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN; 381 382 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr); 383 384 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 385 SPDIFRX_XIMR_MASK, 0); 386 387 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 388 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK); 389 390 /* dummy read to clear CSRNE and RXNE in status register */ 391 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®); 392 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®); 393 394 spin_unlock(&spdifrx->lock); 395 } 396 397 static int stm32_spdifrx_dma_ctrl_register(struct device *dev, 398 struct stm32_spdifrx_data *spdifrx) 399 { 400 int ret; 401 402 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl"); 403 if (IS_ERR(spdifrx->ctrl_chan)) { 404 dev_err(dev, "dma_request_slave_channel failed\n"); 405 return PTR_ERR(spdifrx->ctrl_chan); 406 } 407 408 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer), 409 GFP_KERNEL); 410 if (!spdifrx->dmab) 411 return -ENOMEM; 412 413 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM; 414 spdifrx->dmab->dev.dev = dev; 415 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev, 416 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab); 417 if (ret < 0) { 418 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret); 419 return ret; 420 } 421 422 spdifrx->slave_config.direction = DMA_DEV_TO_MEM; 423 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr + 424 STM32_SPDIFRX_CSR); 425 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr; 426 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 427 spdifrx->slave_config.src_maxburst = 1; 428 429 ret = dmaengine_slave_config(spdifrx->ctrl_chan, 430 &spdifrx->slave_config); 431 if (ret < 0) { 432 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret); 433 spdifrx->ctrl_chan = NULL; 434 } 435 436 return ret; 437 }; 438 439 static const char * const spdifrx_enum_input[] = { 440 "in0", "in1", "in2", "in3" 441 }; 442 443 /* By default CS bits are retrieved from channel A */ 444 static const char * const spdifrx_enum_cs_channel[] = { 445 "A", "B" 446 }; 447 448 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input, 449 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT, 450 spdifrx_enum_input); 451 452 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel, 453 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT, 454 spdifrx_enum_cs_channel); 455 456 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol, 457 struct snd_ctl_elem_info *uinfo) 458 { 459 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 460 uinfo->count = 1; 461 462 return 0; 463 } 464 465 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol, 466 struct snd_ctl_elem_info *uinfo) 467 { 468 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 469 uinfo->count = 1; 470 471 return 0; 472 } 473 474 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx) 475 { 476 int ret = 0; 477 478 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB); 479 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB); 480 481 pinctrl_pm_select_default_state(&spdifrx->pdev->dev); 482 483 ret = stm32_spdifrx_dma_ctrl_start(spdifrx); 484 if (ret < 0) 485 return ret; 486 487 ret = clk_prepare_enable(spdifrx->kclk); 488 if (ret) { 489 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 490 return ret; 491 } 492 493 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 494 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN); 495 if (ret < 0) 496 goto end; 497 498 ret = stm32_spdifrx_start_sync(spdifrx); 499 if (ret < 0) 500 goto end; 501 502 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion, 503 msecs_to_jiffies(100)) 504 <= 0) { 505 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n"); 506 ret = -EAGAIN; 507 } 508 509 stm32_spdifrx_stop(spdifrx); 510 stm32_spdifrx_dma_ctrl_stop(spdifrx); 511 512 end: 513 clk_disable_unprepare(spdifrx->kclk); 514 pinctrl_pm_select_sleep_state(&spdifrx->pdev->dev); 515 516 return ret; 517 } 518 519 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol, 520 struct snd_ctl_elem_value *ucontrol) 521 { 522 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 523 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 524 525 stm32_spdifrx_get_ctrl_data(spdifrx); 526 527 ucontrol->value.iec958.status[0] = spdifrx->cs[0]; 528 ucontrol->value.iec958.status[1] = spdifrx->cs[1]; 529 ucontrol->value.iec958.status[2] = spdifrx->cs[2]; 530 ucontrol->value.iec958.status[3] = spdifrx->cs[3]; 531 ucontrol->value.iec958.status[4] = spdifrx->cs[4]; 532 533 return 0; 534 } 535 536 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol, 537 struct snd_ctl_elem_value *ucontrol) 538 { 539 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 540 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 541 542 stm32_spdifrx_get_ctrl_data(spdifrx); 543 544 ucontrol->value.iec958.status[0] = spdifrx->ub[0]; 545 ucontrol->value.iec958.status[1] = spdifrx->ub[1]; 546 ucontrol->value.iec958.status[2] = spdifrx->ub[2]; 547 ucontrol->value.iec958.status[3] = spdifrx->ub[3]; 548 ucontrol->value.iec958.status[4] = spdifrx->ub[4]; 549 550 return 0; 551 } 552 553 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = { 554 /* Channel status control */ 555 { 556 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 557 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 558 .access = SNDRV_CTL_ELEM_ACCESS_READ | 559 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 560 .info = stm32_spdifrx_info, 561 .get = stm32_spdifrx_capture_get, 562 }, 563 /* User bits control */ 564 { 565 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 566 .name = "IEC958 User Bit Capture Default", 567 .access = SNDRV_CTL_ELEM_ACCESS_READ | 568 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 569 .info = stm32_spdifrx_ub_info, 570 .get = stm32_spdif_user_bits_get, 571 }, 572 }; 573 574 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = { 575 SOC_ENUM("SPDIFRX input", ctrl_enum_input), 576 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel), 577 }; 578 579 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai) 580 { 581 int ret; 582 583 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls, 584 ARRAY_SIZE(stm32_spdifrx_iec_ctrls)); 585 if (ret < 0) 586 return ret; 587 588 return snd_soc_add_component_controls(cpu_dai->component, 589 stm32_spdifrx_ctrls, 590 ARRAY_SIZE(stm32_spdifrx_ctrls)); 591 } 592 593 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai) 594 { 595 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev); 596 597 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr + 598 STM32_SPDIFRX_DR); 599 spdifrx->dma_params.maxburst = 1; 600 601 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 602 603 return stm32_spdifrx_dai_register_ctrls(cpu_dai); 604 } 605 606 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg) 607 { 608 switch (reg) { 609 case STM32_SPDIFRX_CR: 610 case STM32_SPDIFRX_IMR: 611 case STM32_SPDIFRX_SR: 612 case STM32_SPDIFRX_IFCR: 613 case STM32_SPDIFRX_DR: 614 case STM32_SPDIFRX_CSR: 615 case STM32_SPDIFRX_DIR: 616 case STM32_SPDIFRX_VERR: 617 case STM32_SPDIFRX_IDR: 618 case STM32_SPDIFRX_SIDR: 619 return true; 620 default: 621 return false; 622 } 623 } 624 625 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 626 { 627 switch (reg) { 628 case STM32_SPDIFRX_DR: 629 case STM32_SPDIFRX_CSR: 630 case STM32_SPDIFRX_SR: 631 case STM32_SPDIFRX_DIR: 632 return true; 633 default: 634 return false; 635 } 636 } 637 638 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 639 { 640 switch (reg) { 641 case STM32_SPDIFRX_CR: 642 case STM32_SPDIFRX_IMR: 643 case STM32_SPDIFRX_IFCR: 644 return true; 645 default: 646 return false; 647 } 648 } 649 650 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = { 651 .reg_bits = 32, 652 .reg_stride = 4, 653 .val_bits = 32, 654 .max_register = STM32_SPDIFRX_SIDR, 655 .readable_reg = stm32_spdifrx_readable_reg, 656 .volatile_reg = stm32_spdifrx_volatile_reg, 657 .writeable_reg = stm32_spdifrx_writeable_reg, 658 .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1, 659 .fast_io = true, 660 .cache_type = REGCACHE_FLAT, 661 }; 662 663 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid) 664 { 665 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid; 666 struct snd_pcm_substream *substream = spdifrx->substream; 667 struct platform_device *pdev = spdifrx->pdev; 668 unsigned int cr, mask, sr, imr; 669 unsigned int flags; 670 int err = 0, err_xrun = 0; 671 672 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr); 673 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr); 674 675 mask = imr & SPDIFRX_XIMR_MASK; 676 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */ 677 if (mask & SPDIFRX_IMR_IFEIE) 678 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2); 679 680 flags = sr & mask; 681 if (!flags) { 682 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n", 683 sr, imr); 684 return IRQ_NONE; 685 } 686 687 /* Clear IRQs */ 688 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 689 SPDIFRX_XIFCR_MASK, flags); 690 691 if (flags & SPDIFRX_SR_PERR) { 692 dev_dbg(&pdev->dev, "Parity error\n"); 693 err_xrun = 1; 694 } 695 696 if (flags & SPDIFRX_SR_OVR) { 697 dev_dbg(&pdev->dev, "Overrun error\n"); 698 err_xrun = 1; 699 } 700 701 if (flags & SPDIFRX_SR_SBD) 702 dev_dbg(&pdev->dev, "Synchronization block detected\n"); 703 704 if (flags & SPDIFRX_SR_SYNCD) { 705 dev_dbg(&pdev->dev, "Synchronization done\n"); 706 707 /* Enable spdifrx */ 708 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE); 709 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 710 SPDIFRX_CR_SPDIFEN_MASK, cr); 711 } 712 713 if (flags & SPDIFRX_SR_FERR) { 714 dev_dbg(&pdev->dev, "Frame error\n"); 715 err = 1; 716 } 717 718 if (flags & SPDIFRX_SR_SERR) { 719 dev_dbg(&pdev->dev, "Synchronization error\n"); 720 err = 1; 721 } 722 723 if (flags & SPDIFRX_SR_TERR) { 724 dev_dbg(&pdev->dev, "Timeout error\n"); 725 err = 1; 726 } 727 728 if (err) { 729 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */ 730 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 731 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 732 SPDIFRX_CR_SPDIFEN_MASK, cr); 733 734 if (substream) 735 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED); 736 737 return IRQ_HANDLED; 738 } 739 740 if (err_xrun && substream) 741 snd_pcm_stop_xrun(substream); 742 743 return IRQ_HANDLED; 744 } 745 746 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream, 747 struct snd_soc_dai *cpu_dai) 748 { 749 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 750 int ret; 751 752 spdifrx->substream = substream; 753 754 ret = clk_prepare_enable(spdifrx->kclk); 755 if (ret) 756 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 757 758 return ret; 759 } 760 761 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream, 762 struct snd_pcm_hw_params *params, 763 struct snd_soc_dai *cpu_dai) 764 { 765 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 766 int data_size = params_width(params); 767 int fmt; 768 769 switch (data_size) { 770 case 16: 771 fmt = SPDIFRX_DRFMT_PACKED; 772 break; 773 case 32: 774 fmt = SPDIFRX_DRFMT_LEFT; 775 break; 776 default: 777 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n"); 778 return -EINVAL; 779 } 780 781 /* 782 * Set buswidth to 4 bytes for all data formats. 783 * Packed format: transfer 2 x 2 bytes samples 784 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte 785 */ 786 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 787 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 788 789 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 790 SPDIFRX_CR_DRFMT_MASK, 791 SPDIFRX_CR_DRFMTSET(fmt)); 792 } 793 794 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 795 struct snd_soc_dai *cpu_dai) 796 { 797 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 798 int ret = 0; 799 800 switch (cmd) { 801 case SNDRV_PCM_TRIGGER_START: 802 case SNDRV_PCM_TRIGGER_RESUME: 803 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 804 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 805 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE); 806 807 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 808 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN); 809 810 ret = stm32_spdifrx_start_sync(spdifrx); 811 break; 812 case SNDRV_PCM_TRIGGER_SUSPEND: 813 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 814 case SNDRV_PCM_TRIGGER_STOP: 815 stm32_spdifrx_stop(spdifrx); 816 break; 817 default: 818 return -EINVAL; 819 } 820 821 return ret; 822 } 823 824 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream, 825 struct snd_soc_dai *cpu_dai) 826 { 827 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 828 829 spdifrx->substream = NULL; 830 clk_disable_unprepare(spdifrx->kclk); 831 } 832 833 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = { 834 .startup = stm32_spdifrx_startup, 835 .hw_params = stm32_spdifrx_hw_params, 836 .trigger = stm32_spdifrx_trigger, 837 .shutdown = stm32_spdifrx_shutdown, 838 }; 839 840 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = { 841 { 842 .probe = stm32_spdifrx_dai_probe, 843 .capture = { 844 .stream_name = "CPU-Capture", 845 .channels_min = 1, 846 .channels_max = 2, 847 .rates = SNDRV_PCM_RATE_8000_192000, 848 .formats = SNDRV_PCM_FMTBIT_S32_LE | 849 SNDRV_PCM_FMTBIT_S16_LE, 850 }, 851 .ops = &stm32_spdifrx_pcm_dai_ops, 852 } 853 }; 854 855 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = { 856 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 857 .buffer_bytes_max = 8 * PAGE_SIZE, 858 .period_bytes_min = 1024, 859 .period_bytes_max = 4 * PAGE_SIZE, 860 .periods_min = 2, 861 .periods_max = 8, 862 }; 863 864 static const struct snd_soc_component_driver stm32_spdifrx_component = { 865 .name = "stm32-spdifrx", 866 }; 867 868 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = { 869 .pcm_hardware = &stm32_spdifrx_pcm_hw, 870 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 871 }; 872 873 static const struct of_device_id stm32_spdifrx_ids[] = { 874 { 875 .compatible = "st,stm32h7-spdifrx", 876 .data = &stm32_h7_spdifrx_regmap_conf 877 }, 878 {} 879 }; 880 881 static int stm32_spdifrx_parse_of(struct platform_device *pdev, 882 struct stm32_spdifrx_data *spdifrx) 883 { 884 struct device_node *np = pdev->dev.of_node; 885 const struct of_device_id *of_id; 886 struct resource *res; 887 888 if (!np) 889 return -ENODEV; 890 891 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev); 892 if (of_id) 893 spdifrx->regmap_conf = 894 (const struct regmap_config *)of_id->data; 895 else 896 return -EINVAL; 897 898 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 899 spdifrx->base = devm_ioremap_resource(&pdev->dev, res); 900 if (IS_ERR(spdifrx->base)) 901 return PTR_ERR(spdifrx->base); 902 903 spdifrx->phys_addr = res->start; 904 905 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk"); 906 if (IS_ERR(spdifrx->kclk)) { 907 dev_err(&pdev->dev, "Could not get kclk\n"); 908 return PTR_ERR(spdifrx->kclk); 909 } 910 911 spdifrx->irq = platform_get_irq(pdev, 0); 912 if (spdifrx->irq < 0) 913 return spdifrx->irq; 914 915 return 0; 916 } 917 918 static int stm32_spdifrx_probe(struct platform_device *pdev) 919 { 920 struct stm32_spdifrx_data *spdifrx; 921 struct reset_control *rst; 922 const struct snd_dmaengine_pcm_config *pcm_config = NULL; 923 u32 ver, idr; 924 int ret; 925 926 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL); 927 if (!spdifrx) 928 return -ENOMEM; 929 930 spdifrx->pdev = pdev; 931 init_completion(&spdifrx->cs_completion); 932 spin_lock_init(&spdifrx->lock); 933 934 platform_set_drvdata(pdev, spdifrx); 935 936 ret = stm32_spdifrx_parse_of(pdev, spdifrx); 937 if (ret) 938 return ret; 939 940 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk", 941 spdifrx->base, 942 spdifrx->regmap_conf); 943 if (IS_ERR(spdifrx->regmap)) { 944 dev_err(&pdev->dev, "Regmap init failed\n"); 945 return PTR_ERR(spdifrx->regmap); 946 } 947 948 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0, 949 dev_name(&pdev->dev), spdifrx); 950 if (ret) { 951 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 952 return ret; 953 } 954 955 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 956 if (!IS_ERR(rst)) { 957 reset_control_assert(rst); 958 udelay(2); 959 reset_control_deassert(rst); 960 } 961 962 ret = devm_snd_soc_register_component(&pdev->dev, 963 &stm32_spdifrx_component, 964 stm32_spdifrx_dai, 965 ARRAY_SIZE(stm32_spdifrx_dai)); 966 if (ret) 967 return ret; 968 969 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx); 970 if (ret) 971 goto error; 972 973 pcm_config = &stm32_spdifrx_pcm_config; 974 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0); 975 if (ret) { 976 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret); 977 goto error; 978 } 979 980 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr); 981 if (ret) 982 goto error; 983 984 if (idr == SPDIFRX_IPIDR_NUMBER) { 985 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver); 986 987 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n", 988 FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver), 989 FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver)); 990 } 991 992 return ret; 993 994 error: 995 if (!IS_ERR(spdifrx->ctrl_chan)) 996 dma_release_channel(spdifrx->ctrl_chan); 997 if (spdifrx->dmab) 998 snd_dma_free_pages(spdifrx->dmab); 999 1000 return ret; 1001 } 1002 1003 static int stm32_spdifrx_remove(struct platform_device *pdev) 1004 { 1005 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev); 1006 1007 if (spdifrx->ctrl_chan) 1008 dma_release_channel(spdifrx->ctrl_chan); 1009 1010 if (spdifrx->dmab) 1011 snd_dma_free_pages(spdifrx->dmab); 1012 1013 return 0; 1014 } 1015 1016 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids); 1017 1018 #ifdef CONFIG_PM_SLEEP 1019 static int stm32_spdifrx_suspend(struct device *dev) 1020 { 1021 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1022 1023 regcache_cache_only(spdifrx->regmap, true); 1024 regcache_mark_dirty(spdifrx->regmap); 1025 1026 return 0; 1027 } 1028 1029 static int stm32_spdifrx_resume(struct device *dev) 1030 { 1031 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1032 1033 regcache_cache_only(spdifrx->regmap, false); 1034 1035 return regcache_sync(spdifrx->regmap); 1036 } 1037 #endif /* CONFIG_PM_SLEEP */ 1038 1039 static const struct dev_pm_ops stm32_spdifrx_pm_ops = { 1040 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume) 1041 }; 1042 1043 static struct platform_driver stm32_spdifrx_driver = { 1044 .driver = { 1045 .name = "st,stm32-spdifrx", 1046 .of_match_table = stm32_spdifrx_ids, 1047 .pm = &stm32_spdifrx_pm_ops, 1048 }, 1049 .probe = stm32_spdifrx_probe, 1050 .remove = stm32_spdifrx_remove, 1051 }; 1052 1053 module_platform_driver(stm32_spdifrx_driver); 1054 1055 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface"); 1056 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 1057 MODULE_ALIAS("platform:stm32-spdifrx"); 1058 MODULE_LICENSE("GPL v2"); 1059