1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 18 #include <sound/asoundef.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 23 #include "stm32_sai.h" 24 25 #define SAI_FREE_PROTOCOL 0x0 26 #define SAI_SPDIF_PROTOCOL 0x1 27 28 #define SAI_SLOT_SIZE_AUTO 0x0 29 #define SAI_SLOT_SIZE_16 0x1 30 #define SAI_SLOT_SIZE_32 0x2 31 32 #define SAI_DATASIZE_8 0x2 33 #define SAI_DATASIZE_10 0x3 34 #define SAI_DATASIZE_16 0x4 35 #define SAI_DATASIZE_20 0x5 36 #define SAI_DATASIZE_24 0x6 37 #define SAI_DATASIZE_32 0x7 38 39 #define STM_SAI_DAI_NAME_SIZE 15 40 41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 43 44 #define STM_SAI_A_ID 0x0 45 #define STM_SAI_B_ID 0x1 46 47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 48 49 #define SAI_SYNC_NONE 0x0 50 #define SAI_SYNC_INTERNAL 0x1 51 #define SAI_SYNC_EXTERNAL 0x2 52 53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm) 55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm) 56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4((x)->pdata)) 57 58 #define SAI_IEC60958_BLOCK_FRAMES 192 59 #define SAI_IEC60958_STATUS_BYTES 24 60 61 #define SAI_MCLK_NAME_LEN 32 62 #define SAI_RATE_11K 11025 63 #define SAI_MAX_SAMPLE_RATE_8K 192000 64 #define SAI_MAX_SAMPLE_RATE_11K 176400 65 #define SAI_CK_RATE_TOLERANCE 1000 /* ppm */ 66 67 /** 68 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 69 * @pdev: device data pointer 70 * @regmap: SAI register map pointer 71 * @regmap_config: SAI sub block register map configuration pointer 72 * @dma_params: dma configuration data for rx or tx channel 73 * @cpu_dai_drv: DAI driver data pointer 74 * @cpu_dai: DAI runtime data pointer 75 * @substream: PCM substream data pointer 76 * @pdata: SAI block parent data pointer 77 * @np_sync_provider: synchronization provider node 78 * @sai_ck: kernel clock feeding the SAI clock generator 79 * @sai_mclk: master clock from SAI mclk provider 80 * @phys_addr: SAI registers physical base address 81 * @mclk_rate: SAI block master clock frequency (Hz). set at init 82 * @id: SAI sub block id corresponding to sub-block A or B 83 * @dir: SAI block direction (playback or capture). set at init 84 * @master: SAI block mode flag. (true=master, false=slave) set at init 85 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 86 * @sai_ck_used: flag set while exclusivity on SAI kernel clock is active 87 * @fmt: SAI block format. relevant only for custom protocols. set at init 88 * @sync: SAI block synchronization mode. (none, internal or external) 89 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 90 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 91 * @fs_length: frame synchronization length. depends on protocol settings 92 * @slots: rx or tx slot number 93 * @slot_width: rx or tx slot width in bits 94 * @slot_mask: rx or tx active slots mask. set at init or at runtime 95 * @data_size: PCM data width. corresponds to PCM substream width. 96 * @spdif_frm_cnt: S/PDIF playback frame counter 97 * @iec958: iec958 data 98 * @ctrl_lock: control lock 99 * @irq_lock: prevent race condition with IRQ 100 * @set_sai_ck_rate: set SAI kernel clock rate 101 * @put_sai_ck_rate: put SAI kernel clock rate 102 */ 103 struct stm32_sai_sub_data { 104 struct platform_device *pdev; 105 struct regmap *regmap; 106 const struct regmap_config *regmap_config; 107 struct snd_dmaengine_dai_dma_data dma_params; 108 struct snd_soc_dai_driver cpu_dai_drv; 109 struct snd_soc_dai *cpu_dai; 110 struct snd_pcm_substream *substream; 111 struct stm32_sai_data *pdata; 112 struct device_node *np_sync_provider; 113 struct clk *sai_ck; 114 struct clk *sai_mclk; 115 dma_addr_t phys_addr; 116 unsigned int mclk_rate; 117 unsigned int id; 118 int dir; 119 bool master; 120 bool spdif; 121 bool sai_ck_used; 122 int fmt; 123 int sync; 124 int synco; 125 int synci; 126 int fs_length; 127 int slots; 128 int slot_width; 129 int slot_mask; 130 int data_size; 131 unsigned int spdif_frm_cnt; 132 struct snd_aes_iec958 iec958; 133 struct mutex ctrl_lock; /* protect resources accessed by controls */ 134 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 135 int (*set_sai_ck_rate)(struct stm32_sai_sub_data *sai, unsigned int rate); 136 void (*put_sai_ck_rate)(struct stm32_sai_sub_data *sai); 137 }; 138 139 enum stm32_sai_fifo_th { 140 STM_SAI_FIFO_TH_EMPTY, 141 STM_SAI_FIFO_TH_QUARTER, 142 STM_SAI_FIFO_TH_HALF, 143 STM_SAI_FIFO_TH_3_QUARTER, 144 STM_SAI_FIFO_TH_FULL, 145 }; 146 147 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 148 { 149 switch (reg) { 150 case STM_SAI_CR1_REGX: 151 case STM_SAI_CR2_REGX: 152 case STM_SAI_FRCR_REGX: 153 case STM_SAI_SLOTR_REGX: 154 case STM_SAI_IMR_REGX: 155 case STM_SAI_SR_REGX: 156 case STM_SAI_CLRFR_REGX: 157 case STM_SAI_DR_REGX: 158 case STM_SAI_PDMCR_REGX: 159 case STM_SAI_PDMLY_REGX: 160 return true; 161 default: 162 return false; 163 } 164 } 165 166 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 167 { 168 switch (reg) { 169 case STM_SAI_DR_REGX: 170 case STM_SAI_SR_REGX: 171 return true; 172 default: 173 return false; 174 } 175 } 176 177 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 178 { 179 switch (reg) { 180 case STM_SAI_CR1_REGX: 181 case STM_SAI_CR2_REGX: 182 case STM_SAI_FRCR_REGX: 183 case STM_SAI_SLOTR_REGX: 184 case STM_SAI_IMR_REGX: 185 case STM_SAI_CLRFR_REGX: 186 case STM_SAI_DR_REGX: 187 case STM_SAI_PDMCR_REGX: 188 case STM_SAI_PDMLY_REGX: 189 return true; 190 default: 191 return false; 192 } 193 } 194 195 static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai, 196 unsigned int reg, unsigned int mask, 197 unsigned int val) 198 { 199 int ret; 200 201 ret = clk_enable(sai->pdata->pclk); 202 if (ret < 0) 203 return ret; 204 205 ret = regmap_update_bits(sai->regmap, reg, mask, val); 206 207 clk_disable(sai->pdata->pclk); 208 209 return ret; 210 } 211 212 static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai, 213 unsigned int reg, unsigned int mask, 214 unsigned int val) 215 { 216 int ret; 217 218 ret = clk_enable(sai->pdata->pclk); 219 if (ret < 0) 220 return ret; 221 222 ret = regmap_write_bits(sai->regmap, reg, mask, val); 223 224 clk_disable(sai->pdata->pclk); 225 226 return ret; 227 } 228 229 static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai, 230 unsigned int reg, unsigned int *val) 231 { 232 int ret; 233 234 ret = clk_enable(sai->pdata->pclk); 235 if (ret < 0) 236 return ret; 237 238 ret = regmap_read(sai->regmap, reg, val); 239 240 clk_disable(sai->pdata->pclk); 241 242 return ret; 243 } 244 245 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 246 .reg_bits = 32, 247 .reg_stride = 4, 248 .val_bits = 32, 249 .max_register = STM_SAI_DR_REGX, 250 .readable_reg = stm32_sai_sub_readable_reg, 251 .volatile_reg = stm32_sai_sub_volatile_reg, 252 .writeable_reg = stm32_sai_sub_writeable_reg, 253 .fast_io = true, 254 .cache_type = REGCACHE_FLAT, 255 }; 256 257 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 258 .reg_bits = 32, 259 .reg_stride = 4, 260 .val_bits = 32, 261 .max_register = STM_SAI_PDMLY_REGX, 262 .readable_reg = stm32_sai_sub_readable_reg, 263 .volatile_reg = stm32_sai_sub_volatile_reg, 264 .writeable_reg = stm32_sai_sub_writeable_reg, 265 .fast_io = true, 266 .cache_type = REGCACHE_FLAT, 267 }; 268 269 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 270 struct snd_ctl_elem_info *uinfo) 271 { 272 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 273 uinfo->count = 1; 274 275 return 0; 276 } 277 278 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 279 struct snd_ctl_elem_value *uctl) 280 { 281 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 282 283 mutex_lock(&sai->ctrl_lock); 284 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 285 mutex_unlock(&sai->ctrl_lock); 286 287 return 0; 288 } 289 290 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 291 struct snd_ctl_elem_value *uctl) 292 { 293 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 294 295 mutex_lock(&sai->ctrl_lock); 296 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 297 mutex_unlock(&sai->ctrl_lock); 298 299 return 0; 300 } 301 302 static const struct snd_kcontrol_new iec958_ctls = { 303 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 304 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 305 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 306 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 307 .info = snd_pcm_iec958_info, 308 .get = snd_pcm_iec958_get, 309 .put = snd_pcm_iec958_put, 310 }; 311 312 struct stm32_sai_mclk_data { 313 struct clk_hw hw; 314 unsigned long freq; 315 struct stm32_sai_sub_data *sai_data; 316 }; 317 318 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 319 #define STM32_SAI_MAX_CLKS 1 320 321 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 322 unsigned long input_rate, 323 unsigned long output_rate) 324 { 325 int version = sai->pdata->conf.version; 326 int div; 327 328 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 329 if (div > SAI_XCR1_MCKDIV_MAX(version) || div <= 0) { 330 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 331 return -EINVAL; 332 } 333 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 334 335 if (input_rate % div) 336 dev_dbg(&sai->pdev->dev, 337 "Rate not accurate. requested (%ld), actual (%ld)\n", 338 output_rate, input_rate / div); 339 340 return div; 341 } 342 343 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 344 unsigned int div) 345 { 346 int version = sai->pdata->conf.version; 347 int ret, cr1, mask; 348 349 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 350 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 351 return -EINVAL; 352 } 353 354 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 355 cr1 = SAI_XCR1_MCKDIV_SET(div); 356 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1); 357 if (ret < 0) 358 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 359 360 return ret; 361 } 362 363 static bool stm32_sai_rate_accurate(unsigned int max_rate, unsigned int rate) 364 { 365 u64 delta, dividend; 366 int ratio; 367 368 ratio = DIV_ROUND_CLOSEST(max_rate, rate); 369 if (!ratio) 370 return false; 371 372 dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate))); 373 delta = div_u64(dividend, max_rate); 374 375 if (delta <= SAI_CK_RATE_TOLERANCE) 376 return true; 377 378 return false; 379 } 380 381 static int stm32_sai_set_parent_clk(struct stm32_sai_sub_data *sai, 382 unsigned int rate) 383 { 384 struct platform_device *pdev = sai->pdev; 385 struct clk *parent_clk = sai->pdata->clk_x8k; 386 int ret; 387 388 if (!(rate % SAI_RATE_11K)) 389 parent_clk = sai->pdata->clk_x11k; 390 391 ret = clk_set_parent(sai->sai_ck, parent_clk); 392 if (ret) 393 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", 394 ret, ret == -EBUSY ? 395 "Active stream rates conflict\n" : "\n"); 396 397 return ret; 398 } 399 400 static void stm32_sai_put_parent_rate(struct stm32_sai_sub_data *sai) 401 { 402 if (sai->sai_ck_used) { 403 sai->sai_ck_used = false; 404 clk_rate_exclusive_put(sai->sai_ck); 405 } 406 } 407 408 static int stm32_sai_set_parent_rate(struct stm32_sai_sub_data *sai, 409 unsigned int rate) 410 { 411 struct platform_device *pdev = sai->pdev; 412 unsigned int sai_ck_rate, sai_ck_max_rate, sai_ck_min_rate, sai_curr_rate, sai_new_rate; 413 int div, ret; 414 415 /* 416 * Set minimum and maximum expected kernel clock frequency 417 * - mclk on or spdif: 418 * f_sai_ck = MCKDIV * mclk-fs * fs 419 * Here typical 256 ratio is assumed for mclk-fs 420 * - mclk off: 421 * f_sai_ck = MCKDIV * FRL * fs 422 * Where FRL=[8..256], MCKDIV=[1..n] (n depends on SAI version) 423 * Set constraint MCKDIV * FRL <= 256, to ensure MCKDIV is in available range 424 * f_sai_ck = sai_ck_max_rate * pow_of_two(FRL) / 256 425 */ 426 sai_ck_min_rate = rate * 256; 427 if (!(rate % SAI_RATE_11K)) 428 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_11K * 256; 429 else 430 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_8K * 256; 431 432 if (!sai->sai_mclk && !STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 433 sai_ck_min_rate = rate * sai->fs_length; 434 sai_ck_max_rate /= DIV_ROUND_CLOSEST(256, roundup_pow_of_two(sai->fs_length)); 435 } 436 437 /* 438 * Request exclusivity, as the clock is shared by SAI sub-blocks and by 439 * some SAI instances. This allows to ensure that the rate cannot be 440 * changed while one or more SAIs are using the clock. 441 */ 442 clk_rate_exclusive_get(sai->sai_ck); 443 sai->sai_ck_used = true; 444 445 /* 446 * Check current kernel clock rate. If it gives the expected accuracy 447 * return immediately. 448 */ 449 sai_curr_rate = clk_get_rate(sai->sai_ck); 450 dev_dbg(&pdev->dev, "kernel clock rate: min [%u], max [%u], current [%u]", 451 sai_ck_min_rate, sai_ck_max_rate, sai_curr_rate); 452 if (stm32_sai_rate_accurate(sai_ck_max_rate, sai_curr_rate) && 453 sai_curr_rate >= sai_ck_min_rate) 454 return 0; 455 456 /* 457 * Otherwise try to set the maximum rate and check the new actual rate. 458 * If the new rate does not give the expected accuracy, try to set 459 * lower rates for the kernel clock. 460 */ 461 sai_ck_rate = sai_ck_max_rate; 462 div = 1; 463 do { 464 /* Check new rate accuracy. Return if ok */ 465 sai_new_rate = clk_round_rate(sai->sai_ck, sai_ck_rate); 466 if (stm32_sai_rate_accurate(sai_ck_rate, sai_new_rate)) { 467 ret = clk_set_rate(sai->sai_ck, sai_ck_rate); 468 if (ret) { 469 dev_err(&pdev->dev, "Error %d setting sai_ck rate. %s", 470 ret, ret == -EBUSY ? 471 "Active stream rates may be in conflict\n" : "\n"); 472 goto err; 473 } 474 475 return 0; 476 } 477 478 /* Try a lower frequency */ 479 div++; 480 sai_ck_rate = sai_ck_max_rate / div; 481 } while (sai_ck_rate >= sai_ck_min_rate); 482 483 /* No accurate rate found */ 484 dev_err(&pdev->dev, "Failed to find an accurate rate"); 485 486 err: 487 stm32_sai_put_parent_rate(sai); 488 489 return -EINVAL; 490 } 491 492 static int stm32_sai_mclk_determine_rate(struct clk_hw *hw, 493 struct clk_rate_request *req) 494 { 495 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 496 struct stm32_sai_sub_data *sai = mclk->sai_data; 497 int div; 498 499 div = stm32_sai_get_clk_div(sai, req->best_parent_rate, req->rate); 500 if (div <= 0) 501 return -EINVAL; 502 503 mclk->freq = req->best_parent_rate / div; 504 505 req->rate = mclk->freq; 506 507 return 0; 508 } 509 510 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 511 unsigned long parent_rate) 512 { 513 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 514 515 return mclk->freq; 516 } 517 518 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 519 unsigned long parent_rate) 520 { 521 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 522 struct stm32_sai_sub_data *sai = mclk->sai_data; 523 int div, ret; 524 525 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 526 if (div < 0) 527 return div; 528 529 ret = stm32_sai_set_clk_div(sai, div); 530 if (ret) 531 return ret; 532 533 mclk->freq = rate; 534 535 return 0; 536 } 537 538 static int stm32_sai_mclk_enable(struct clk_hw *hw) 539 { 540 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 541 struct stm32_sai_sub_data *sai = mclk->sai_data; 542 543 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 544 545 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 546 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 547 } 548 549 static void stm32_sai_mclk_disable(struct clk_hw *hw) 550 { 551 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 552 struct stm32_sai_sub_data *sai = mclk->sai_data; 553 554 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 555 556 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 557 } 558 559 static const struct clk_ops mclk_ops = { 560 .enable = stm32_sai_mclk_enable, 561 .disable = stm32_sai_mclk_disable, 562 .recalc_rate = stm32_sai_mclk_recalc_rate, 563 .determine_rate = stm32_sai_mclk_determine_rate, 564 .set_rate = stm32_sai_mclk_set_rate, 565 }; 566 567 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 568 { 569 struct clk_hw *hw; 570 struct stm32_sai_mclk_data *mclk; 571 struct device *dev = &sai->pdev->dev; 572 const char *pname = __clk_get_name(sai->sai_ck); 573 char *mclk_name, *p, *s = (char *)pname; 574 int ret, i = 0; 575 576 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 577 if (!mclk) 578 return -ENOMEM; 579 580 mclk_name = devm_kcalloc(dev, sizeof(char), 581 SAI_MCLK_NAME_LEN, GFP_KERNEL); 582 if (!mclk_name) 583 return -ENOMEM; 584 585 /* 586 * Forge mclk clock name from parent clock name and suffix. 587 * String after "_" char is stripped in parent name. 588 */ 589 p = mclk_name; 590 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 591 *p++ = *s++; 592 i++; 593 } 594 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 595 596 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 597 mclk->sai_data = sai; 598 hw = &mclk->hw; 599 600 dev_dbg(dev, "Register master clock %s\n", mclk_name); 601 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 602 if (ret) { 603 dev_err(dev, "mclk register returned %d\n", ret); 604 return ret; 605 } 606 sai->sai_mclk = hw->clk; 607 608 /* register mclk provider */ 609 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 610 } 611 612 static irqreturn_t stm32_sai_isr(int irq, void *devid) 613 { 614 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 615 struct platform_device *pdev = sai->pdev; 616 unsigned int sr, imr, flags; 617 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 618 619 stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr); 620 stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr); 621 622 flags = sr & imr; 623 if (!flags) 624 return IRQ_NONE; 625 626 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 627 SAI_XCLRFR_MASK); 628 629 if (!sai->substream) { 630 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 631 return IRQ_NONE; 632 } 633 634 if (flags & SAI_XIMR_OVRUDRIE) { 635 dev_err(&pdev->dev, "IRQ %s\n", 636 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 637 status = SNDRV_PCM_STATE_XRUN; 638 } 639 640 if (flags & SAI_XIMR_MUTEDETIE) 641 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 642 643 if (flags & SAI_XIMR_WCKCFGIE) { 644 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 645 status = SNDRV_PCM_STATE_DISCONNECTED; 646 } 647 648 if (flags & SAI_XIMR_CNRDYIE) 649 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 650 651 if (flags & SAI_XIMR_AFSDETIE) { 652 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 653 status = SNDRV_PCM_STATE_XRUN; 654 } 655 656 if (flags & SAI_XIMR_LFSDETIE) { 657 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 658 status = SNDRV_PCM_STATE_XRUN; 659 } 660 661 spin_lock(&sai->irq_lock); 662 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) 663 snd_pcm_stop_xrun(sai->substream); 664 spin_unlock(&sai->irq_lock); 665 666 return IRQ_HANDLED; 667 } 668 669 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 670 int clk_id, unsigned int freq, int dir) 671 { 672 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 673 int ret; 674 675 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { 676 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 677 SAI_XCR1_NODIV, 678 freq ? 0 : SAI_XCR1_NODIV); 679 if (ret < 0) 680 return ret; 681 682 /* Assume shutdown if requested frequency is 0Hz */ 683 if (!freq) { 684 /* Release mclk rate only if rate was actually set */ 685 if (sai->mclk_rate) { 686 clk_rate_exclusive_put(sai->sai_mclk); 687 sai->mclk_rate = 0; 688 } 689 690 if (sai->put_sai_ck_rate) 691 sai->put_sai_ck_rate(sai); 692 693 return 0; 694 } 695 696 /* If master clock is used, configure SAI kernel clock now */ 697 ret = sai->set_sai_ck_rate(sai, freq); 698 if (ret) 699 return ret; 700 701 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); 702 if (ret) { 703 dev_err(cpu_dai->dev, 704 ret == -EBUSY ? 705 "Active streams have incompatible rates" : 706 "Could not set mclk rate\n"); 707 return ret; 708 } 709 710 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 711 sai->mclk_rate = freq; 712 } 713 714 return 0; 715 } 716 717 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 718 u32 rx_mask, int slots, int slot_width) 719 { 720 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 721 int slotr, slotr_mask, slot_size; 722 723 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 724 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 725 return 0; 726 } 727 728 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 729 tx_mask, rx_mask, slots, slot_width); 730 731 switch (slot_width) { 732 case 16: 733 slot_size = SAI_SLOT_SIZE_16; 734 break; 735 case 32: 736 slot_size = SAI_SLOT_SIZE_32; 737 break; 738 default: 739 slot_size = SAI_SLOT_SIZE_AUTO; 740 break; 741 } 742 743 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 744 SAI_XSLOTR_NBSLOT_SET(slots - 1); 745 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 746 747 /* tx/rx mask set in machine init, if slot number defined in DT */ 748 if (STM_SAI_IS_PLAYBACK(sai)) { 749 sai->slot_mask = tx_mask; 750 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 751 } 752 753 if (STM_SAI_IS_CAPTURE(sai)) { 754 sai->slot_mask = rx_mask; 755 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 756 } 757 758 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 759 760 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 761 762 sai->slot_width = slot_width; 763 sai->slots = slots; 764 765 return 0; 766 } 767 768 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 769 { 770 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 771 int cr1, frcr = 0; 772 int cr1_mask, frcr_mask = 0; 773 int ret; 774 775 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 776 777 /* Do not generate master by default */ 778 cr1 = SAI_XCR1_NODIV; 779 cr1_mask = SAI_XCR1_NODIV; 780 781 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 782 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 783 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 784 goto conf_update; 785 } 786 787 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 788 789 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 790 /* SCK active high for all protocols */ 791 case SND_SOC_DAIFMT_I2S: 792 cr1 |= SAI_XCR1_CKSTR; 793 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 794 break; 795 /* Left justified */ 796 case SND_SOC_DAIFMT_MSB: 797 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 798 break; 799 /* Right justified */ 800 case SND_SOC_DAIFMT_LSB: 801 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 802 break; 803 case SND_SOC_DAIFMT_DSP_A: 804 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 805 break; 806 case SND_SOC_DAIFMT_DSP_B: 807 frcr |= SAI_XFRCR_FSPOL; 808 break; 809 default: 810 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 811 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 812 return -EINVAL; 813 } 814 815 cr1_mask |= SAI_XCR1_CKSTR; 816 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 817 SAI_XFRCR_FSDEF; 818 819 /* DAI clock strobing. Invert setting previously set */ 820 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 821 case SND_SOC_DAIFMT_NB_NF: 822 break; 823 case SND_SOC_DAIFMT_IB_NF: 824 cr1 ^= SAI_XCR1_CKSTR; 825 break; 826 case SND_SOC_DAIFMT_NB_IF: 827 frcr ^= SAI_XFRCR_FSPOL; 828 break; 829 case SND_SOC_DAIFMT_IB_IF: 830 /* Invert fs & sck */ 831 cr1 ^= SAI_XCR1_CKSTR; 832 frcr ^= SAI_XFRCR_FSPOL; 833 break; 834 default: 835 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 836 fmt & SND_SOC_DAIFMT_INV_MASK); 837 return -EINVAL; 838 } 839 cr1_mask |= SAI_XCR1_CKSTR; 840 frcr_mask |= SAI_XFRCR_FSPOL; 841 842 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 843 844 /* DAI clock master masks */ 845 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 846 case SND_SOC_DAIFMT_BC_FC: 847 /* codec is master */ 848 cr1 |= SAI_XCR1_SLAVE; 849 sai->master = false; 850 break; 851 case SND_SOC_DAIFMT_BP_FP: 852 sai->master = true; 853 break; 854 default: 855 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 856 fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); 857 return -EINVAL; 858 } 859 860 /* Set slave mode if sub-block is synchronized with another SAI */ 861 if (sai->sync) { 862 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 863 cr1 |= SAI_XCR1_SLAVE; 864 sai->master = false; 865 } 866 867 cr1_mask |= SAI_XCR1_SLAVE; 868 869 conf_update: 870 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 871 if (ret < 0) { 872 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 873 return ret; 874 } 875 876 sai->fmt = fmt; 877 878 return 0; 879 } 880 881 static int stm32_sai_startup(struct snd_pcm_substream *substream, 882 struct snd_soc_dai *cpu_dai) 883 { 884 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 885 int imr, cr2, ret; 886 unsigned long flags; 887 888 spin_lock_irqsave(&sai->irq_lock, flags); 889 sai->substream = substream; 890 spin_unlock_irqrestore(&sai->irq_lock, flags); 891 892 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 893 snd_pcm_hw_constraint_mask64(substream->runtime, 894 SNDRV_PCM_HW_PARAM_FORMAT, 895 SNDRV_PCM_FMTBIT_S32_LE); 896 snd_pcm_hw_constraint_single(substream->runtime, 897 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 898 } 899 900 ret = clk_prepare_enable(sai->sai_ck); 901 if (ret < 0) { 902 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 903 return ret; 904 } 905 906 /* Enable ITs */ 907 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, 908 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 909 910 imr = SAI_XIMR_OVRUDRIE; 911 if (STM_SAI_IS_CAPTURE(sai)) { 912 stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2); 913 if (cr2 & SAI_XCR2_MUTECNT_MASK) 914 imr |= SAI_XIMR_MUTEDETIE; 915 } 916 917 if (sai->master) 918 imr |= SAI_XIMR_WCKCFGIE; 919 else 920 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 921 922 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 923 SAI_XIMR_MASK, imr); 924 925 return 0; 926 } 927 928 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 929 struct snd_pcm_substream *substream, 930 struct snd_pcm_hw_params *params) 931 { 932 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 933 int cr1, cr1_mask, ret; 934 935 /* 936 * DMA bursts increment is set to 4 words. 937 * SAI fifo threshold is set to half fifo, to keep enough space 938 * for DMA incoming bursts. 939 */ 940 stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX, 941 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 942 SAI_XCR2_FFLUSH | 943 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 944 945 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 946 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 947 sai->spdif_frm_cnt = 0; 948 return 0; 949 } 950 951 /* Mode, data format and channel config */ 952 cr1_mask = SAI_XCR1_DS_MASK; 953 switch (params_format(params)) { 954 case SNDRV_PCM_FORMAT_S8: 955 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 956 break; 957 case SNDRV_PCM_FORMAT_S16_LE: 958 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 959 break; 960 case SNDRV_PCM_FORMAT_S32_LE: 961 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 962 break; 963 default: 964 dev_err(cpu_dai->dev, "Data format not supported\n"); 965 return -EINVAL; 966 } 967 968 cr1_mask |= SAI_XCR1_MONO; 969 if ((sai->slots == 2) && (params_channels(params) == 1)) 970 cr1 |= SAI_XCR1_MONO; 971 972 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 973 if (ret < 0) { 974 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 975 return ret; 976 } 977 978 return 0; 979 } 980 981 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 982 { 983 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 984 int slotr, slot_sz; 985 986 stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr); 987 988 /* 989 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 990 * By default slot width = data size, if not forced from DT 991 */ 992 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 993 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 994 sai->slot_width = sai->data_size; 995 996 if (sai->slot_width < sai->data_size) { 997 dev_err(cpu_dai->dev, 998 "Data size %d larger than slot width\n", 999 sai->data_size); 1000 return -EINVAL; 1001 } 1002 1003 /* Slot number is set to 2, if not specified in DT */ 1004 if (!sai->slots) 1005 sai->slots = 2; 1006 1007 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 1008 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 1009 SAI_XSLOTR_NBSLOT_MASK, 1010 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 1011 1012 /* Set default slots mask if not already set from DT */ 1013 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 1014 sai->slot_mask = (1 << sai->slots) - 1; 1015 stm32_sai_sub_reg_up(sai, 1016 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 1017 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 1018 } 1019 1020 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 1021 sai->slots, sai->slot_width); 1022 1023 return 0; 1024 } 1025 1026 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 1027 { 1028 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1029 int fs_active, offset, format; 1030 int frcr, frcr_mask; 1031 1032 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1033 sai->fs_length = sai->slot_width * sai->slots; 1034 1035 fs_active = sai->fs_length / 2; 1036 if ((format == SND_SOC_DAIFMT_DSP_A) || 1037 (format == SND_SOC_DAIFMT_DSP_B)) 1038 fs_active = 1; 1039 1040 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 1041 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 1042 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 1043 1044 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 1045 sai->fs_length, fs_active); 1046 1047 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 1048 1049 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 1050 offset = sai->slot_width - sai->data_size; 1051 1052 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 1053 SAI_XSLOTR_FBOFF_MASK, 1054 SAI_XSLOTR_FBOFF_SET(offset)); 1055 } 1056 } 1057 1058 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 1059 { 1060 unsigned char *cs = sai->iec958.status; 1061 1062 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 1063 cs[1] = IEC958_AES1_CON_GENERAL; 1064 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 1065 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 1066 } 1067 1068 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 1069 struct snd_pcm_runtime *runtime) 1070 { 1071 if (!runtime) 1072 return; 1073 1074 /* Force the sample rate according to runtime rate */ 1075 mutex_lock(&sai->ctrl_lock); 1076 switch (runtime->rate) { 1077 case 22050: 1078 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 1079 break; 1080 case 44100: 1081 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 1082 break; 1083 case 88200: 1084 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 1085 break; 1086 case 176400: 1087 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 1088 break; 1089 case 24000: 1090 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 1091 break; 1092 case 48000: 1093 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 1094 break; 1095 case 96000: 1096 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 1097 break; 1098 case 192000: 1099 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 1100 break; 1101 case 32000: 1102 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 1103 break; 1104 default: 1105 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 1106 break; 1107 } 1108 mutex_unlock(&sai->ctrl_lock); 1109 } 1110 1111 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 1112 struct snd_pcm_hw_params *params) 1113 { 1114 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1115 int div = 0, cr1 = 0; 1116 int sai_clk_rate, mclk_ratio, den; 1117 unsigned int rate = params_rate(params); 1118 int ret; 1119 1120 if (!sai->sai_mclk) { 1121 ret = sai->set_sai_ck_rate(sai, rate); 1122 if (ret) 1123 return ret; 1124 } 1125 sai_clk_rate = clk_get_rate(sai->sai_ck); 1126 1127 if (STM_SAI_IS_F4(sai->pdata)) { 1128 /* mclk on (NODIV=0) 1129 * mclk_rate = 256 * fs 1130 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 1131 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 1132 * mclk off (NODIV=1) 1133 * MCKDIV ignored. sck = sai_ck 1134 */ 1135 if (!sai->mclk_rate) 1136 return 0; 1137 1138 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 1139 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1140 2 * sai->mclk_rate); 1141 if (div < 0) 1142 return div; 1143 } 1144 } else { 1145 /* 1146 * TDM mode : 1147 * mclk on 1148 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 1149 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 1150 * mclk off 1151 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 1152 * Note: NOMCK/NODIV correspond to same bit. 1153 */ 1154 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1155 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1156 rate * 128); 1157 if (div < 0) 1158 return div; 1159 } else { 1160 if (sai->mclk_rate) { 1161 mclk_ratio = sai->mclk_rate / rate; 1162 if (mclk_ratio == 512) { 1163 cr1 = SAI_XCR1_OSR; 1164 } else if (mclk_ratio != 256) { 1165 dev_err(cpu_dai->dev, 1166 "Wrong mclk ratio %d\n", 1167 mclk_ratio); 1168 return -EINVAL; 1169 } 1170 1171 stm32_sai_sub_reg_up(sai, 1172 STM_SAI_CR1_REGX, 1173 SAI_XCR1_OSR, cr1); 1174 1175 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1176 sai->mclk_rate); 1177 if (div < 0) 1178 return div; 1179 } else { 1180 /* mclk-fs not set, master clock not active */ 1181 den = sai->fs_length * params_rate(params); 1182 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1183 den); 1184 if (div < 0) 1185 return div; 1186 } 1187 } 1188 } 1189 1190 return stm32_sai_set_clk_div(sai, div); 1191 } 1192 1193 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 1194 struct snd_pcm_hw_params *params, 1195 struct snd_soc_dai *cpu_dai) 1196 { 1197 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1198 int ret; 1199 1200 sai->data_size = params_width(params); 1201 1202 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1203 /* Rate not already set in runtime structure */ 1204 substream->runtime->rate = params_rate(params); 1205 stm32_sai_set_iec958_status(sai, substream->runtime); 1206 } else { 1207 ret = stm32_sai_set_slots(cpu_dai); 1208 if (ret < 0) 1209 return ret; 1210 stm32_sai_set_frame(cpu_dai); 1211 } 1212 1213 ret = stm32_sai_set_config(cpu_dai, substream, params); 1214 if (ret) 1215 return ret; 1216 1217 if (sai->master) 1218 ret = stm32_sai_configure_clock(cpu_dai, params); 1219 1220 return ret; 1221 } 1222 1223 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 1224 struct snd_soc_dai *cpu_dai) 1225 { 1226 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1227 int ret; 1228 1229 switch (cmd) { 1230 case SNDRV_PCM_TRIGGER_START: 1231 case SNDRV_PCM_TRIGGER_RESUME: 1232 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1233 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 1234 1235 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1236 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 1237 1238 /* Enable SAI */ 1239 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1240 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 1241 if (ret < 0) 1242 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1243 break; 1244 case SNDRV_PCM_TRIGGER_SUSPEND: 1245 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1246 case SNDRV_PCM_TRIGGER_STOP: 1247 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 1248 1249 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 1250 SAI_XIMR_MASK, 0); 1251 1252 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1253 SAI_XCR1_SAIEN, 1254 (unsigned int)~SAI_XCR1_SAIEN); 1255 1256 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1257 SAI_XCR1_DMAEN, 1258 (unsigned int)~SAI_XCR1_DMAEN); 1259 if (ret < 0) 1260 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1261 1262 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1263 sai->spdif_frm_cnt = 0; 1264 break; 1265 default: 1266 return -EINVAL; 1267 } 1268 1269 return ret; 1270 } 1271 1272 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 1273 struct snd_soc_dai *cpu_dai) 1274 { 1275 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1276 unsigned long flags; 1277 1278 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 1279 1280 clk_disable_unprepare(sai->sai_ck); 1281 1282 /* 1283 * Release kernel clock if following conditions are fulfilled 1284 * - Master clock is not used. Kernel clock won't be released trough sysclk 1285 * - Put handler is defined. Involve that clock is managed exclusively 1286 */ 1287 if (!sai->sai_mclk && sai->put_sai_ck_rate) 1288 sai->put_sai_ck_rate(sai); 1289 1290 spin_lock_irqsave(&sai->irq_lock, flags); 1291 sai->substream = NULL; 1292 spin_unlock_irqrestore(&sai->irq_lock, flags); 1293 } 1294 1295 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1296 struct snd_soc_dai *cpu_dai) 1297 { 1298 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1299 struct snd_kcontrol_new knew = iec958_ctls; 1300 1301 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1302 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 1303 knew.device = rtd->pcm->device; 1304 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1305 } 1306 1307 return 0; 1308 } 1309 1310 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 1311 { 1312 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1313 int cr1 = 0, cr1_mask, ret; 1314 1315 sai->cpu_dai = cpu_dai; 1316 1317 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1318 /* 1319 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1320 * as it allows bytes, half-word and words transfers. (See DMA fifos 1321 * constraints). 1322 */ 1323 sai->dma_params.maxburst = 4; 1324 if (sai->pdata->conf.fifo_size < 8 || sai->pdata->conf.no_dma_burst) 1325 sai->dma_params.maxburst = 1; 1326 /* Buswidth will be set by framework at runtime */ 1327 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1328 1329 if (STM_SAI_IS_PLAYBACK(sai)) 1330 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 1331 else 1332 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 1333 1334 /* Next settings are not relevant for spdif mode */ 1335 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1336 return 0; 1337 1338 cr1_mask = SAI_XCR1_RX_TX; 1339 if (STM_SAI_IS_CAPTURE(sai)) 1340 cr1 |= SAI_XCR1_RX_TX; 1341 1342 /* Configure synchronization */ 1343 if (sai->sync == SAI_SYNC_EXTERNAL) { 1344 /* Configure synchro client and provider */ 1345 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 1346 sai->synco, sai->synci); 1347 if (ret) 1348 return ret; 1349 } 1350 1351 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 1352 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 1353 1354 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 1355 } 1356 1357 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 1358 .probe = stm32_sai_dai_probe, 1359 .set_sysclk = stm32_sai_set_sysclk, 1360 .set_fmt = stm32_sai_set_dai_fmt, 1361 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1362 .startup = stm32_sai_startup, 1363 .hw_params = stm32_sai_hw_params, 1364 .trigger = stm32_sai_trigger, 1365 .shutdown = stm32_sai_shutdown, 1366 .pcm_new = stm32_sai_pcm_new, 1367 }; 1368 1369 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops2 = { 1370 .probe = stm32_sai_dai_probe, 1371 .set_sysclk = stm32_sai_set_sysclk, 1372 .set_fmt = stm32_sai_set_dai_fmt, 1373 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1374 .startup = stm32_sai_startup, 1375 .hw_params = stm32_sai_hw_params, 1376 .trigger = stm32_sai_trigger, 1377 .shutdown = stm32_sai_shutdown, 1378 }; 1379 1380 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 1381 int channel, unsigned long hwoff, 1382 unsigned long bytes) 1383 { 1384 struct snd_pcm_runtime *runtime = substream->runtime; 1385 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1386 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 1387 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1388 int *ptr = (int *)(runtime->dma_area + hwoff + 1389 channel * (runtime->dma_bytes / runtime->channels)); 1390 ssize_t cnt = bytes_to_samples(runtime, bytes); 1391 unsigned int frm_cnt = sai->spdif_frm_cnt; 1392 unsigned int byte; 1393 unsigned int mask; 1394 1395 do { 1396 *ptr = ((*ptr >> 8) & 0x00ffffff); 1397 1398 /* Set channel status bit */ 1399 byte = frm_cnt >> 3; 1400 mask = 1 << (frm_cnt - (byte << 3)); 1401 if (sai->iec958.status[byte] & mask) 1402 *ptr |= 0x04000000; 1403 ptr++; 1404 1405 if (!(cnt % 2)) 1406 frm_cnt++; 1407 1408 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 1409 frm_cnt = 0; 1410 } while (--cnt); 1411 sai->spdif_frm_cnt = frm_cnt; 1412 1413 return 0; 1414 } 1415 1416 /* No support of mmap in S/PDIF mode */ 1417 static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = { 1418 .info = SNDRV_PCM_INFO_INTERLEAVED, 1419 .buffer_bytes_max = 8 * PAGE_SIZE, 1420 .period_bytes_min = 1024, 1421 .period_bytes_max = PAGE_SIZE, 1422 .periods_min = 2, 1423 .periods_max = 8, 1424 }; 1425 1426 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 1427 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 1428 .buffer_bytes_max = 8 * PAGE_SIZE, 1429 .period_bytes_min = 1024, /* 5ms at 48kHz */ 1430 .period_bytes_max = PAGE_SIZE, 1431 .periods_min = 2, 1432 .periods_max = 8, 1433 }; 1434 1435 static struct snd_soc_dai_driver stm32_sai_playback_dai = { 1436 .id = 1, /* avoid call to fmt_single_name() */ 1437 .playback = { 1438 .channels_min = 1, 1439 .channels_max = 16, 1440 .rate_min = 8000, 1441 .rate_max = 192000, 1442 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1443 /* DMA does not support 24 bits transfers */ 1444 .formats = 1445 SNDRV_PCM_FMTBIT_S8 | 1446 SNDRV_PCM_FMTBIT_S16_LE | 1447 SNDRV_PCM_FMTBIT_S32_LE, 1448 }, 1449 .ops = &stm32_sai_pcm_dai_ops, 1450 }; 1451 1452 static struct snd_soc_dai_driver stm32_sai_capture_dai = { 1453 .id = 1, /* avoid call to fmt_single_name() */ 1454 .capture = { 1455 .channels_min = 1, 1456 .channels_max = 16, 1457 .rate_min = 8000, 1458 .rate_max = 192000, 1459 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1460 /* DMA does not support 24 bits transfers */ 1461 .formats = 1462 SNDRV_PCM_FMTBIT_S8 | 1463 SNDRV_PCM_FMTBIT_S16_LE | 1464 SNDRV_PCM_FMTBIT_S32_LE, 1465 }, 1466 .ops = &stm32_sai_pcm_dai_ops2, 1467 }; 1468 1469 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 1470 .pcm_hardware = &stm32_sai_pcm_hw, 1471 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1472 }; 1473 1474 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 1475 .pcm_hardware = &stm32_sai_pcm_hw_spdif, 1476 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1477 .process = stm32_sai_pcm_process_spdif, 1478 }; 1479 1480 static const struct snd_soc_component_driver stm32_component = { 1481 .name = "stm32-sai", 1482 .legacy_dai_naming = 1, 1483 }; 1484 1485 static const struct of_device_id stm32_sai_sub_ids[] = { 1486 { .compatible = "st,stm32-sai-sub-a", 1487 .data = (void *)STM_SAI_A_ID}, 1488 { .compatible = "st,stm32-sai-sub-b", 1489 .data = (void *)STM_SAI_B_ID}, 1490 {} 1491 }; 1492 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 1493 1494 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 1495 struct stm32_sai_sub_data *sai) 1496 { 1497 struct device_node *np = pdev->dev.of_node; 1498 struct resource *res; 1499 void __iomem *base; 1500 struct of_phandle_args args; 1501 int ret; 1502 1503 if (!np) 1504 return -ENODEV; 1505 1506 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1507 if (IS_ERR(base)) 1508 return PTR_ERR(base); 1509 1510 sai->phys_addr = res->start; 1511 1512 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 1513 /* Note: PDM registers not available for sub-block B */ 1514 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai)) 1515 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 1516 1517 /* 1518 * Do not manage peripheral clock through regmap framework as this 1519 * can lead to circular locking issue with sai master clock provider. 1520 * Manage peripheral clock directly in driver instead. 1521 */ 1522 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1523 sai->regmap_config); 1524 if (IS_ERR(sai->regmap)) 1525 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap), 1526 "Regmap init error\n"); 1527 1528 /* Get direction property */ 1529 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 1530 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 1531 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 1532 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 1533 } else { 1534 dev_err(&pdev->dev, "Unsupported direction\n"); 1535 return -EINVAL; 1536 } 1537 1538 /* Get spdif iec60958 property */ 1539 sai->spdif = false; 1540 if (of_property_present(np, "st,iec60958")) { 1541 if (!STM_SAI_HAS_SPDIF(sai) || 1542 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 1543 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 1544 return -EINVAL; 1545 } 1546 stm32_sai_init_iec958_status(sai); 1547 sai->spdif = true; 1548 sai->master = true; 1549 } 1550 1551 /* Get synchronization property */ 1552 args.np = NULL; 1553 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1554 if (ret < 0 && ret != -ENOENT) { 1555 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1556 return ret; 1557 } 1558 1559 sai->sync = SAI_SYNC_NONE; 1560 if (args.np) { 1561 if (args.np == np) { 1562 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 1563 of_node_put(args.np); 1564 return -EINVAL; 1565 } 1566 1567 sai->np_sync_provider = of_get_parent(args.np); 1568 if (!sai->np_sync_provider) { 1569 dev_err(&pdev->dev, "%pOFn parent node not found\n", 1570 np); 1571 of_node_put(args.np); 1572 return -ENODEV; 1573 } 1574 1575 sai->sync = SAI_SYNC_INTERNAL; 1576 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1577 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1578 dev_err(&pdev->dev, 1579 "External synchro not supported\n"); 1580 of_node_put(args.np); 1581 return -EINVAL; 1582 } 1583 sai->sync = SAI_SYNC_EXTERNAL; 1584 1585 sai->synci = args.args[0]; 1586 if (sai->synci < 1 || 1587 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1588 dev_err(&pdev->dev, "Wrong SAI index\n"); 1589 of_node_put(args.np); 1590 return -EINVAL; 1591 } 1592 1593 if (of_property_match_string(args.np, "compatible", 1594 "st,stm32-sai-sub-a") >= 0) 1595 sai->synco = STM_SAI_SYNC_OUT_A; 1596 1597 if (of_property_match_string(args.np, "compatible", 1598 "st,stm32-sai-sub-b") >= 0) 1599 sai->synco = STM_SAI_SYNC_OUT_B; 1600 1601 if (!sai->synco) { 1602 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1603 of_node_put(args.np); 1604 return -EINVAL; 1605 } 1606 } 1607 1608 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1609 pdev->name, args.np->full_name); 1610 } 1611 1612 of_node_put(args.np); 1613 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1614 if (IS_ERR(sai->sai_ck)) 1615 return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck), 1616 "Missing kernel clock sai_ck\n"); 1617 1618 ret = clk_prepare(sai->pdata->pclk); 1619 if (ret < 0) 1620 return ret; 1621 1622 if (STM_SAI_IS_F4(sai->pdata)) 1623 return 0; 1624 1625 /* Register mclk provider if requested */ 1626 if (of_property_present(np, "#clock-cells")) { 1627 ret = stm32_sai_add_mclk_provider(sai); 1628 if (ret < 0) 1629 return ret; 1630 } else { 1631 sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK"); 1632 if (IS_ERR(sai->sai_mclk)) 1633 return PTR_ERR(sai->sai_mclk); 1634 } 1635 1636 return 0; 1637 } 1638 1639 static int stm32_sai_sub_probe(struct platform_device *pdev) 1640 { 1641 struct stm32_sai_sub_data *sai; 1642 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1643 int ret; 1644 1645 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1646 if (!sai) 1647 return -ENOMEM; 1648 1649 sai->id = (uintptr_t)device_get_match_data(&pdev->dev); 1650 1651 sai->pdev = pdev; 1652 mutex_init(&sai->ctrl_lock); 1653 spin_lock_init(&sai->irq_lock); 1654 platform_set_drvdata(pdev, sai); 1655 1656 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1657 if (!sai->pdata) { 1658 dev_err(&pdev->dev, "Parent device data not available\n"); 1659 return -EINVAL; 1660 } 1661 1662 if (sai->pdata->conf.get_sai_ck_parent) { 1663 sai->set_sai_ck_rate = stm32_sai_set_parent_clk; 1664 } else { 1665 sai->set_sai_ck_rate = stm32_sai_set_parent_rate; 1666 sai->put_sai_ck_rate = stm32_sai_put_parent_rate; 1667 } 1668 1669 ret = stm32_sai_sub_parse_of(pdev, sai); 1670 if (ret) 1671 return ret; 1672 1673 if (STM_SAI_IS_PLAYBACK(sai)) 1674 sai->cpu_dai_drv = stm32_sai_playback_dai; 1675 else 1676 sai->cpu_dai_drv = stm32_sai_capture_dai; 1677 sai->cpu_dai_drv.name = dev_name(&pdev->dev); 1678 1679 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1680 IRQF_SHARED, dev_name(&pdev->dev), sai); 1681 if (ret) { 1682 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1683 return ret; 1684 } 1685 1686 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1687 conf = &stm32_sai_pcm_config_spdif; 1688 1689 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1690 if (ret) 1691 return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n"); 1692 1693 ret = snd_soc_register_component(&pdev->dev, &stm32_component, 1694 &sai->cpu_dai_drv, 1); 1695 if (ret) { 1696 snd_dmaengine_pcm_unregister(&pdev->dev); 1697 return ret; 1698 } 1699 1700 pm_runtime_enable(&pdev->dev); 1701 1702 return 0; 1703 } 1704 1705 static void stm32_sai_sub_remove(struct platform_device *pdev) 1706 { 1707 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev); 1708 1709 clk_unprepare(sai->pdata->pclk); 1710 snd_dmaengine_pcm_unregister(&pdev->dev); 1711 snd_soc_unregister_component(&pdev->dev); 1712 pm_runtime_disable(&pdev->dev); 1713 } 1714 1715 static int stm32_sai_sub_suspend(struct device *dev) 1716 { 1717 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1718 int ret; 1719 1720 ret = clk_enable(sai->pdata->pclk); 1721 if (ret < 0) 1722 return ret; 1723 1724 regcache_cache_only(sai->regmap, true); 1725 regcache_mark_dirty(sai->regmap); 1726 1727 clk_disable(sai->pdata->pclk); 1728 1729 return 0; 1730 } 1731 1732 static int stm32_sai_sub_resume(struct device *dev) 1733 { 1734 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1735 int ret; 1736 1737 ret = clk_enable(sai->pdata->pclk); 1738 if (ret < 0) 1739 return ret; 1740 1741 regcache_cache_only(sai->regmap, false); 1742 ret = regcache_sync(sai->regmap); 1743 1744 clk_disable(sai->pdata->pclk); 1745 1746 return ret; 1747 } 1748 1749 static const struct dev_pm_ops stm32_sai_sub_pm_ops = { 1750 SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume) 1751 }; 1752 1753 static struct platform_driver stm32_sai_sub_driver = { 1754 .driver = { 1755 .name = "st,stm32-sai-sub", 1756 .of_match_table = stm32_sai_sub_ids, 1757 .pm = pm_ptr(&stm32_sai_sub_pm_ops), 1758 }, 1759 .probe = stm32_sai_sub_probe, 1760 .remove = stm32_sai_sub_remove, 1761 }; 1762 1763 module_platform_driver(stm32_sai_sub_driver); 1764 1765 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1766 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1767 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1768 MODULE_LICENSE("GPL v2"); 1769