1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 18 #include <sound/asoundef.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 23 #include "stm32_sai.h" 24 25 #define SAI_FREE_PROTOCOL 0x0 26 #define SAI_SPDIF_PROTOCOL 0x1 27 28 #define SAI_SLOT_SIZE_AUTO 0x0 29 #define SAI_SLOT_SIZE_16 0x1 30 #define SAI_SLOT_SIZE_32 0x2 31 32 #define SAI_DATASIZE_8 0x2 33 #define SAI_DATASIZE_10 0x3 34 #define SAI_DATASIZE_16 0x4 35 #define SAI_DATASIZE_20 0x5 36 #define SAI_DATASIZE_24 0x6 37 #define SAI_DATASIZE_32 0x7 38 39 #define STM_SAI_DAI_NAME_SIZE 15 40 41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 43 44 #define STM_SAI_A_ID 0x0 45 #define STM_SAI_B_ID 0x1 46 47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 48 49 #define SAI_SYNC_NONE 0x0 50 #define SAI_SYNC_INTERNAL 0x1 51 #define SAI_SYNC_EXTERNAL 0x2 52 53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm) 55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm) 56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4((x)->pdata)) 57 58 #define SAI_IEC60958_BLOCK_FRAMES 192 59 #define SAI_IEC60958_STATUS_BYTES 24 60 61 #define SAI_MCLK_NAME_LEN 32 62 #define SAI_RATE_11K 11025 63 #define SAI_MAX_SAMPLE_RATE_8K 192000 64 #define SAI_MAX_SAMPLE_RATE_11K 176400 65 #define SAI_CK_RATE_TOLERANCE 1000 /* ppm */ 66 67 /** 68 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 69 * @pdev: device data pointer 70 * @regmap: SAI register map pointer 71 * @regmap_config: SAI sub block register map configuration pointer 72 * @dma_params: dma configuration data for rx or tx channel 73 * @cpu_dai_drv: DAI driver data pointer 74 * @cpu_dai: DAI runtime data pointer 75 * @substream: PCM substream data pointer 76 * @pdata: SAI block parent data pointer 77 * @np_sync_provider: synchronization provider node 78 * @sai_ck: kernel clock feeding the SAI clock generator 79 * @sai_mclk: master clock from SAI mclk provider 80 * @phys_addr: SAI registers physical base address 81 * @mclk_rate: SAI block master clock frequency (Hz). set at init 82 * @id: SAI sub block id corresponding to sub-block A or B 83 * @dir: SAI block direction (playback or capture). set at init 84 * @master: SAI block mode flag. (true=master, false=slave) set at init 85 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 86 * @sai_ck_used: flag set while exclusivity on SAI kernel clock is active 87 * @fmt: SAI block format. relevant only for custom protocols. set at init 88 * @sync: SAI block synchronization mode. (none, internal or external) 89 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 90 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 91 * @fs_length: frame synchronization length. depends on protocol settings 92 * @slots: rx or tx slot number 93 * @slot_width: rx or tx slot width in bits 94 * @slot_mask: rx or tx active slots mask. set at init or at runtime 95 * @data_size: PCM data width. corresponds to PCM substream width. 96 * @spdif_frm_cnt: S/PDIF playback frame counter 97 * @iec958: iec958 data 98 * @ctrl_lock: control lock 99 * @irq_lock: prevent race condition with IRQ 100 * @set_sai_ck_rate: set SAI kernel clock rate 101 * @put_sai_ck_rate: put SAI kernel clock rate 102 */ 103 struct stm32_sai_sub_data { 104 struct platform_device *pdev; 105 struct regmap *regmap; 106 const struct regmap_config *regmap_config; 107 struct snd_dmaengine_dai_dma_data dma_params; 108 struct snd_soc_dai_driver cpu_dai_drv; 109 struct snd_soc_dai *cpu_dai; 110 struct snd_pcm_substream *substream; 111 struct stm32_sai_data *pdata; 112 struct device_node *np_sync_provider; 113 struct clk *sai_ck; 114 struct clk *sai_mclk; 115 dma_addr_t phys_addr; 116 unsigned int mclk_rate; 117 unsigned int id; 118 int dir; 119 bool master; 120 bool spdif; 121 bool sai_ck_used; 122 int fmt; 123 int sync; 124 int synco; 125 int synci; 126 int fs_length; 127 int slots; 128 int slot_width; 129 int slot_mask; 130 int data_size; 131 unsigned int spdif_frm_cnt; 132 struct snd_aes_iec958 iec958; 133 struct mutex ctrl_lock; /* protect resources accessed by controls */ 134 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 135 int (*set_sai_ck_rate)(struct stm32_sai_sub_data *sai, unsigned int rate); 136 void (*put_sai_ck_rate)(struct stm32_sai_sub_data *sai); 137 }; 138 139 enum stm32_sai_fifo_th { 140 STM_SAI_FIFO_TH_EMPTY, 141 STM_SAI_FIFO_TH_QUARTER, 142 STM_SAI_FIFO_TH_HALF, 143 STM_SAI_FIFO_TH_3_QUARTER, 144 STM_SAI_FIFO_TH_FULL, 145 }; 146 147 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 148 { 149 switch (reg) { 150 case STM_SAI_CR1_REGX: 151 case STM_SAI_CR2_REGX: 152 case STM_SAI_FRCR_REGX: 153 case STM_SAI_SLOTR_REGX: 154 case STM_SAI_IMR_REGX: 155 case STM_SAI_SR_REGX: 156 case STM_SAI_CLRFR_REGX: 157 case STM_SAI_DR_REGX: 158 case STM_SAI_PDMCR_REGX: 159 case STM_SAI_PDMLY_REGX: 160 return true; 161 default: 162 return false; 163 } 164 } 165 166 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 167 { 168 switch (reg) { 169 case STM_SAI_DR_REGX: 170 case STM_SAI_SR_REGX: 171 return true; 172 default: 173 return false; 174 } 175 } 176 177 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 178 { 179 switch (reg) { 180 case STM_SAI_CR1_REGX: 181 case STM_SAI_CR2_REGX: 182 case STM_SAI_FRCR_REGX: 183 case STM_SAI_SLOTR_REGX: 184 case STM_SAI_IMR_REGX: 185 case STM_SAI_CLRFR_REGX: 186 case STM_SAI_DR_REGX: 187 case STM_SAI_PDMCR_REGX: 188 case STM_SAI_PDMLY_REGX: 189 return true; 190 default: 191 return false; 192 } 193 } 194 195 static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai, 196 unsigned int reg, unsigned int mask, 197 unsigned int val) 198 { 199 int ret; 200 201 ret = clk_enable(sai->pdata->pclk); 202 if (ret < 0) 203 return ret; 204 205 ret = regmap_update_bits(sai->regmap, reg, mask, val); 206 207 clk_disable(sai->pdata->pclk); 208 209 return ret; 210 } 211 212 static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai, 213 unsigned int reg, unsigned int mask, 214 unsigned int val) 215 { 216 int ret; 217 218 ret = clk_enable(sai->pdata->pclk); 219 if (ret < 0) 220 return ret; 221 222 ret = regmap_write_bits(sai->regmap, reg, mask, val); 223 224 clk_disable(sai->pdata->pclk); 225 226 return ret; 227 } 228 229 static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai, 230 unsigned int reg, unsigned int *val) 231 { 232 int ret; 233 234 ret = clk_enable(sai->pdata->pclk); 235 if (ret < 0) 236 return ret; 237 238 ret = regmap_read(sai->regmap, reg, val); 239 240 clk_disable(sai->pdata->pclk); 241 242 return ret; 243 } 244 245 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 246 .reg_bits = 32, 247 .reg_stride = 4, 248 .val_bits = 32, 249 .max_register = STM_SAI_DR_REGX, 250 .readable_reg = stm32_sai_sub_readable_reg, 251 .volatile_reg = stm32_sai_sub_volatile_reg, 252 .writeable_reg = stm32_sai_sub_writeable_reg, 253 .fast_io = true, 254 .cache_type = REGCACHE_FLAT, 255 }; 256 257 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 258 .reg_bits = 32, 259 .reg_stride = 4, 260 .val_bits = 32, 261 .max_register = STM_SAI_PDMLY_REGX, 262 .readable_reg = stm32_sai_sub_readable_reg, 263 .volatile_reg = stm32_sai_sub_volatile_reg, 264 .writeable_reg = stm32_sai_sub_writeable_reg, 265 .fast_io = true, 266 .cache_type = REGCACHE_FLAT, 267 }; 268 269 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 270 struct snd_ctl_elem_info *uinfo) 271 { 272 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 273 uinfo->count = 1; 274 275 return 0; 276 } 277 278 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 279 struct snd_ctl_elem_value *uctl) 280 { 281 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 282 283 mutex_lock(&sai->ctrl_lock); 284 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 285 mutex_unlock(&sai->ctrl_lock); 286 287 return 0; 288 } 289 290 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 291 struct snd_ctl_elem_value *uctl) 292 { 293 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 294 295 mutex_lock(&sai->ctrl_lock); 296 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 297 mutex_unlock(&sai->ctrl_lock); 298 299 return 0; 300 } 301 302 static const struct snd_kcontrol_new iec958_ctls = { 303 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 304 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 305 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 306 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 307 .info = snd_pcm_iec958_info, 308 .get = snd_pcm_iec958_get, 309 .put = snd_pcm_iec958_put, 310 }; 311 312 struct stm32_sai_mclk_data { 313 struct clk_hw hw; 314 unsigned long freq; 315 struct stm32_sai_sub_data *sai_data; 316 }; 317 318 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 319 #define STM32_SAI_MAX_CLKS 1 320 321 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 322 unsigned long input_rate, 323 unsigned long output_rate) 324 { 325 int version = sai->pdata->conf.version; 326 int div; 327 328 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 329 if (div > SAI_XCR1_MCKDIV_MAX(version) || div <= 0) { 330 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 331 return -EINVAL; 332 } 333 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 334 335 if (input_rate % div) 336 dev_dbg(&sai->pdev->dev, 337 "Rate not accurate. requested (%ld), actual (%ld)\n", 338 output_rate, input_rate / div); 339 340 return div; 341 } 342 343 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 344 unsigned int div) 345 { 346 int version = sai->pdata->conf.version; 347 int ret, cr1, mask; 348 349 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 350 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 351 return -EINVAL; 352 } 353 354 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 355 cr1 = SAI_XCR1_MCKDIV_SET(div); 356 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1); 357 if (ret < 0) 358 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 359 360 return ret; 361 } 362 363 static bool stm32_sai_rate_accurate(unsigned int max_rate, unsigned int rate) 364 { 365 u64 delta, dividend; 366 int ratio; 367 368 ratio = DIV_ROUND_CLOSEST(max_rate, rate); 369 if (!ratio) 370 return false; 371 372 dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate))); 373 delta = div_u64(dividend, max_rate); 374 375 if (delta <= SAI_CK_RATE_TOLERANCE) 376 return true; 377 378 return false; 379 } 380 381 static int stm32_sai_set_parent_clk(struct stm32_sai_sub_data *sai, 382 unsigned int rate) 383 { 384 struct platform_device *pdev = sai->pdev; 385 struct clk *parent_clk = sai->pdata->clk_x8k; 386 int ret; 387 388 if (!(rate % SAI_RATE_11K)) 389 parent_clk = sai->pdata->clk_x11k; 390 391 ret = clk_set_parent(sai->sai_ck, parent_clk); 392 if (ret) 393 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", 394 ret, ret == -EBUSY ? 395 "Active stream rates conflict\n" : "\n"); 396 397 return ret; 398 } 399 400 static void stm32_sai_put_parent_rate(struct stm32_sai_sub_data *sai) 401 { 402 if (sai->sai_ck_used) { 403 sai->sai_ck_used = false; 404 clk_rate_exclusive_put(sai->sai_ck); 405 } 406 } 407 408 static int stm32_sai_set_parent_rate(struct stm32_sai_sub_data *sai, 409 unsigned int rate) 410 { 411 struct platform_device *pdev = sai->pdev; 412 unsigned int sai_ck_rate, sai_ck_max_rate, sai_ck_min_rate, sai_curr_rate, sai_new_rate; 413 int div, ret; 414 415 /* 416 * Set minimum and maximum expected kernel clock frequency 417 * - mclk on or spdif: 418 * f_sai_ck = MCKDIV * mclk-fs * fs 419 * Here typical 256 ratio is assumed for mclk-fs 420 * - mclk off: 421 * f_sai_ck = MCKDIV * FRL * fs 422 * Where FRL=[8..256], MCKDIV=[1..n] (n depends on SAI version) 423 * Set constraint MCKDIV * FRL <= 256, to ensure MCKDIV is in available range 424 * f_sai_ck = sai_ck_max_rate * pow_of_two(FRL) / 256 425 */ 426 sai_ck_min_rate = rate * 256; 427 if (!(rate % SAI_RATE_11K)) 428 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_11K * 256; 429 else 430 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_8K * 256; 431 432 if (!sai->sai_mclk && !STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 433 sai_ck_min_rate = rate * sai->fs_length; 434 sai_ck_max_rate /= DIV_ROUND_CLOSEST(256, roundup_pow_of_two(sai->fs_length)); 435 } 436 437 /* 438 * Request exclusivity, as the clock is shared by SAI sub-blocks and by 439 * some SAI instances. This allows to ensure that the rate cannot be 440 * changed while one or more SAIs are using the clock. 441 */ 442 clk_rate_exclusive_get(sai->sai_ck); 443 sai->sai_ck_used = true; 444 445 /* 446 * Check current kernel clock rate. If it gives the expected accuracy 447 * return immediately. 448 */ 449 sai_curr_rate = clk_get_rate(sai->sai_ck); 450 dev_dbg(&pdev->dev, "kernel clock rate: min [%u], max [%u], current [%u]", 451 sai_ck_min_rate, sai_ck_max_rate, sai_curr_rate); 452 if (stm32_sai_rate_accurate(sai_ck_max_rate, sai_curr_rate) && 453 sai_curr_rate >= sai_ck_min_rate) 454 return 0; 455 456 /* 457 * Otherwise try to set the maximum rate and check the new actual rate. 458 * If the new rate does not give the expected accuracy, try to set 459 * lower rates for the kernel clock. 460 */ 461 sai_ck_rate = sai_ck_max_rate; 462 div = 1; 463 do { 464 /* Check new rate accuracy. Return if ok */ 465 sai_new_rate = clk_round_rate(sai->sai_ck, sai_ck_rate); 466 if (stm32_sai_rate_accurate(sai_ck_rate, sai_new_rate)) { 467 ret = clk_set_rate(sai->sai_ck, sai_ck_rate); 468 if (ret) { 469 dev_err(&pdev->dev, "Error %d setting sai_ck rate. %s", 470 ret, ret == -EBUSY ? 471 "Active stream rates may be in conflict\n" : "\n"); 472 goto err; 473 } 474 475 return 0; 476 } 477 478 /* Try a lower frequency */ 479 div++; 480 sai_ck_rate = sai_ck_max_rate / div; 481 } while (sai_ck_rate >= sai_ck_min_rate); 482 483 /* No accurate rate found */ 484 dev_err(&pdev->dev, "Failed to find an accurate rate"); 485 486 err: 487 stm32_sai_put_parent_rate(sai); 488 489 return -EINVAL; 490 } 491 492 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 493 unsigned long *prate) 494 { 495 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 496 struct stm32_sai_sub_data *sai = mclk->sai_data; 497 int div; 498 499 div = stm32_sai_get_clk_div(sai, *prate, rate); 500 if (div <= 0) 501 return -EINVAL; 502 503 mclk->freq = *prate / div; 504 505 return mclk->freq; 506 } 507 508 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 509 unsigned long parent_rate) 510 { 511 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 512 513 return mclk->freq; 514 } 515 516 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 517 unsigned long parent_rate) 518 { 519 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 520 struct stm32_sai_sub_data *sai = mclk->sai_data; 521 int div, ret; 522 523 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 524 if (div < 0) 525 return div; 526 527 ret = stm32_sai_set_clk_div(sai, div); 528 if (ret) 529 return ret; 530 531 mclk->freq = rate; 532 533 return 0; 534 } 535 536 static int stm32_sai_mclk_enable(struct clk_hw *hw) 537 { 538 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 539 struct stm32_sai_sub_data *sai = mclk->sai_data; 540 541 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 542 543 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 544 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 545 } 546 547 static void stm32_sai_mclk_disable(struct clk_hw *hw) 548 { 549 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 550 struct stm32_sai_sub_data *sai = mclk->sai_data; 551 552 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 553 554 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 555 } 556 557 static const struct clk_ops mclk_ops = { 558 .enable = stm32_sai_mclk_enable, 559 .disable = stm32_sai_mclk_disable, 560 .recalc_rate = stm32_sai_mclk_recalc_rate, 561 .round_rate = stm32_sai_mclk_round_rate, 562 .set_rate = stm32_sai_mclk_set_rate, 563 }; 564 565 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 566 { 567 struct clk_hw *hw; 568 struct stm32_sai_mclk_data *mclk; 569 struct device *dev = &sai->pdev->dev; 570 const char *pname = __clk_get_name(sai->sai_ck); 571 char *mclk_name, *p, *s = (char *)pname; 572 int ret, i = 0; 573 574 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 575 if (!mclk) 576 return -ENOMEM; 577 578 mclk_name = devm_kcalloc(dev, sizeof(char), 579 SAI_MCLK_NAME_LEN, GFP_KERNEL); 580 if (!mclk_name) 581 return -ENOMEM; 582 583 /* 584 * Forge mclk clock name from parent clock name and suffix. 585 * String after "_" char is stripped in parent name. 586 */ 587 p = mclk_name; 588 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 589 *p++ = *s++; 590 i++; 591 } 592 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 593 594 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 595 mclk->sai_data = sai; 596 hw = &mclk->hw; 597 598 dev_dbg(dev, "Register master clock %s\n", mclk_name); 599 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 600 if (ret) { 601 dev_err(dev, "mclk register returned %d\n", ret); 602 return ret; 603 } 604 sai->sai_mclk = hw->clk; 605 606 /* register mclk provider */ 607 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 608 } 609 610 static irqreturn_t stm32_sai_isr(int irq, void *devid) 611 { 612 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 613 struct platform_device *pdev = sai->pdev; 614 unsigned int sr, imr, flags; 615 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 616 617 stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr); 618 stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr); 619 620 flags = sr & imr; 621 if (!flags) 622 return IRQ_NONE; 623 624 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 625 SAI_XCLRFR_MASK); 626 627 if (!sai->substream) { 628 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 629 return IRQ_NONE; 630 } 631 632 if (flags & SAI_XIMR_OVRUDRIE) { 633 dev_err(&pdev->dev, "IRQ %s\n", 634 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 635 status = SNDRV_PCM_STATE_XRUN; 636 } 637 638 if (flags & SAI_XIMR_MUTEDETIE) 639 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 640 641 if (flags & SAI_XIMR_WCKCFGIE) { 642 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 643 status = SNDRV_PCM_STATE_DISCONNECTED; 644 } 645 646 if (flags & SAI_XIMR_CNRDYIE) 647 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 648 649 if (flags & SAI_XIMR_AFSDETIE) { 650 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 651 status = SNDRV_PCM_STATE_XRUN; 652 } 653 654 if (flags & SAI_XIMR_LFSDETIE) { 655 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 656 status = SNDRV_PCM_STATE_XRUN; 657 } 658 659 spin_lock(&sai->irq_lock); 660 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) 661 snd_pcm_stop_xrun(sai->substream); 662 spin_unlock(&sai->irq_lock); 663 664 return IRQ_HANDLED; 665 } 666 667 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 668 int clk_id, unsigned int freq, int dir) 669 { 670 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 671 int ret; 672 673 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { 674 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 675 SAI_XCR1_NODIV, 676 freq ? 0 : SAI_XCR1_NODIV); 677 if (ret < 0) 678 return ret; 679 680 /* Assume shutdown if requested frequency is 0Hz */ 681 if (!freq) { 682 /* Release mclk rate only if rate was actually set */ 683 if (sai->mclk_rate) { 684 clk_rate_exclusive_put(sai->sai_mclk); 685 sai->mclk_rate = 0; 686 } 687 688 if (sai->put_sai_ck_rate) 689 sai->put_sai_ck_rate(sai); 690 691 return 0; 692 } 693 694 /* If master clock is used, configure SAI kernel clock now */ 695 ret = sai->set_sai_ck_rate(sai, freq); 696 if (ret) 697 return ret; 698 699 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); 700 if (ret) { 701 dev_err(cpu_dai->dev, 702 ret == -EBUSY ? 703 "Active streams have incompatible rates" : 704 "Could not set mclk rate\n"); 705 return ret; 706 } 707 708 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 709 sai->mclk_rate = freq; 710 } 711 712 return 0; 713 } 714 715 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 716 u32 rx_mask, int slots, int slot_width) 717 { 718 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 719 int slotr, slotr_mask, slot_size; 720 721 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 722 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 723 return 0; 724 } 725 726 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 727 tx_mask, rx_mask, slots, slot_width); 728 729 switch (slot_width) { 730 case 16: 731 slot_size = SAI_SLOT_SIZE_16; 732 break; 733 case 32: 734 slot_size = SAI_SLOT_SIZE_32; 735 break; 736 default: 737 slot_size = SAI_SLOT_SIZE_AUTO; 738 break; 739 } 740 741 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 742 SAI_XSLOTR_NBSLOT_SET(slots - 1); 743 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 744 745 /* tx/rx mask set in machine init, if slot number defined in DT */ 746 if (STM_SAI_IS_PLAYBACK(sai)) { 747 sai->slot_mask = tx_mask; 748 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 749 } 750 751 if (STM_SAI_IS_CAPTURE(sai)) { 752 sai->slot_mask = rx_mask; 753 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 754 } 755 756 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 757 758 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 759 760 sai->slot_width = slot_width; 761 sai->slots = slots; 762 763 return 0; 764 } 765 766 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 767 { 768 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 769 int cr1, frcr = 0; 770 int cr1_mask, frcr_mask = 0; 771 int ret; 772 773 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 774 775 /* Do not generate master by default */ 776 cr1 = SAI_XCR1_NODIV; 777 cr1_mask = SAI_XCR1_NODIV; 778 779 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 780 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 781 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 782 goto conf_update; 783 } 784 785 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 786 787 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 788 /* SCK active high for all protocols */ 789 case SND_SOC_DAIFMT_I2S: 790 cr1 |= SAI_XCR1_CKSTR; 791 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 792 break; 793 /* Left justified */ 794 case SND_SOC_DAIFMT_MSB: 795 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 796 break; 797 /* Right justified */ 798 case SND_SOC_DAIFMT_LSB: 799 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 800 break; 801 case SND_SOC_DAIFMT_DSP_A: 802 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 803 break; 804 case SND_SOC_DAIFMT_DSP_B: 805 frcr |= SAI_XFRCR_FSPOL; 806 break; 807 default: 808 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 809 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 810 return -EINVAL; 811 } 812 813 cr1_mask |= SAI_XCR1_CKSTR; 814 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 815 SAI_XFRCR_FSDEF; 816 817 /* DAI clock strobing. Invert setting previously set */ 818 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 819 case SND_SOC_DAIFMT_NB_NF: 820 break; 821 case SND_SOC_DAIFMT_IB_NF: 822 cr1 ^= SAI_XCR1_CKSTR; 823 break; 824 case SND_SOC_DAIFMT_NB_IF: 825 frcr ^= SAI_XFRCR_FSPOL; 826 break; 827 case SND_SOC_DAIFMT_IB_IF: 828 /* Invert fs & sck */ 829 cr1 ^= SAI_XCR1_CKSTR; 830 frcr ^= SAI_XFRCR_FSPOL; 831 break; 832 default: 833 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 834 fmt & SND_SOC_DAIFMT_INV_MASK); 835 return -EINVAL; 836 } 837 cr1_mask |= SAI_XCR1_CKSTR; 838 frcr_mask |= SAI_XFRCR_FSPOL; 839 840 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 841 842 /* DAI clock master masks */ 843 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 844 case SND_SOC_DAIFMT_BC_FC: 845 /* codec is master */ 846 cr1 |= SAI_XCR1_SLAVE; 847 sai->master = false; 848 break; 849 case SND_SOC_DAIFMT_BP_FP: 850 sai->master = true; 851 break; 852 default: 853 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 854 fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); 855 return -EINVAL; 856 } 857 858 /* Set slave mode if sub-block is synchronized with another SAI */ 859 if (sai->sync) { 860 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 861 cr1 |= SAI_XCR1_SLAVE; 862 sai->master = false; 863 } 864 865 cr1_mask |= SAI_XCR1_SLAVE; 866 867 conf_update: 868 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 869 if (ret < 0) { 870 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 871 return ret; 872 } 873 874 sai->fmt = fmt; 875 876 return 0; 877 } 878 879 static int stm32_sai_startup(struct snd_pcm_substream *substream, 880 struct snd_soc_dai *cpu_dai) 881 { 882 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 883 int imr, cr2, ret; 884 unsigned long flags; 885 886 spin_lock_irqsave(&sai->irq_lock, flags); 887 sai->substream = substream; 888 spin_unlock_irqrestore(&sai->irq_lock, flags); 889 890 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 891 snd_pcm_hw_constraint_mask64(substream->runtime, 892 SNDRV_PCM_HW_PARAM_FORMAT, 893 SNDRV_PCM_FMTBIT_S32_LE); 894 snd_pcm_hw_constraint_single(substream->runtime, 895 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 896 } 897 898 ret = clk_prepare_enable(sai->sai_ck); 899 if (ret < 0) { 900 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 901 return ret; 902 } 903 904 /* Enable ITs */ 905 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, 906 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 907 908 imr = SAI_XIMR_OVRUDRIE; 909 if (STM_SAI_IS_CAPTURE(sai)) { 910 stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2); 911 if (cr2 & SAI_XCR2_MUTECNT_MASK) 912 imr |= SAI_XIMR_MUTEDETIE; 913 } 914 915 if (sai->master) 916 imr |= SAI_XIMR_WCKCFGIE; 917 else 918 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 919 920 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 921 SAI_XIMR_MASK, imr); 922 923 return 0; 924 } 925 926 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 927 struct snd_pcm_substream *substream, 928 struct snd_pcm_hw_params *params) 929 { 930 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 931 int cr1, cr1_mask, ret; 932 933 /* 934 * DMA bursts increment is set to 4 words. 935 * SAI fifo threshold is set to half fifo, to keep enough space 936 * for DMA incoming bursts. 937 */ 938 stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX, 939 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 940 SAI_XCR2_FFLUSH | 941 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 942 943 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 944 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 945 sai->spdif_frm_cnt = 0; 946 return 0; 947 } 948 949 /* Mode, data format and channel config */ 950 cr1_mask = SAI_XCR1_DS_MASK; 951 switch (params_format(params)) { 952 case SNDRV_PCM_FORMAT_S8: 953 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 954 break; 955 case SNDRV_PCM_FORMAT_S16_LE: 956 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 957 break; 958 case SNDRV_PCM_FORMAT_S32_LE: 959 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 960 break; 961 default: 962 dev_err(cpu_dai->dev, "Data format not supported\n"); 963 return -EINVAL; 964 } 965 966 cr1_mask |= SAI_XCR1_MONO; 967 if ((sai->slots == 2) && (params_channels(params) == 1)) 968 cr1 |= SAI_XCR1_MONO; 969 970 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 971 if (ret < 0) { 972 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 973 return ret; 974 } 975 976 return 0; 977 } 978 979 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 980 { 981 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 982 int slotr, slot_sz; 983 984 stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr); 985 986 /* 987 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 988 * By default slot width = data size, if not forced from DT 989 */ 990 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 991 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 992 sai->slot_width = sai->data_size; 993 994 if (sai->slot_width < sai->data_size) { 995 dev_err(cpu_dai->dev, 996 "Data size %d larger than slot width\n", 997 sai->data_size); 998 return -EINVAL; 999 } 1000 1001 /* Slot number is set to 2, if not specified in DT */ 1002 if (!sai->slots) 1003 sai->slots = 2; 1004 1005 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 1006 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 1007 SAI_XSLOTR_NBSLOT_MASK, 1008 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 1009 1010 /* Set default slots mask if not already set from DT */ 1011 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 1012 sai->slot_mask = (1 << sai->slots) - 1; 1013 stm32_sai_sub_reg_up(sai, 1014 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 1015 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 1016 } 1017 1018 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 1019 sai->slots, sai->slot_width); 1020 1021 return 0; 1022 } 1023 1024 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 1025 { 1026 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1027 int fs_active, offset, format; 1028 int frcr, frcr_mask; 1029 1030 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1031 sai->fs_length = sai->slot_width * sai->slots; 1032 1033 fs_active = sai->fs_length / 2; 1034 if ((format == SND_SOC_DAIFMT_DSP_A) || 1035 (format == SND_SOC_DAIFMT_DSP_B)) 1036 fs_active = 1; 1037 1038 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 1039 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 1040 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 1041 1042 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 1043 sai->fs_length, fs_active); 1044 1045 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 1046 1047 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 1048 offset = sai->slot_width - sai->data_size; 1049 1050 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 1051 SAI_XSLOTR_FBOFF_MASK, 1052 SAI_XSLOTR_FBOFF_SET(offset)); 1053 } 1054 } 1055 1056 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 1057 { 1058 unsigned char *cs = sai->iec958.status; 1059 1060 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 1061 cs[1] = IEC958_AES1_CON_GENERAL; 1062 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 1063 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 1064 } 1065 1066 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 1067 struct snd_pcm_runtime *runtime) 1068 { 1069 if (!runtime) 1070 return; 1071 1072 /* Force the sample rate according to runtime rate */ 1073 mutex_lock(&sai->ctrl_lock); 1074 switch (runtime->rate) { 1075 case 22050: 1076 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 1077 break; 1078 case 44100: 1079 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 1080 break; 1081 case 88200: 1082 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 1083 break; 1084 case 176400: 1085 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 1086 break; 1087 case 24000: 1088 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 1089 break; 1090 case 48000: 1091 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 1092 break; 1093 case 96000: 1094 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 1095 break; 1096 case 192000: 1097 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 1098 break; 1099 case 32000: 1100 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 1101 break; 1102 default: 1103 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 1104 break; 1105 } 1106 mutex_unlock(&sai->ctrl_lock); 1107 } 1108 1109 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 1110 struct snd_pcm_hw_params *params) 1111 { 1112 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1113 int div = 0, cr1 = 0; 1114 int sai_clk_rate, mclk_ratio, den; 1115 unsigned int rate = params_rate(params); 1116 int ret; 1117 1118 if (!sai->sai_mclk) { 1119 ret = sai->set_sai_ck_rate(sai, rate); 1120 if (ret) 1121 return ret; 1122 } 1123 sai_clk_rate = clk_get_rate(sai->sai_ck); 1124 1125 if (STM_SAI_IS_F4(sai->pdata)) { 1126 /* mclk on (NODIV=0) 1127 * mclk_rate = 256 * fs 1128 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 1129 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 1130 * mclk off (NODIV=1) 1131 * MCKDIV ignored. sck = sai_ck 1132 */ 1133 if (!sai->mclk_rate) 1134 return 0; 1135 1136 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 1137 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1138 2 * sai->mclk_rate); 1139 if (div < 0) 1140 return div; 1141 } 1142 } else { 1143 /* 1144 * TDM mode : 1145 * mclk on 1146 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 1147 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 1148 * mclk off 1149 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 1150 * Note: NOMCK/NODIV correspond to same bit. 1151 */ 1152 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1153 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1154 rate * 128); 1155 if (div < 0) 1156 return div; 1157 } else { 1158 if (sai->mclk_rate) { 1159 mclk_ratio = sai->mclk_rate / rate; 1160 if (mclk_ratio == 512) { 1161 cr1 = SAI_XCR1_OSR; 1162 } else if (mclk_ratio != 256) { 1163 dev_err(cpu_dai->dev, 1164 "Wrong mclk ratio %d\n", 1165 mclk_ratio); 1166 return -EINVAL; 1167 } 1168 1169 stm32_sai_sub_reg_up(sai, 1170 STM_SAI_CR1_REGX, 1171 SAI_XCR1_OSR, cr1); 1172 1173 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1174 sai->mclk_rate); 1175 if (div < 0) 1176 return div; 1177 } else { 1178 /* mclk-fs not set, master clock not active */ 1179 den = sai->fs_length * params_rate(params); 1180 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1181 den); 1182 if (div < 0) 1183 return div; 1184 } 1185 } 1186 } 1187 1188 return stm32_sai_set_clk_div(sai, div); 1189 } 1190 1191 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 1192 struct snd_pcm_hw_params *params, 1193 struct snd_soc_dai *cpu_dai) 1194 { 1195 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1196 int ret; 1197 1198 sai->data_size = params_width(params); 1199 1200 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1201 /* Rate not already set in runtime structure */ 1202 substream->runtime->rate = params_rate(params); 1203 stm32_sai_set_iec958_status(sai, substream->runtime); 1204 } else { 1205 ret = stm32_sai_set_slots(cpu_dai); 1206 if (ret < 0) 1207 return ret; 1208 stm32_sai_set_frame(cpu_dai); 1209 } 1210 1211 ret = stm32_sai_set_config(cpu_dai, substream, params); 1212 if (ret) 1213 return ret; 1214 1215 if (sai->master) 1216 ret = stm32_sai_configure_clock(cpu_dai, params); 1217 1218 return ret; 1219 } 1220 1221 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 1222 struct snd_soc_dai *cpu_dai) 1223 { 1224 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1225 int ret; 1226 1227 switch (cmd) { 1228 case SNDRV_PCM_TRIGGER_START: 1229 case SNDRV_PCM_TRIGGER_RESUME: 1230 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1231 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 1232 1233 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1234 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 1235 1236 /* Enable SAI */ 1237 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1238 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 1239 if (ret < 0) 1240 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1241 break; 1242 case SNDRV_PCM_TRIGGER_SUSPEND: 1243 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1244 case SNDRV_PCM_TRIGGER_STOP: 1245 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 1246 1247 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 1248 SAI_XIMR_MASK, 0); 1249 1250 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1251 SAI_XCR1_SAIEN, 1252 (unsigned int)~SAI_XCR1_SAIEN); 1253 1254 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1255 SAI_XCR1_DMAEN, 1256 (unsigned int)~SAI_XCR1_DMAEN); 1257 if (ret < 0) 1258 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1259 1260 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1261 sai->spdif_frm_cnt = 0; 1262 break; 1263 default: 1264 return -EINVAL; 1265 } 1266 1267 return ret; 1268 } 1269 1270 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 1271 struct snd_soc_dai *cpu_dai) 1272 { 1273 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1274 unsigned long flags; 1275 1276 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 1277 1278 clk_disable_unprepare(sai->sai_ck); 1279 1280 /* 1281 * Release kernel clock if following conditions are fulfilled 1282 * - Master clock is not used. Kernel clock won't be released trough sysclk 1283 * - Put handler is defined. Involve that clock is managed exclusively 1284 */ 1285 if (!sai->sai_mclk && sai->put_sai_ck_rate) 1286 sai->put_sai_ck_rate(sai); 1287 1288 spin_lock_irqsave(&sai->irq_lock, flags); 1289 sai->substream = NULL; 1290 spin_unlock_irqrestore(&sai->irq_lock, flags); 1291 } 1292 1293 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1294 struct snd_soc_dai *cpu_dai) 1295 { 1296 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1297 struct snd_kcontrol_new knew = iec958_ctls; 1298 1299 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1300 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 1301 knew.device = rtd->pcm->device; 1302 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1303 } 1304 1305 return 0; 1306 } 1307 1308 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 1309 { 1310 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1311 int cr1 = 0, cr1_mask, ret; 1312 1313 sai->cpu_dai = cpu_dai; 1314 1315 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1316 /* 1317 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1318 * as it allows bytes, half-word and words transfers. (See DMA fifos 1319 * constraints). 1320 */ 1321 sai->dma_params.maxburst = 4; 1322 if (sai->pdata->conf.fifo_size < 8 || sai->pdata->conf.no_dma_burst) 1323 sai->dma_params.maxburst = 1; 1324 /* Buswidth will be set by framework at runtime */ 1325 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1326 1327 if (STM_SAI_IS_PLAYBACK(sai)) 1328 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 1329 else 1330 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 1331 1332 /* Next settings are not relevant for spdif mode */ 1333 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1334 return 0; 1335 1336 cr1_mask = SAI_XCR1_RX_TX; 1337 if (STM_SAI_IS_CAPTURE(sai)) 1338 cr1 |= SAI_XCR1_RX_TX; 1339 1340 /* Configure synchronization */ 1341 if (sai->sync == SAI_SYNC_EXTERNAL) { 1342 /* Configure synchro client and provider */ 1343 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 1344 sai->synco, sai->synci); 1345 if (ret) 1346 return ret; 1347 } 1348 1349 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 1350 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 1351 1352 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 1353 } 1354 1355 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 1356 .probe = stm32_sai_dai_probe, 1357 .set_sysclk = stm32_sai_set_sysclk, 1358 .set_fmt = stm32_sai_set_dai_fmt, 1359 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1360 .startup = stm32_sai_startup, 1361 .hw_params = stm32_sai_hw_params, 1362 .trigger = stm32_sai_trigger, 1363 .shutdown = stm32_sai_shutdown, 1364 .pcm_new = stm32_sai_pcm_new, 1365 }; 1366 1367 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops2 = { 1368 .probe = stm32_sai_dai_probe, 1369 .set_sysclk = stm32_sai_set_sysclk, 1370 .set_fmt = stm32_sai_set_dai_fmt, 1371 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1372 .startup = stm32_sai_startup, 1373 .hw_params = stm32_sai_hw_params, 1374 .trigger = stm32_sai_trigger, 1375 .shutdown = stm32_sai_shutdown, 1376 }; 1377 1378 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 1379 int channel, unsigned long hwoff, 1380 unsigned long bytes) 1381 { 1382 struct snd_pcm_runtime *runtime = substream->runtime; 1383 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1384 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 1385 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1386 int *ptr = (int *)(runtime->dma_area + hwoff + 1387 channel * (runtime->dma_bytes / runtime->channels)); 1388 ssize_t cnt = bytes_to_samples(runtime, bytes); 1389 unsigned int frm_cnt = sai->spdif_frm_cnt; 1390 unsigned int byte; 1391 unsigned int mask; 1392 1393 do { 1394 *ptr = ((*ptr >> 8) & 0x00ffffff); 1395 1396 /* Set channel status bit */ 1397 byte = frm_cnt >> 3; 1398 mask = 1 << (frm_cnt - (byte << 3)); 1399 if (sai->iec958.status[byte] & mask) 1400 *ptr |= 0x04000000; 1401 ptr++; 1402 1403 if (!(cnt % 2)) 1404 frm_cnt++; 1405 1406 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 1407 frm_cnt = 0; 1408 } while (--cnt); 1409 sai->spdif_frm_cnt = frm_cnt; 1410 1411 return 0; 1412 } 1413 1414 /* No support of mmap in S/PDIF mode */ 1415 static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = { 1416 .info = SNDRV_PCM_INFO_INTERLEAVED, 1417 .buffer_bytes_max = 8 * PAGE_SIZE, 1418 .period_bytes_min = 1024, 1419 .period_bytes_max = PAGE_SIZE, 1420 .periods_min = 2, 1421 .periods_max = 8, 1422 }; 1423 1424 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 1425 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 1426 .buffer_bytes_max = 8 * PAGE_SIZE, 1427 .period_bytes_min = 1024, /* 5ms at 48kHz */ 1428 .period_bytes_max = PAGE_SIZE, 1429 .periods_min = 2, 1430 .periods_max = 8, 1431 }; 1432 1433 static struct snd_soc_dai_driver stm32_sai_playback_dai = { 1434 .id = 1, /* avoid call to fmt_single_name() */ 1435 .playback = { 1436 .channels_min = 1, 1437 .channels_max = 16, 1438 .rate_min = 8000, 1439 .rate_max = 192000, 1440 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1441 /* DMA does not support 24 bits transfers */ 1442 .formats = 1443 SNDRV_PCM_FMTBIT_S8 | 1444 SNDRV_PCM_FMTBIT_S16_LE | 1445 SNDRV_PCM_FMTBIT_S32_LE, 1446 }, 1447 .ops = &stm32_sai_pcm_dai_ops, 1448 }; 1449 1450 static struct snd_soc_dai_driver stm32_sai_capture_dai = { 1451 .id = 1, /* avoid call to fmt_single_name() */ 1452 .capture = { 1453 .channels_min = 1, 1454 .channels_max = 16, 1455 .rate_min = 8000, 1456 .rate_max = 192000, 1457 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1458 /* DMA does not support 24 bits transfers */ 1459 .formats = 1460 SNDRV_PCM_FMTBIT_S8 | 1461 SNDRV_PCM_FMTBIT_S16_LE | 1462 SNDRV_PCM_FMTBIT_S32_LE, 1463 }, 1464 .ops = &stm32_sai_pcm_dai_ops2, 1465 }; 1466 1467 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 1468 .pcm_hardware = &stm32_sai_pcm_hw, 1469 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1470 }; 1471 1472 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 1473 .pcm_hardware = &stm32_sai_pcm_hw_spdif, 1474 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1475 .process = stm32_sai_pcm_process_spdif, 1476 }; 1477 1478 static const struct snd_soc_component_driver stm32_component = { 1479 .name = "stm32-sai", 1480 .legacy_dai_naming = 1, 1481 }; 1482 1483 static const struct of_device_id stm32_sai_sub_ids[] = { 1484 { .compatible = "st,stm32-sai-sub-a", 1485 .data = (void *)STM_SAI_A_ID}, 1486 { .compatible = "st,stm32-sai-sub-b", 1487 .data = (void *)STM_SAI_B_ID}, 1488 {} 1489 }; 1490 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 1491 1492 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 1493 struct stm32_sai_sub_data *sai) 1494 { 1495 struct device_node *np = pdev->dev.of_node; 1496 struct resource *res; 1497 void __iomem *base; 1498 struct of_phandle_args args; 1499 int ret; 1500 1501 if (!np) 1502 return -ENODEV; 1503 1504 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1505 if (IS_ERR(base)) 1506 return PTR_ERR(base); 1507 1508 sai->phys_addr = res->start; 1509 1510 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 1511 /* Note: PDM registers not available for sub-block B */ 1512 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai)) 1513 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 1514 1515 /* 1516 * Do not manage peripheral clock through regmap framework as this 1517 * can lead to circular locking issue with sai master clock provider. 1518 * Manage peripheral clock directly in driver instead. 1519 */ 1520 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1521 sai->regmap_config); 1522 if (IS_ERR(sai->regmap)) 1523 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap), 1524 "Regmap init error\n"); 1525 1526 /* Get direction property */ 1527 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 1528 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 1529 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 1530 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 1531 } else { 1532 dev_err(&pdev->dev, "Unsupported direction\n"); 1533 return -EINVAL; 1534 } 1535 1536 /* Get spdif iec60958 property */ 1537 sai->spdif = false; 1538 if (of_property_present(np, "st,iec60958")) { 1539 if (!STM_SAI_HAS_SPDIF(sai) || 1540 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 1541 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 1542 return -EINVAL; 1543 } 1544 stm32_sai_init_iec958_status(sai); 1545 sai->spdif = true; 1546 sai->master = true; 1547 } 1548 1549 /* Get synchronization property */ 1550 args.np = NULL; 1551 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1552 if (ret < 0 && ret != -ENOENT) { 1553 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1554 return ret; 1555 } 1556 1557 sai->sync = SAI_SYNC_NONE; 1558 if (args.np) { 1559 if (args.np == np) { 1560 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 1561 of_node_put(args.np); 1562 return -EINVAL; 1563 } 1564 1565 sai->np_sync_provider = of_get_parent(args.np); 1566 if (!sai->np_sync_provider) { 1567 dev_err(&pdev->dev, "%pOFn parent node not found\n", 1568 np); 1569 of_node_put(args.np); 1570 return -ENODEV; 1571 } 1572 1573 sai->sync = SAI_SYNC_INTERNAL; 1574 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1575 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1576 dev_err(&pdev->dev, 1577 "External synchro not supported\n"); 1578 of_node_put(args.np); 1579 return -EINVAL; 1580 } 1581 sai->sync = SAI_SYNC_EXTERNAL; 1582 1583 sai->synci = args.args[0]; 1584 if (sai->synci < 1 || 1585 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1586 dev_err(&pdev->dev, "Wrong SAI index\n"); 1587 of_node_put(args.np); 1588 return -EINVAL; 1589 } 1590 1591 if (of_property_match_string(args.np, "compatible", 1592 "st,stm32-sai-sub-a") >= 0) 1593 sai->synco = STM_SAI_SYNC_OUT_A; 1594 1595 if (of_property_match_string(args.np, "compatible", 1596 "st,stm32-sai-sub-b") >= 0) 1597 sai->synco = STM_SAI_SYNC_OUT_B; 1598 1599 if (!sai->synco) { 1600 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1601 of_node_put(args.np); 1602 return -EINVAL; 1603 } 1604 } 1605 1606 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1607 pdev->name, args.np->full_name); 1608 } 1609 1610 of_node_put(args.np); 1611 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1612 if (IS_ERR(sai->sai_ck)) 1613 return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck), 1614 "Missing kernel clock sai_ck\n"); 1615 1616 ret = clk_prepare(sai->pdata->pclk); 1617 if (ret < 0) 1618 return ret; 1619 1620 if (STM_SAI_IS_F4(sai->pdata)) 1621 return 0; 1622 1623 /* Register mclk provider if requested */ 1624 if (of_property_present(np, "#clock-cells")) { 1625 ret = stm32_sai_add_mclk_provider(sai); 1626 if (ret < 0) 1627 return ret; 1628 } else { 1629 sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK"); 1630 if (IS_ERR(sai->sai_mclk)) 1631 return PTR_ERR(sai->sai_mclk); 1632 } 1633 1634 return 0; 1635 } 1636 1637 static int stm32_sai_sub_probe(struct platform_device *pdev) 1638 { 1639 struct stm32_sai_sub_data *sai; 1640 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1641 int ret; 1642 1643 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1644 if (!sai) 1645 return -ENOMEM; 1646 1647 sai->id = (uintptr_t)device_get_match_data(&pdev->dev); 1648 1649 sai->pdev = pdev; 1650 mutex_init(&sai->ctrl_lock); 1651 spin_lock_init(&sai->irq_lock); 1652 platform_set_drvdata(pdev, sai); 1653 1654 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1655 if (!sai->pdata) { 1656 dev_err(&pdev->dev, "Parent device data not available\n"); 1657 return -EINVAL; 1658 } 1659 1660 if (sai->pdata->conf.get_sai_ck_parent) { 1661 sai->set_sai_ck_rate = stm32_sai_set_parent_clk; 1662 } else { 1663 sai->set_sai_ck_rate = stm32_sai_set_parent_rate; 1664 sai->put_sai_ck_rate = stm32_sai_put_parent_rate; 1665 } 1666 1667 ret = stm32_sai_sub_parse_of(pdev, sai); 1668 if (ret) 1669 return ret; 1670 1671 if (STM_SAI_IS_PLAYBACK(sai)) 1672 sai->cpu_dai_drv = stm32_sai_playback_dai; 1673 else 1674 sai->cpu_dai_drv = stm32_sai_capture_dai; 1675 sai->cpu_dai_drv.name = dev_name(&pdev->dev); 1676 1677 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1678 IRQF_SHARED, dev_name(&pdev->dev), sai); 1679 if (ret) { 1680 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1681 return ret; 1682 } 1683 1684 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1685 conf = &stm32_sai_pcm_config_spdif; 1686 1687 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1688 if (ret) 1689 return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n"); 1690 1691 ret = snd_soc_register_component(&pdev->dev, &stm32_component, 1692 &sai->cpu_dai_drv, 1); 1693 if (ret) { 1694 snd_dmaengine_pcm_unregister(&pdev->dev); 1695 return ret; 1696 } 1697 1698 pm_runtime_enable(&pdev->dev); 1699 1700 return 0; 1701 } 1702 1703 static void stm32_sai_sub_remove(struct platform_device *pdev) 1704 { 1705 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev); 1706 1707 clk_unprepare(sai->pdata->pclk); 1708 snd_dmaengine_pcm_unregister(&pdev->dev); 1709 snd_soc_unregister_component(&pdev->dev); 1710 pm_runtime_disable(&pdev->dev); 1711 } 1712 1713 static int stm32_sai_sub_suspend(struct device *dev) 1714 { 1715 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1716 int ret; 1717 1718 ret = clk_enable(sai->pdata->pclk); 1719 if (ret < 0) 1720 return ret; 1721 1722 regcache_cache_only(sai->regmap, true); 1723 regcache_mark_dirty(sai->regmap); 1724 1725 clk_disable(sai->pdata->pclk); 1726 1727 return 0; 1728 } 1729 1730 static int stm32_sai_sub_resume(struct device *dev) 1731 { 1732 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1733 int ret; 1734 1735 ret = clk_enable(sai->pdata->pclk); 1736 if (ret < 0) 1737 return ret; 1738 1739 regcache_cache_only(sai->regmap, false); 1740 ret = regcache_sync(sai->regmap); 1741 1742 clk_disable(sai->pdata->pclk); 1743 1744 return ret; 1745 } 1746 1747 static const struct dev_pm_ops stm32_sai_sub_pm_ops = { 1748 SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume) 1749 }; 1750 1751 static struct platform_driver stm32_sai_sub_driver = { 1752 .driver = { 1753 .name = "st,stm32-sai-sub", 1754 .of_match_table = stm32_sai_sub_ids, 1755 .pm = pm_ptr(&stm32_sai_sub_pm_ops), 1756 }, 1757 .probe = stm32_sai_sub_probe, 1758 .remove = stm32_sai_sub_remove, 1759 }; 1760 1761 module_platform_driver(stm32_sai_sub_driver); 1762 1763 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1764 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1765 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1766 MODULE_LICENSE("GPL v2"); 1767