1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/regmap.h> 25 26 #include <sound/core.h> 27 #include <sound/dmaengine_pcm.h> 28 #include <sound/pcm_params.h> 29 30 #include "stm32_sai.h" 31 32 #define SAI_FREE_PROTOCOL 0x0 33 34 #define SAI_SLOT_SIZE_AUTO 0x0 35 #define SAI_SLOT_SIZE_16 0x1 36 #define SAI_SLOT_SIZE_32 0x2 37 38 #define SAI_DATASIZE_8 0x2 39 #define SAI_DATASIZE_10 0x3 40 #define SAI_DATASIZE_16 0x4 41 #define SAI_DATASIZE_20 0x5 42 #define SAI_DATASIZE_24 0x6 43 #define SAI_DATASIZE_32 0x7 44 45 #define STM_SAI_FIFO_SIZE 8 46 #define STM_SAI_DAI_NAME_SIZE 15 47 48 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 49 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 50 51 #define STM_SAI_A_ID 0x0 52 #define STM_SAI_B_ID 0x1 53 54 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 55 56 /** 57 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 58 * @pdev: device data pointer 59 * @regmap: SAI register map pointer 60 * @dma_params: dma configuration data for rx or tx channel 61 * @cpu_dai_drv: DAI driver data pointer 62 * @cpu_dai: DAI runtime data pointer 63 * @substream: PCM substream data pointer 64 * @pdata: SAI block parent data pointer 65 * @sai_ck: kernel clock feeding the SAI clock generator 66 * @phys_addr: SAI registers physical base address 67 * @mclk_rate: SAI block master clock frequency (Hz). set at init 68 * @id: SAI sub block id corresponding to sub-block A or B 69 * @dir: SAI block direction (playback or capture). set at init 70 * @master: SAI block mode flag. (true=master, false=slave) set at init 71 * @fmt: SAI block format. relevant only for custom protocols. set at init 72 * @sync: SAI block synchronization mode. (none, internal or external) 73 * @fs_length: frame synchronization length. depends on protocol settings 74 * @slots: rx or tx slot number 75 * @slot_width: rx or tx slot width in bits 76 * @slot_mask: rx or tx active slots mask. set at init or at runtime 77 * @data_size: PCM data width. corresponds to PCM substream width. 78 */ 79 struct stm32_sai_sub_data { 80 struct platform_device *pdev; 81 struct regmap *regmap; 82 struct snd_dmaengine_dai_dma_data dma_params; 83 struct snd_soc_dai_driver *cpu_dai_drv; 84 struct snd_soc_dai *cpu_dai; 85 struct snd_pcm_substream *substream; 86 struct stm32_sai_data *pdata; 87 struct clk *sai_ck; 88 dma_addr_t phys_addr; 89 unsigned int mclk_rate; 90 unsigned int id; 91 int dir; 92 bool master; 93 int fmt; 94 int sync; 95 int fs_length; 96 int slots; 97 int slot_width; 98 int slot_mask; 99 int data_size; 100 }; 101 102 enum stm32_sai_fifo_th { 103 STM_SAI_FIFO_TH_EMPTY, 104 STM_SAI_FIFO_TH_QUARTER, 105 STM_SAI_FIFO_TH_HALF, 106 STM_SAI_FIFO_TH_3_QUARTER, 107 STM_SAI_FIFO_TH_FULL, 108 }; 109 110 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 111 { 112 switch (reg) { 113 case STM_SAI_CR1_REGX: 114 case STM_SAI_CR2_REGX: 115 case STM_SAI_FRCR_REGX: 116 case STM_SAI_SLOTR_REGX: 117 case STM_SAI_IMR_REGX: 118 case STM_SAI_SR_REGX: 119 case STM_SAI_CLRFR_REGX: 120 case STM_SAI_DR_REGX: 121 return true; 122 default: 123 return false; 124 } 125 } 126 127 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 128 { 129 switch (reg) { 130 case STM_SAI_DR_REGX: 131 return true; 132 default: 133 return false; 134 } 135 } 136 137 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 138 { 139 switch (reg) { 140 case STM_SAI_CR1_REGX: 141 case STM_SAI_CR2_REGX: 142 case STM_SAI_FRCR_REGX: 143 case STM_SAI_SLOTR_REGX: 144 case STM_SAI_IMR_REGX: 145 case STM_SAI_SR_REGX: 146 case STM_SAI_CLRFR_REGX: 147 case STM_SAI_DR_REGX: 148 return true; 149 default: 150 return false; 151 } 152 } 153 154 static const struct regmap_config stm32_sai_sub_regmap_config = { 155 .reg_bits = 32, 156 .reg_stride = 4, 157 .val_bits = 32, 158 .max_register = STM_SAI_DR_REGX, 159 .readable_reg = stm32_sai_sub_readable_reg, 160 .volatile_reg = stm32_sai_sub_volatile_reg, 161 .writeable_reg = stm32_sai_sub_writeable_reg, 162 .fast_io = true, 163 }; 164 165 static irqreturn_t stm32_sai_isr(int irq, void *devid) 166 { 167 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 168 struct snd_pcm_substream *substream = sai->substream; 169 struct platform_device *pdev = sai->pdev; 170 unsigned int sr, imr, flags; 171 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 172 173 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 174 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 175 176 flags = sr & imr; 177 if (!flags) 178 return IRQ_NONE; 179 180 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 181 SAI_XCLRFR_MASK); 182 183 if (flags & SAI_XIMR_OVRUDRIE) { 184 dev_err(&pdev->dev, "IT %s\n", 185 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 186 status = SNDRV_PCM_STATE_XRUN; 187 } 188 189 if (flags & SAI_XIMR_MUTEDETIE) 190 dev_dbg(&pdev->dev, "IT mute detected\n"); 191 192 if (flags & SAI_XIMR_WCKCFGIE) { 193 dev_err(&pdev->dev, "IT wrong clock configuration\n"); 194 status = SNDRV_PCM_STATE_DISCONNECTED; 195 } 196 197 if (flags & SAI_XIMR_CNRDYIE) 198 dev_warn(&pdev->dev, "IT Codec not ready\n"); 199 200 if (flags & SAI_XIMR_AFSDETIE) { 201 dev_warn(&pdev->dev, "IT Anticipated frame synchro\n"); 202 status = SNDRV_PCM_STATE_XRUN; 203 } 204 205 if (flags & SAI_XIMR_LFSDETIE) { 206 dev_warn(&pdev->dev, "IT Late frame synchro\n"); 207 status = SNDRV_PCM_STATE_XRUN; 208 } 209 210 if (status != SNDRV_PCM_STATE_RUNNING) { 211 snd_pcm_stream_lock(substream); 212 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 213 snd_pcm_stream_unlock(substream); 214 } 215 216 return IRQ_HANDLED; 217 } 218 219 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 220 int clk_id, unsigned int freq, int dir) 221 { 222 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 223 224 if ((dir == SND_SOC_CLOCK_OUT) && sai->master) { 225 sai->mclk_rate = freq; 226 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 227 } 228 229 return 0; 230 } 231 232 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 233 u32 rx_mask, int slots, int slot_width) 234 { 235 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 236 int slotr, slotr_mask, slot_size; 237 238 dev_dbg(cpu_dai->dev, "masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 239 tx_mask, rx_mask, slots, slot_width); 240 241 switch (slot_width) { 242 case 16: 243 slot_size = SAI_SLOT_SIZE_16; 244 break; 245 case 32: 246 slot_size = SAI_SLOT_SIZE_32; 247 break; 248 default: 249 slot_size = SAI_SLOT_SIZE_AUTO; 250 break; 251 } 252 253 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 254 SAI_XSLOTR_NBSLOT_SET(slots - 1); 255 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 256 257 /* tx/rx mask set in machine init, if slot number defined in DT */ 258 if (STM_SAI_IS_PLAYBACK(sai)) { 259 sai->slot_mask = tx_mask; 260 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 261 } 262 263 if (STM_SAI_IS_CAPTURE(sai)) { 264 sai->slot_mask = rx_mask; 265 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 266 } 267 268 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 269 270 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 271 272 sai->slot_width = slot_width; 273 sai->slots = slots; 274 275 return 0; 276 } 277 278 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 279 { 280 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 281 int cr1 = 0, frcr = 0; 282 int cr1_mask = 0, frcr_mask = 0; 283 int ret; 284 285 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 286 287 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 288 /* SCK active high for all protocols */ 289 case SND_SOC_DAIFMT_I2S: 290 cr1 |= SAI_XCR1_CKSTR; 291 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 292 break; 293 /* Left justified */ 294 case SND_SOC_DAIFMT_MSB: 295 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 296 break; 297 /* Right justified */ 298 case SND_SOC_DAIFMT_LSB: 299 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 300 break; 301 case SND_SOC_DAIFMT_DSP_A: 302 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 303 break; 304 case SND_SOC_DAIFMT_DSP_B: 305 frcr |= SAI_XFRCR_FSPOL; 306 break; 307 default: 308 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 309 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 310 return -EINVAL; 311 } 312 313 cr1_mask |= SAI_XCR1_PRTCFG_MASK | SAI_XCR1_CKSTR; 314 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 315 SAI_XFRCR_FSDEF; 316 317 /* DAI clock strobing. Invert setting previously set */ 318 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 319 case SND_SOC_DAIFMT_NB_NF: 320 break; 321 case SND_SOC_DAIFMT_IB_NF: 322 cr1 ^= SAI_XCR1_CKSTR; 323 break; 324 case SND_SOC_DAIFMT_NB_IF: 325 frcr ^= SAI_XFRCR_FSPOL; 326 break; 327 case SND_SOC_DAIFMT_IB_IF: 328 /* Invert fs & sck */ 329 cr1 ^= SAI_XCR1_CKSTR; 330 frcr ^= SAI_XFRCR_FSPOL; 331 break; 332 default: 333 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 334 fmt & SND_SOC_DAIFMT_INV_MASK); 335 return -EINVAL; 336 } 337 cr1_mask |= SAI_XCR1_CKSTR; 338 frcr_mask |= SAI_XFRCR_FSPOL; 339 340 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 341 342 /* DAI clock master masks */ 343 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 344 case SND_SOC_DAIFMT_CBM_CFM: 345 /* codec is master */ 346 cr1 |= SAI_XCR1_SLAVE; 347 sai->master = false; 348 break; 349 case SND_SOC_DAIFMT_CBS_CFS: 350 sai->master = true; 351 break; 352 default: 353 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 354 fmt & SND_SOC_DAIFMT_MASTER_MASK); 355 return -EINVAL; 356 } 357 cr1_mask |= SAI_XCR1_SLAVE; 358 359 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 360 if (ret < 0) { 361 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 362 return ret; 363 } 364 365 sai->fmt = fmt; 366 367 return 0; 368 } 369 370 static int stm32_sai_startup(struct snd_pcm_substream *substream, 371 struct snd_soc_dai *cpu_dai) 372 { 373 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 374 int imr, cr2, ret; 375 376 sai->substream = substream; 377 378 ret = clk_prepare_enable(sai->sai_ck); 379 if (ret < 0) { 380 dev_err(cpu_dai->dev, "failed to enable clock: %d\n", ret); 381 return ret; 382 } 383 384 /* Enable ITs */ 385 regmap_update_bits(sai->regmap, STM_SAI_SR_REGX, 386 SAI_XSR_MASK, (unsigned int)~SAI_XSR_MASK); 387 388 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, 389 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 390 391 imr = SAI_XIMR_OVRUDRIE; 392 if (STM_SAI_IS_CAPTURE(sai)) { 393 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 394 if (cr2 & SAI_XCR2_MUTECNT_MASK) 395 imr |= SAI_XIMR_MUTEDETIE; 396 } 397 398 if (sai->master) 399 imr |= SAI_XIMR_WCKCFGIE; 400 else 401 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 402 403 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 404 SAI_XIMR_MASK, imr); 405 406 return 0; 407 } 408 409 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 410 struct snd_pcm_substream *substream, 411 struct snd_pcm_hw_params *params) 412 { 413 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 414 int cr1, cr1_mask, ret; 415 int fth = STM_SAI_FIFO_TH_HALF; 416 417 /* FIFO config */ 418 regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX, 419 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 420 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_SET(fth)); 421 422 /* Mode, data format and channel config */ 423 cr1 = SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 424 switch (params_format(params)) { 425 case SNDRV_PCM_FORMAT_S8: 426 cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_8); 427 break; 428 case SNDRV_PCM_FORMAT_S16_LE: 429 cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_16); 430 break; 431 case SNDRV_PCM_FORMAT_S32_LE: 432 cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_32); 433 break; 434 default: 435 dev_err(cpu_dai->dev, "Data format not supported"); 436 return -EINVAL; 437 } 438 cr1_mask = SAI_XCR1_DS_MASK | SAI_XCR1_PRTCFG_MASK; 439 440 cr1_mask |= SAI_XCR1_RX_TX; 441 if (STM_SAI_IS_CAPTURE(sai)) 442 cr1 |= SAI_XCR1_RX_TX; 443 444 cr1_mask |= SAI_XCR1_MONO; 445 if ((sai->slots == 2) && (params_channels(params) == 1)) 446 cr1 |= SAI_XCR1_MONO; 447 448 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 449 if (ret < 0) { 450 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 451 return ret; 452 } 453 454 /* DMA config */ 455 sai->dma_params.maxburst = STM_SAI_FIFO_SIZE * fth / sizeof(u32); 456 snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)&sai->dma_params); 457 458 return 0; 459 } 460 461 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 462 { 463 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 464 int slotr, slot_sz; 465 466 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 467 468 /* 469 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 470 * By default slot width = data size, if not forced from DT 471 */ 472 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 473 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 474 sai->slot_width = sai->data_size; 475 476 if (sai->slot_width < sai->data_size) { 477 dev_err(cpu_dai->dev, 478 "Data size %d larger than slot width\n", 479 sai->data_size); 480 return -EINVAL; 481 } 482 483 /* Slot number is set to 2, if not specified in DT */ 484 if (!sai->slots) 485 sai->slots = 2; 486 487 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 488 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 489 SAI_XSLOTR_NBSLOT_MASK, 490 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 491 492 /* Set default slots mask if not already set from DT */ 493 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 494 sai->slot_mask = (1 << sai->slots) - 1; 495 regmap_update_bits(sai->regmap, 496 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 497 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 498 } 499 500 dev_dbg(cpu_dai->dev, "slots %d, slot width %d\n", 501 sai->slots, sai->slot_width); 502 503 return 0; 504 } 505 506 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 507 { 508 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 509 int fs_active, offset, format; 510 int frcr, frcr_mask; 511 512 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 513 sai->fs_length = sai->slot_width * sai->slots; 514 515 fs_active = sai->fs_length / 2; 516 if ((format == SND_SOC_DAIFMT_DSP_A) || 517 (format == SND_SOC_DAIFMT_DSP_B)) 518 fs_active = 1; 519 520 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 521 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 522 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 523 524 dev_dbg(cpu_dai->dev, "frame length %d, frame active %d\n", 525 sai->fs_length, fs_active); 526 527 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 528 529 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 530 offset = sai->slot_width - sai->data_size; 531 532 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 533 SAI_XSLOTR_FBOFF_MASK, 534 SAI_XSLOTR_FBOFF_SET(offset)); 535 } 536 } 537 538 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 539 struct snd_pcm_hw_params *params) 540 { 541 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 542 int cr1, mask, div = 0; 543 int sai_clk_rate, ret; 544 545 if (!sai->mclk_rate) { 546 dev_err(cpu_dai->dev, "Mclk rate is null\n"); 547 return -EINVAL; 548 } 549 550 if (!(params_rate(params) % 11025)) 551 clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k); 552 else 553 clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k); 554 sai_clk_rate = clk_get_rate(sai->sai_ck); 555 556 /* 557 * mclk_rate = 256 * fs 558 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 559 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 560 */ 561 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) 562 div = DIV_ROUND_CLOSEST(sai_clk_rate, 2 * sai->mclk_rate); 563 564 if (div > SAI_XCR1_MCKDIV_MAX) { 565 dev_err(cpu_dai->dev, "Divider %d out of range\n", div); 566 return -EINVAL; 567 } 568 dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div); 569 570 mask = SAI_XCR1_MCKDIV_MASK; 571 cr1 = SAI_XCR1_MCKDIV_SET(div); 572 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 573 if (ret < 0) { 574 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 575 return ret; 576 } 577 578 return 0; 579 } 580 581 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 582 struct snd_pcm_hw_params *params, 583 struct snd_soc_dai *cpu_dai) 584 { 585 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 586 int ret; 587 588 sai->data_size = params_width(params); 589 590 ret = stm32_sai_set_slots(cpu_dai); 591 if (ret < 0) 592 return ret; 593 stm32_sai_set_frame(cpu_dai); 594 595 ret = stm32_sai_set_config(cpu_dai, substream, params); 596 if (ret) 597 return ret; 598 599 if (sai->master) 600 ret = stm32_sai_configure_clock(cpu_dai, params); 601 602 return ret; 603 } 604 605 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 606 struct snd_soc_dai *cpu_dai) 607 { 608 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 609 int ret; 610 611 switch (cmd) { 612 case SNDRV_PCM_TRIGGER_START: 613 case SNDRV_PCM_TRIGGER_RESUME: 614 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 615 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 616 617 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 618 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 619 620 /* Enable SAI */ 621 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 622 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 623 if (ret < 0) 624 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 625 break; 626 case SNDRV_PCM_TRIGGER_SUSPEND: 627 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 628 case SNDRV_PCM_TRIGGER_STOP: 629 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 630 631 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 632 SAI_XCR1_DMAEN, 633 (unsigned int)~SAI_XCR1_DMAEN); 634 635 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 636 SAI_XCR1_SAIEN, 637 (unsigned int)~SAI_XCR1_SAIEN); 638 if (ret < 0) 639 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 640 break; 641 default: 642 return -EINVAL; 643 } 644 645 return ret; 646 } 647 648 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 649 struct snd_soc_dai *cpu_dai) 650 { 651 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 652 653 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 654 655 clk_disable_unprepare(sai->sai_ck); 656 sai->substream = NULL; 657 } 658 659 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 660 { 661 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 662 663 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 664 sai->dma_params.maxburst = 1; 665 /* Buswidth will be set by framework at runtime */ 666 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 667 668 if (STM_SAI_IS_PLAYBACK(sai)) 669 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 670 else 671 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 672 673 return 0; 674 } 675 676 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 677 .set_sysclk = stm32_sai_set_sysclk, 678 .set_fmt = stm32_sai_set_dai_fmt, 679 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 680 .startup = stm32_sai_startup, 681 .hw_params = stm32_sai_hw_params, 682 .trigger = stm32_sai_trigger, 683 .shutdown = stm32_sai_shutdown, 684 }; 685 686 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 687 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 688 .buffer_bytes_max = 8 * PAGE_SIZE, 689 .period_bytes_min = 1024, /* 5ms at 48kHz */ 690 .period_bytes_max = PAGE_SIZE, 691 .periods_min = 2, 692 .periods_max = 8, 693 }; 694 695 static struct snd_soc_dai_driver stm32_sai_playback_dai[] = { 696 { 697 .probe = stm32_sai_dai_probe, 698 .id = 1, /* avoid call to fmt_single_name() */ 699 .playback = { 700 .channels_min = 1, 701 .channels_max = 2, 702 .rate_min = 8000, 703 .rate_max = 192000, 704 .rates = SNDRV_PCM_RATE_CONTINUOUS, 705 /* DMA does not support 24 bits transfers */ 706 .formats = 707 SNDRV_PCM_FMTBIT_S8 | 708 SNDRV_PCM_FMTBIT_S16_LE | 709 SNDRV_PCM_FMTBIT_S32_LE, 710 }, 711 .ops = &stm32_sai_pcm_dai_ops, 712 } 713 }; 714 715 static struct snd_soc_dai_driver stm32_sai_capture_dai[] = { 716 { 717 .probe = stm32_sai_dai_probe, 718 .id = 1, /* avoid call to fmt_single_name() */ 719 .capture = { 720 .channels_min = 1, 721 .channels_max = 2, 722 .rate_min = 8000, 723 .rate_max = 192000, 724 .rates = SNDRV_PCM_RATE_CONTINUOUS, 725 /* DMA does not support 24 bits transfers */ 726 .formats = 727 SNDRV_PCM_FMTBIT_S8 | 728 SNDRV_PCM_FMTBIT_S16_LE | 729 SNDRV_PCM_FMTBIT_S32_LE, 730 }, 731 .ops = &stm32_sai_pcm_dai_ops, 732 } 733 }; 734 735 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 736 .pcm_hardware = &stm32_sai_pcm_hw, 737 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 738 }; 739 740 static const struct snd_soc_component_driver stm32_component = { 741 .name = "stm32-sai", 742 }; 743 744 static const struct of_device_id stm32_sai_sub_ids[] = { 745 { .compatible = "st,stm32-sai-sub-a", 746 .data = (void *)STM_SAI_A_ID}, 747 { .compatible = "st,stm32-sai-sub-b", 748 .data = (void *)STM_SAI_B_ID}, 749 {} 750 }; 751 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 752 753 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 754 struct stm32_sai_sub_data *sai) 755 { 756 struct device_node *np = pdev->dev.of_node; 757 struct resource *res; 758 void __iomem *base; 759 760 if (!np) 761 return -ENODEV; 762 763 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 764 765 dev_err(&pdev->dev, "res %pr\n", res); 766 767 base = devm_ioremap_resource(&pdev->dev, res); 768 if (IS_ERR(base)) 769 return PTR_ERR(base); 770 771 sai->phys_addr = res->start; 772 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, 773 &stm32_sai_sub_regmap_config); 774 775 /* Get direction property */ 776 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 777 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 778 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 779 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 780 } else { 781 dev_err(&pdev->dev, "Unsupported direction\n"); 782 return -EINVAL; 783 } 784 785 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 786 if (IS_ERR(sai->sai_ck)) { 787 dev_err(&pdev->dev, "missing kernel clock sai_ck\n"); 788 return PTR_ERR(sai->sai_ck); 789 } 790 791 return 0; 792 } 793 794 static int stm32_sai_sub_dais_init(struct platform_device *pdev, 795 struct stm32_sai_sub_data *sai) 796 { 797 sai->cpu_dai_drv = devm_kzalloc(&pdev->dev, 798 sizeof(struct snd_soc_dai_driver), 799 GFP_KERNEL); 800 if (!sai->cpu_dai_drv) 801 return -ENOMEM; 802 803 sai->cpu_dai_drv->name = dev_name(&pdev->dev); 804 if (STM_SAI_IS_PLAYBACK(sai)) { 805 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai, 806 sizeof(stm32_sai_playback_dai)); 807 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name; 808 } else { 809 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai, 810 sizeof(stm32_sai_capture_dai)); 811 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name; 812 } 813 814 return 0; 815 } 816 817 static int stm32_sai_sub_probe(struct platform_device *pdev) 818 { 819 struct stm32_sai_sub_data *sai; 820 const struct of_device_id *of_id; 821 int ret; 822 823 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 824 if (!sai) 825 return -ENOMEM; 826 827 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 828 if (!of_id) 829 return -EINVAL; 830 sai->id = (uintptr_t)of_id->data; 831 832 sai->pdev = pdev; 833 platform_set_drvdata(pdev, sai); 834 835 sai->pdata = dev_get_drvdata(pdev->dev.parent); 836 if (!sai->pdata) { 837 dev_err(&pdev->dev, "Parent device data not available\n"); 838 return -EINVAL; 839 } 840 841 ret = stm32_sai_sub_parse_of(pdev, sai); 842 if (ret) 843 return ret; 844 845 ret = stm32_sai_sub_dais_init(pdev, sai); 846 if (ret) 847 return ret; 848 849 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 850 IRQF_SHARED, dev_name(&pdev->dev), sai); 851 if (ret) { 852 dev_err(&pdev->dev, "irq request returned %d\n", ret); 853 return ret; 854 } 855 856 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 857 sai->cpu_dai_drv, 1); 858 if (ret) 859 return ret; 860 861 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, 862 &stm32_sai_pcm_config, 0); 863 if (ret) { 864 dev_err(&pdev->dev, "could not register pcm dma\n"); 865 return ret; 866 } 867 868 return 0; 869 } 870 871 static struct platform_driver stm32_sai_sub_driver = { 872 .driver = { 873 .name = "st,stm32-sai-sub", 874 .of_match_table = stm32_sai_sub_ids, 875 }, 876 .probe = stm32_sai_sub_probe, 877 }; 878 879 module_platform_driver(stm32_sai_sub_driver); 880 881 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 882 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 883 MODULE_ALIAS("platform:st,stm32-sai-sub"); 884 MODULE_LICENSE("GPL v2"); 885