1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clk-provider.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/regmap.h> 26 27 #include <sound/asoundef.h> 28 #include <sound/core.h> 29 #include <sound/dmaengine_pcm.h> 30 #include <sound/pcm_params.h> 31 32 #include "stm32_sai.h" 33 34 #define SAI_FREE_PROTOCOL 0x0 35 #define SAI_SPDIF_PROTOCOL 0x1 36 37 #define SAI_SLOT_SIZE_AUTO 0x0 38 #define SAI_SLOT_SIZE_16 0x1 39 #define SAI_SLOT_SIZE_32 0x2 40 41 #define SAI_DATASIZE_8 0x2 42 #define SAI_DATASIZE_10 0x3 43 #define SAI_DATASIZE_16 0x4 44 #define SAI_DATASIZE_20 0x5 45 #define SAI_DATASIZE_24 0x6 46 #define SAI_DATASIZE_32 0x7 47 48 #define STM_SAI_FIFO_SIZE 8 49 #define STM_SAI_DAI_NAME_SIZE 15 50 51 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 52 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 53 54 #define STM_SAI_A_ID 0x0 55 #define STM_SAI_B_ID 0x1 56 57 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 58 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 59 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 60 61 #define SAI_SYNC_NONE 0x0 62 #define SAI_SYNC_INTERNAL 0x1 63 #define SAI_SYNC_EXTERNAL 0x2 64 65 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 66 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf->has_spdif) 67 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 68 69 #define SAI_IEC60958_BLOCK_FRAMES 192 70 #define SAI_IEC60958_STATUS_BYTES 24 71 72 #define SAI_MCLK_NAME_LEN 32 73 #define SAI_RATE_11K 11025 74 75 /** 76 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 77 * @pdev: device data pointer 78 * @regmap: SAI register map pointer 79 * @regmap_config: SAI sub block register map configuration pointer 80 * @dma_params: dma configuration data for rx or tx channel 81 * @cpu_dai_drv: DAI driver data pointer 82 * @cpu_dai: DAI runtime data pointer 83 * @substream: PCM substream data pointer 84 * @pdata: SAI block parent data pointer 85 * @np_sync_provider: synchronization provider node 86 * @sai_ck: kernel clock feeding the SAI clock generator 87 * @sai_mclk: master clock from SAI mclk provider 88 * @phys_addr: SAI registers physical base address 89 * @mclk_rate: SAI block master clock frequency (Hz). set at init 90 * @id: SAI sub block id corresponding to sub-block A or B 91 * @dir: SAI block direction (playback or capture). set at init 92 * @master: SAI block mode flag. (true=master, false=slave) set at init 93 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 94 * @fmt: SAI block format. relevant only for custom protocols. set at init 95 * @sync: SAI block synchronization mode. (none, internal or external) 96 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 97 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 98 * @fs_length: frame synchronization length. depends on protocol settings 99 * @slots: rx or tx slot number 100 * @slot_width: rx or tx slot width in bits 101 * @slot_mask: rx or tx active slots mask. set at init or at runtime 102 * @data_size: PCM data width. corresponds to PCM substream width. 103 * @spdif_frm_cnt: S/PDIF playback frame counter 104 * @iec958: iec958 data 105 * @ctrl_lock: control lock 106 * @irq_lock: prevent race condition with IRQ 107 */ 108 struct stm32_sai_sub_data { 109 struct platform_device *pdev; 110 struct regmap *regmap; 111 const struct regmap_config *regmap_config; 112 struct snd_dmaengine_dai_dma_data dma_params; 113 struct snd_soc_dai_driver *cpu_dai_drv; 114 struct snd_soc_dai *cpu_dai; 115 struct snd_pcm_substream *substream; 116 struct stm32_sai_data *pdata; 117 struct device_node *np_sync_provider; 118 struct clk *sai_ck; 119 struct clk *sai_mclk; 120 dma_addr_t phys_addr; 121 unsigned int mclk_rate; 122 unsigned int id; 123 int dir; 124 bool master; 125 bool spdif; 126 int fmt; 127 int sync; 128 int synco; 129 int synci; 130 int fs_length; 131 int slots; 132 int slot_width; 133 int slot_mask; 134 int data_size; 135 unsigned int spdif_frm_cnt; 136 struct snd_aes_iec958 iec958; 137 struct mutex ctrl_lock; /* protect resources accessed by controls */ 138 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 139 }; 140 141 enum stm32_sai_fifo_th { 142 STM_SAI_FIFO_TH_EMPTY, 143 STM_SAI_FIFO_TH_QUARTER, 144 STM_SAI_FIFO_TH_HALF, 145 STM_SAI_FIFO_TH_3_QUARTER, 146 STM_SAI_FIFO_TH_FULL, 147 }; 148 149 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 150 { 151 switch (reg) { 152 case STM_SAI_CR1_REGX: 153 case STM_SAI_CR2_REGX: 154 case STM_SAI_FRCR_REGX: 155 case STM_SAI_SLOTR_REGX: 156 case STM_SAI_IMR_REGX: 157 case STM_SAI_SR_REGX: 158 case STM_SAI_CLRFR_REGX: 159 case STM_SAI_DR_REGX: 160 case STM_SAI_PDMCR_REGX: 161 case STM_SAI_PDMLY_REGX: 162 return true; 163 default: 164 return false; 165 } 166 } 167 168 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 169 { 170 switch (reg) { 171 case STM_SAI_DR_REGX: 172 return true; 173 default: 174 return false; 175 } 176 } 177 178 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 179 { 180 switch (reg) { 181 case STM_SAI_CR1_REGX: 182 case STM_SAI_CR2_REGX: 183 case STM_SAI_FRCR_REGX: 184 case STM_SAI_SLOTR_REGX: 185 case STM_SAI_IMR_REGX: 186 case STM_SAI_SR_REGX: 187 case STM_SAI_CLRFR_REGX: 188 case STM_SAI_DR_REGX: 189 case STM_SAI_PDMCR_REGX: 190 case STM_SAI_PDMLY_REGX: 191 return true; 192 default: 193 return false; 194 } 195 } 196 197 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 198 .reg_bits = 32, 199 .reg_stride = 4, 200 .val_bits = 32, 201 .max_register = STM_SAI_DR_REGX, 202 .readable_reg = stm32_sai_sub_readable_reg, 203 .volatile_reg = stm32_sai_sub_volatile_reg, 204 .writeable_reg = stm32_sai_sub_writeable_reg, 205 .fast_io = true, 206 }; 207 208 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 209 .reg_bits = 32, 210 .reg_stride = 4, 211 .val_bits = 32, 212 .max_register = STM_SAI_PDMLY_REGX, 213 .readable_reg = stm32_sai_sub_readable_reg, 214 .volatile_reg = stm32_sai_sub_volatile_reg, 215 .writeable_reg = stm32_sai_sub_writeable_reg, 216 .fast_io = true, 217 }; 218 219 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 220 struct snd_ctl_elem_info *uinfo) 221 { 222 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 223 uinfo->count = 1; 224 225 return 0; 226 } 227 228 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 229 struct snd_ctl_elem_value *uctl) 230 { 231 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 232 233 mutex_lock(&sai->ctrl_lock); 234 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 235 mutex_unlock(&sai->ctrl_lock); 236 237 return 0; 238 } 239 240 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 241 struct snd_ctl_elem_value *uctl) 242 { 243 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 244 245 mutex_lock(&sai->ctrl_lock); 246 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 247 mutex_unlock(&sai->ctrl_lock); 248 249 return 0; 250 } 251 252 static const struct snd_kcontrol_new iec958_ctls = { 253 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 254 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 255 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 256 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 257 .info = snd_pcm_iec958_info, 258 .get = snd_pcm_iec958_get, 259 .put = snd_pcm_iec958_put, 260 }; 261 262 struct stm32_sai_mclk_data { 263 struct clk_hw hw; 264 unsigned long freq; 265 struct stm32_sai_sub_data *sai_data; 266 }; 267 268 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 269 #define STM32_SAI_MAX_CLKS 1 270 271 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 272 unsigned long input_rate, 273 unsigned long output_rate) 274 { 275 int version = sai->pdata->conf->version; 276 int div; 277 278 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 279 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 280 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 281 return -EINVAL; 282 } 283 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 284 285 if (input_rate % div) 286 dev_dbg(&sai->pdev->dev, 287 "Rate not accurate. requested (%ld), actual (%ld)\n", 288 output_rate, input_rate / div); 289 290 return div; 291 } 292 293 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 294 unsigned int div) 295 { 296 int version = sai->pdata->conf->version; 297 int ret, cr1, mask; 298 299 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 300 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 301 return -EINVAL; 302 } 303 304 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 305 cr1 = SAI_XCR1_MCKDIV_SET(div); 306 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); 307 if (ret < 0) 308 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 309 310 return ret; 311 } 312 313 static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai, 314 unsigned int rate) 315 { 316 struct platform_device *pdev = sai->pdev; 317 struct clk *parent_clk = sai->pdata->clk_x8k; 318 int ret; 319 320 if (!(rate % SAI_RATE_11K)) 321 parent_clk = sai->pdata->clk_x11k; 322 323 ret = clk_set_parent(sai->sai_ck, parent_clk); 324 if (ret) 325 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", 326 ret, ret == -EBUSY ? 327 "Active stream rates conflict\n" : "\n"); 328 329 return ret; 330 } 331 332 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 333 unsigned long *prate) 334 { 335 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 336 struct stm32_sai_sub_data *sai = mclk->sai_data; 337 int div; 338 339 div = stm32_sai_get_clk_div(sai, *prate, rate); 340 if (div < 0) 341 return div; 342 343 mclk->freq = *prate / div; 344 345 return mclk->freq; 346 } 347 348 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 349 unsigned long parent_rate) 350 { 351 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 352 353 return mclk->freq; 354 } 355 356 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 357 unsigned long parent_rate) 358 { 359 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 360 struct stm32_sai_sub_data *sai = mclk->sai_data; 361 int div, ret; 362 363 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 364 if (div < 0) 365 return div; 366 367 ret = stm32_sai_set_clk_div(sai, div); 368 if (ret) 369 return ret; 370 371 mclk->freq = rate; 372 373 return 0; 374 } 375 376 static int stm32_sai_mclk_enable(struct clk_hw *hw) 377 { 378 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 379 struct stm32_sai_sub_data *sai = mclk->sai_data; 380 381 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 382 383 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 384 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 385 } 386 387 static void stm32_sai_mclk_disable(struct clk_hw *hw) 388 { 389 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 390 struct stm32_sai_sub_data *sai = mclk->sai_data; 391 392 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 393 394 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 395 } 396 397 static const struct clk_ops mclk_ops = { 398 .enable = stm32_sai_mclk_enable, 399 .disable = stm32_sai_mclk_disable, 400 .recalc_rate = stm32_sai_mclk_recalc_rate, 401 .round_rate = stm32_sai_mclk_round_rate, 402 .set_rate = stm32_sai_mclk_set_rate, 403 }; 404 405 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 406 { 407 struct clk_hw *hw; 408 struct stm32_sai_mclk_data *mclk; 409 struct device *dev = &sai->pdev->dev; 410 const char *pname = __clk_get_name(sai->sai_ck); 411 char *mclk_name, *p, *s = (char *)pname; 412 int ret, i = 0; 413 414 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 415 if (!mclk) 416 return -ENOMEM; 417 418 mclk_name = devm_kcalloc(dev, sizeof(char), 419 SAI_MCLK_NAME_LEN, GFP_KERNEL); 420 if (!mclk_name) 421 return -ENOMEM; 422 423 /* 424 * Forge mclk clock name from parent clock name and suffix. 425 * String after "_" char is stripped in parent name. 426 */ 427 p = mclk_name; 428 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 429 *p++ = *s++; 430 i++; 431 } 432 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 433 434 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 435 mclk->sai_data = sai; 436 hw = &mclk->hw; 437 438 dev_dbg(dev, "Register master clock %s\n", mclk_name); 439 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 440 if (ret) { 441 dev_err(dev, "mclk register returned %d\n", ret); 442 return ret; 443 } 444 sai->sai_mclk = hw->clk; 445 446 /* register mclk provider */ 447 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 448 } 449 450 static irqreturn_t stm32_sai_isr(int irq, void *devid) 451 { 452 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 453 struct platform_device *pdev = sai->pdev; 454 unsigned int sr, imr, flags; 455 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 456 457 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); 458 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); 459 460 flags = sr & imr; 461 if (!flags) 462 return IRQ_NONE; 463 464 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 465 SAI_XCLRFR_MASK); 466 467 if (!sai->substream) { 468 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 469 return IRQ_NONE; 470 } 471 472 if (flags & SAI_XIMR_OVRUDRIE) { 473 dev_err(&pdev->dev, "IRQ %s\n", 474 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 475 status = SNDRV_PCM_STATE_XRUN; 476 } 477 478 if (flags & SAI_XIMR_MUTEDETIE) 479 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 480 481 if (flags & SAI_XIMR_WCKCFGIE) { 482 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 483 status = SNDRV_PCM_STATE_DISCONNECTED; 484 } 485 486 if (flags & SAI_XIMR_CNRDYIE) 487 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 488 489 if (flags & SAI_XIMR_AFSDETIE) { 490 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 491 status = SNDRV_PCM_STATE_XRUN; 492 } 493 494 if (flags & SAI_XIMR_LFSDETIE) { 495 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 496 status = SNDRV_PCM_STATE_XRUN; 497 } 498 499 spin_lock(&sai->irq_lock); 500 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) 501 snd_pcm_stop_xrun(sai->substream); 502 spin_unlock(&sai->irq_lock); 503 504 return IRQ_HANDLED; 505 } 506 507 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 508 int clk_id, unsigned int freq, int dir) 509 { 510 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 511 int ret; 512 513 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { 514 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 515 SAI_XCR1_NODIV, 516 (unsigned int)~SAI_XCR1_NODIV); 517 if (ret < 0) 518 return ret; 519 520 /* If master clock is used, set parent clock now */ 521 ret = stm32_sai_set_parent_clock(sai, freq); 522 if (ret) 523 return ret; 524 525 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); 526 if (ret) { 527 dev_err(cpu_dai->dev, 528 ret == -EBUSY ? 529 "Active streams have incompatible rates" : 530 "Could not set mclk rate\n"); 531 return ret; 532 } 533 534 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 535 sai->mclk_rate = freq; 536 } 537 538 return 0; 539 } 540 541 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 542 u32 rx_mask, int slots, int slot_width) 543 { 544 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 545 int slotr, slotr_mask, slot_size; 546 547 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 548 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 549 return 0; 550 } 551 552 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 553 tx_mask, rx_mask, slots, slot_width); 554 555 switch (slot_width) { 556 case 16: 557 slot_size = SAI_SLOT_SIZE_16; 558 break; 559 case 32: 560 slot_size = SAI_SLOT_SIZE_32; 561 break; 562 default: 563 slot_size = SAI_SLOT_SIZE_AUTO; 564 break; 565 } 566 567 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 568 SAI_XSLOTR_NBSLOT_SET(slots - 1); 569 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 570 571 /* tx/rx mask set in machine init, if slot number defined in DT */ 572 if (STM_SAI_IS_PLAYBACK(sai)) { 573 sai->slot_mask = tx_mask; 574 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 575 } 576 577 if (STM_SAI_IS_CAPTURE(sai)) { 578 sai->slot_mask = rx_mask; 579 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 580 } 581 582 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 583 584 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 585 586 sai->slot_width = slot_width; 587 sai->slots = slots; 588 589 return 0; 590 } 591 592 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 593 { 594 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 595 int cr1, frcr = 0; 596 int cr1_mask, frcr_mask = 0; 597 int ret; 598 599 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 600 601 /* Do not generate master by default */ 602 cr1 = SAI_XCR1_NODIV; 603 cr1_mask = SAI_XCR1_NODIV; 604 605 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 606 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 607 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 608 goto conf_update; 609 } 610 611 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 612 613 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 614 /* SCK active high for all protocols */ 615 case SND_SOC_DAIFMT_I2S: 616 cr1 |= SAI_XCR1_CKSTR; 617 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 618 break; 619 /* Left justified */ 620 case SND_SOC_DAIFMT_MSB: 621 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 622 break; 623 /* Right justified */ 624 case SND_SOC_DAIFMT_LSB: 625 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 626 break; 627 case SND_SOC_DAIFMT_DSP_A: 628 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 629 break; 630 case SND_SOC_DAIFMT_DSP_B: 631 frcr |= SAI_XFRCR_FSPOL; 632 break; 633 default: 634 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 635 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 636 return -EINVAL; 637 } 638 639 cr1_mask |= SAI_XCR1_CKSTR; 640 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 641 SAI_XFRCR_FSDEF; 642 643 /* DAI clock strobing. Invert setting previously set */ 644 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 645 case SND_SOC_DAIFMT_NB_NF: 646 break; 647 case SND_SOC_DAIFMT_IB_NF: 648 cr1 ^= SAI_XCR1_CKSTR; 649 break; 650 case SND_SOC_DAIFMT_NB_IF: 651 frcr ^= SAI_XFRCR_FSPOL; 652 break; 653 case SND_SOC_DAIFMT_IB_IF: 654 /* Invert fs & sck */ 655 cr1 ^= SAI_XCR1_CKSTR; 656 frcr ^= SAI_XFRCR_FSPOL; 657 break; 658 default: 659 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 660 fmt & SND_SOC_DAIFMT_INV_MASK); 661 return -EINVAL; 662 } 663 cr1_mask |= SAI_XCR1_CKSTR; 664 frcr_mask |= SAI_XFRCR_FSPOL; 665 666 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 667 668 /* DAI clock master masks */ 669 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 670 case SND_SOC_DAIFMT_CBM_CFM: 671 /* codec is master */ 672 cr1 |= SAI_XCR1_SLAVE; 673 sai->master = false; 674 break; 675 case SND_SOC_DAIFMT_CBS_CFS: 676 sai->master = true; 677 break; 678 default: 679 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 680 fmt & SND_SOC_DAIFMT_MASTER_MASK); 681 return -EINVAL; 682 } 683 684 /* Set slave mode if sub-block is synchronized with another SAI */ 685 if (sai->sync) { 686 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 687 cr1 |= SAI_XCR1_SLAVE; 688 sai->master = false; 689 } 690 691 cr1_mask |= SAI_XCR1_SLAVE; 692 693 conf_update: 694 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 695 if (ret < 0) { 696 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 697 return ret; 698 } 699 700 sai->fmt = fmt; 701 702 return 0; 703 } 704 705 static int stm32_sai_startup(struct snd_pcm_substream *substream, 706 struct snd_soc_dai *cpu_dai) 707 { 708 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 709 int imr, cr2, ret; 710 unsigned long flags; 711 712 spin_lock_irqsave(&sai->irq_lock, flags); 713 sai->substream = substream; 714 spin_unlock_irqrestore(&sai->irq_lock, flags); 715 716 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 717 snd_pcm_hw_constraint_mask64(substream->runtime, 718 SNDRV_PCM_HW_PARAM_FORMAT, 719 SNDRV_PCM_FMTBIT_S32_LE); 720 snd_pcm_hw_constraint_single(substream->runtime, 721 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 722 } 723 724 ret = clk_prepare_enable(sai->sai_ck); 725 if (ret < 0) { 726 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 727 return ret; 728 } 729 730 /* Enable ITs */ 731 732 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, 733 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 734 735 imr = SAI_XIMR_OVRUDRIE; 736 if (STM_SAI_IS_CAPTURE(sai)) { 737 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); 738 if (cr2 & SAI_XCR2_MUTECNT_MASK) 739 imr |= SAI_XIMR_MUTEDETIE; 740 } 741 742 if (sai->master) 743 imr |= SAI_XIMR_WCKCFGIE; 744 else 745 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 746 747 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 748 SAI_XIMR_MASK, imr); 749 750 return 0; 751 } 752 753 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 754 struct snd_pcm_substream *substream, 755 struct snd_pcm_hw_params *params) 756 { 757 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 758 int cr1, cr1_mask, ret; 759 760 /* 761 * DMA bursts increment is set to 4 words. 762 * SAI fifo threshold is set to half fifo, to keep enough space 763 * for DMA incoming bursts. 764 */ 765 regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX, 766 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 767 SAI_XCR2_FFLUSH | 768 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 769 770 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 771 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 772 sai->spdif_frm_cnt = 0; 773 return 0; 774 } 775 776 /* Mode, data format and channel config */ 777 cr1_mask = SAI_XCR1_DS_MASK; 778 switch (params_format(params)) { 779 case SNDRV_PCM_FORMAT_S8: 780 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 781 break; 782 case SNDRV_PCM_FORMAT_S16_LE: 783 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 784 break; 785 case SNDRV_PCM_FORMAT_S32_LE: 786 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 787 break; 788 default: 789 dev_err(cpu_dai->dev, "Data format not supported"); 790 return -EINVAL; 791 } 792 793 cr1_mask |= SAI_XCR1_MONO; 794 if ((sai->slots == 2) && (params_channels(params) == 1)) 795 cr1 |= SAI_XCR1_MONO; 796 797 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 798 if (ret < 0) { 799 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 800 return ret; 801 } 802 803 return 0; 804 } 805 806 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 807 { 808 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 809 int slotr, slot_sz; 810 811 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); 812 813 /* 814 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 815 * By default slot width = data size, if not forced from DT 816 */ 817 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 818 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 819 sai->slot_width = sai->data_size; 820 821 if (sai->slot_width < sai->data_size) { 822 dev_err(cpu_dai->dev, 823 "Data size %d larger than slot width\n", 824 sai->data_size); 825 return -EINVAL; 826 } 827 828 /* Slot number is set to 2, if not specified in DT */ 829 if (!sai->slots) 830 sai->slots = 2; 831 832 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 833 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 834 SAI_XSLOTR_NBSLOT_MASK, 835 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 836 837 /* Set default slots mask if not already set from DT */ 838 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 839 sai->slot_mask = (1 << sai->slots) - 1; 840 regmap_update_bits(sai->regmap, 841 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 842 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 843 } 844 845 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 846 sai->slots, sai->slot_width); 847 848 return 0; 849 } 850 851 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 852 { 853 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 854 int fs_active, offset, format; 855 int frcr, frcr_mask; 856 857 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 858 sai->fs_length = sai->slot_width * sai->slots; 859 860 fs_active = sai->fs_length / 2; 861 if ((format == SND_SOC_DAIFMT_DSP_A) || 862 (format == SND_SOC_DAIFMT_DSP_B)) 863 fs_active = 1; 864 865 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 866 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 867 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 868 869 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 870 sai->fs_length, fs_active); 871 872 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); 873 874 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 875 offset = sai->slot_width - sai->data_size; 876 877 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, 878 SAI_XSLOTR_FBOFF_MASK, 879 SAI_XSLOTR_FBOFF_SET(offset)); 880 } 881 } 882 883 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 884 { 885 unsigned char *cs = sai->iec958.status; 886 887 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 888 cs[1] = IEC958_AES1_CON_GENERAL; 889 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 890 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 891 } 892 893 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 894 struct snd_pcm_runtime *runtime) 895 { 896 if (!runtime) 897 return; 898 899 /* Force the sample rate according to runtime rate */ 900 mutex_lock(&sai->ctrl_lock); 901 switch (runtime->rate) { 902 case 22050: 903 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 904 break; 905 case 44100: 906 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 907 break; 908 case 88200: 909 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 910 break; 911 case 176400: 912 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 913 break; 914 case 24000: 915 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 916 break; 917 case 48000: 918 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 919 break; 920 case 96000: 921 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 922 break; 923 case 192000: 924 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 925 break; 926 case 32000: 927 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 928 break; 929 default: 930 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 931 break; 932 } 933 mutex_unlock(&sai->ctrl_lock); 934 } 935 936 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 937 struct snd_pcm_hw_params *params) 938 { 939 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 940 int div = 0, cr1 = 0; 941 int sai_clk_rate, mclk_ratio, den; 942 unsigned int rate = params_rate(params); 943 int ret; 944 945 if (!sai->sai_mclk) { 946 ret = stm32_sai_set_parent_clock(sai, rate); 947 if (ret) 948 return ret; 949 } 950 sai_clk_rate = clk_get_rate(sai->sai_ck); 951 952 if (STM_SAI_IS_F4(sai->pdata)) { 953 /* mclk on (NODIV=0) 954 * mclk_rate = 256 * fs 955 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 956 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 957 * mclk off (NODIV=1) 958 * MCKDIV ignored. sck = sai_ck 959 */ 960 if (!sai->mclk_rate) 961 return 0; 962 963 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 964 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 965 2 * sai->mclk_rate); 966 if (div < 0) 967 return div; 968 } 969 } else { 970 /* 971 * TDM mode : 972 * mclk on 973 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 974 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 975 * mclk off 976 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 977 * Note: NOMCK/NODIV correspond to same bit. 978 */ 979 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 980 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 981 rate * 128); 982 if (div < 0) 983 return div; 984 } else { 985 if (sai->mclk_rate) { 986 mclk_ratio = sai->mclk_rate / rate; 987 if (mclk_ratio == 512) { 988 cr1 = SAI_XCR1_OSR; 989 } else if (mclk_ratio != 256) { 990 dev_err(cpu_dai->dev, 991 "Wrong mclk ratio %d\n", 992 mclk_ratio); 993 return -EINVAL; 994 } 995 996 regmap_update_bits(sai->regmap, 997 STM_SAI_CR1_REGX, 998 SAI_XCR1_OSR, cr1); 999 1000 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1001 sai->mclk_rate); 1002 if (div < 0) 1003 return div; 1004 } else { 1005 /* mclk-fs not set, master clock not active */ 1006 den = sai->fs_length * params_rate(params); 1007 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1008 den); 1009 if (div < 0) 1010 return div; 1011 } 1012 } 1013 } 1014 1015 return stm32_sai_set_clk_div(sai, div); 1016 } 1017 1018 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 1019 struct snd_pcm_hw_params *params, 1020 struct snd_soc_dai *cpu_dai) 1021 { 1022 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1023 int ret; 1024 1025 sai->data_size = params_width(params); 1026 1027 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1028 /* Rate not already set in runtime structure */ 1029 substream->runtime->rate = params_rate(params); 1030 stm32_sai_set_iec958_status(sai, substream->runtime); 1031 } else { 1032 ret = stm32_sai_set_slots(cpu_dai); 1033 if (ret < 0) 1034 return ret; 1035 stm32_sai_set_frame(cpu_dai); 1036 } 1037 1038 ret = stm32_sai_set_config(cpu_dai, substream, params); 1039 if (ret) 1040 return ret; 1041 1042 if (sai->master) 1043 ret = stm32_sai_configure_clock(cpu_dai, params); 1044 1045 return ret; 1046 } 1047 1048 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 1049 struct snd_soc_dai *cpu_dai) 1050 { 1051 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1052 int ret; 1053 1054 switch (cmd) { 1055 case SNDRV_PCM_TRIGGER_START: 1056 case SNDRV_PCM_TRIGGER_RESUME: 1057 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1058 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 1059 1060 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1061 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 1062 1063 /* Enable SAI */ 1064 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1065 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 1066 if (ret < 0) 1067 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1068 break; 1069 case SNDRV_PCM_TRIGGER_SUSPEND: 1070 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1071 case SNDRV_PCM_TRIGGER_STOP: 1072 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 1073 1074 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, 1075 SAI_XIMR_MASK, 0); 1076 1077 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1078 SAI_XCR1_SAIEN, 1079 (unsigned int)~SAI_XCR1_SAIEN); 1080 1081 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, 1082 SAI_XCR1_DMAEN, 1083 (unsigned int)~SAI_XCR1_DMAEN); 1084 if (ret < 0) 1085 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1086 1087 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1088 sai->spdif_frm_cnt = 0; 1089 break; 1090 default: 1091 return -EINVAL; 1092 } 1093 1094 return ret; 1095 } 1096 1097 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 1098 struct snd_soc_dai *cpu_dai) 1099 { 1100 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1101 unsigned long flags; 1102 1103 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 1104 1105 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV, 1106 SAI_XCR1_NODIV); 1107 1108 /* Release mclk rate only if rate was actually set */ 1109 if (sai->mclk_rate) { 1110 clk_rate_exclusive_put(sai->sai_mclk); 1111 sai->mclk_rate = 0; 1112 } 1113 1114 clk_disable_unprepare(sai->sai_ck); 1115 1116 spin_lock_irqsave(&sai->irq_lock, flags); 1117 sai->substream = NULL; 1118 spin_unlock_irqrestore(&sai->irq_lock, flags); 1119 } 1120 1121 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1122 struct snd_soc_dai *cpu_dai) 1123 { 1124 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1125 struct snd_kcontrol_new knew = iec958_ctls; 1126 1127 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1128 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 1129 knew.device = rtd->pcm->device; 1130 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1131 } 1132 1133 return 0; 1134 } 1135 1136 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 1137 { 1138 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1139 int cr1 = 0, cr1_mask, ret; 1140 1141 sai->cpu_dai = cpu_dai; 1142 1143 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1144 /* 1145 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1146 * as it allows bytes, half-word and words transfers. (See DMA fifos 1147 * constraints). 1148 */ 1149 sai->dma_params.maxburst = 4; 1150 /* Buswidth will be set by framework at runtime */ 1151 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1152 1153 if (STM_SAI_IS_PLAYBACK(sai)) 1154 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 1155 else 1156 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 1157 1158 /* Next settings are not relevant for spdif mode */ 1159 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1160 return 0; 1161 1162 cr1_mask = SAI_XCR1_RX_TX; 1163 if (STM_SAI_IS_CAPTURE(sai)) 1164 cr1 |= SAI_XCR1_RX_TX; 1165 1166 /* Configure synchronization */ 1167 if (sai->sync == SAI_SYNC_EXTERNAL) { 1168 /* Configure synchro client and provider */ 1169 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 1170 sai->synco, sai->synci); 1171 if (ret) 1172 return ret; 1173 } 1174 1175 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 1176 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 1177 1178 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); 1179 } 1180 1181 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 1182 .set_sysclk = stm32_sai_set_sysclk, 1183 .set_fmt = stm32_sai_set_dai_fmt, 1184 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1185 .startup = stm32_sai_startup, 1186 .hw_params = stm32_sai_hw_params, 1187 .trigger = stm32_sai_trigger, 1188 .shutdown = stm32_sai_shutdown, 1189 }; 1190 1191 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 1192 int channel, unsigned long hwoff, 1193 void *buf, unsigned long bytes) 1194 { 1195 struct snd_pcm_runtime *runtime = substream->runtime; 1196 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1197 struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 1198 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1199 int *ptr = (int *)(runtime->dma_area + hwoff + 1200 channel * (runtime->dma_bytes / runtime->channels)); 1201 ssize_t cnt = bytes_to_samples(runtime, bytes); 1202 unsigned int frm_cnt = sai->spdif_frm_cnt; 1203 unsigned int byte; 1204 unsigned int mask; 1205 1206 do { 1207 *ptr = ((*ptr >> 8) & 0x00ffffff); 1208 1209 /* Set channel status bit */ 1210 byte = frm_cnt >> 3; 1211 mask = 1 << (frm_cnt - (byte << 3)); 1212 if (sai->iec958.status[byte] & mask) 1213 *ptr |= 0x04000000; 1214 ptr++; 1215 1216 if (!(cnt % 2)) 1217 frm_cnt++; 1218 1219 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 1220 frm_cnt = 0; 1221 } while (--cnt); 1222 sai->spdif_frm_cnt = frm_cnt; 1223 1224 return 0; 1225 } 1226 1227 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 1228 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 1229 .buffer_bytes_max = 8 * PAGE_SIZE, 1230 .period_bytes_min = 1024, /* 5ms at 48kHz */ 1231 .period_bytes_max = PAGE_SIZE, 1232 .periods_min = 2, 1233 .periods_max = 8, 1234 }; 1235 1236 static struct snd_soc_dai_driver stm32_sai_playback_dai[] = { 1237 { 1238 .probe = stm32_sai_dai_probe, 1239 .pcm_new = stm32_sai_pcm_new, 1240 .id = 1, /* avoid call to fmt_single_name() */ 1241 .playback = { 1242 .channels_min = 1, 1243 .channels_max = 2, 1244 .rate_min = 8000, 1245 .rate_max = 192000, 1246 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1247 /* DMA does not support 24 bits transfers */ 1248 .formats = 1249 SNDRV_PCM_FMTBIT_S8 | 1250 SNDRV_PCM_FMTBIT_S16_LE | 1251 SNDRV_PCM_FMTBIT_S32_LE, 1252 }, 1253 .ops = &stm32_sai_pcm_dai_ops, 1254 } 1255 }; 1256 1257 static struct snd_soc_dai_driver stm32_sai_capture_dai[] = { 1258 { 1259 .probe = stm32_sai_dai_probe, 1260 .id = 1, /* avoid call to fmt_single_name() */ 1261 .capture = { 1262 .channels_min = 1, 1263 .channels_max = 2, 1264 .rate_min = 8000, 1265 .rate_max = 192000, 1266 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1267 /* DMA does not support 24 bits transfers */ 1268 .formats = 1269 SNDRV_PCM_FMTBIT_S8 | 1270 SNDRV_PCM_FMTBIT_S16_LE | 1271 SNDRV_PCM_FMTBIT_S32_LE, 1272 }, 1273 .ops = &stm32_sai_pcm_dai_ops, 1274 } 1275 }; 1276 1277 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 1278 .pcm_hardware = &stm32_sai_pcm_hw, 1279 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1280 }; 1281 1282 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 1283 .pcm_hardware = &stm32_sai_pcm_hw, 1284 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1285 .process = stm32_sai_pcm_process_spdif, 1286 }; 1287 1288 static const struct snd_soc_component_driver stm32_component = { 1289 .name = "stm32-sai", 1290 }; 1291 1292 static const struct of_device_id stm32_sai_sub_ids[] = { 1293 { .compatible = "st,stm32-sai-sub-a", 1294 .data = (void *)STM_SAI_A_ID}, 1295 { .compatible = "st,stm32-sai-sub-b", 1296 .data = (void *)STM_SAI_B_ID}, 1297 {} 1298 }; 1299 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 1300 1301 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 1302 struct stm32_sai_sub_data *sai) 1303 { 1304 struct device_node *np = pdev->dev.of_node; 1305 struct resource *res; 1306 void __iomem *base; 1307 struct of_phandle_args args; 1308 int ret; 1309 1310 if (!np) 1311 return -ENODEV; 1312 1313 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1314 base = devm_ioremap_resource(&pdev->dev, res); 1315 if (IS_ERR(base)) 1316 return PTR_ERR(base); 1317 1318 sai->phys_addr = res->start; 1319 1320 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 1321 /* Note: PDM registers not available for H7 sub-block B */ 1322 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai)) 1323 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 1324 1325 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", 1326 base, sai->regmap_config); 1327 if (IS_ERR(sai->regmap)) { 1328 dev_err(&pdev->dev, "Failed to initialize MMIO\n"); 1329 return PTR_ERR(sai->regmap); 1330 } 1331 1332 /* Get direction property */ 1333 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 1334 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 1335 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 1336 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 1337 } else { 1338 dev_err(&pdev->dev, "Unsupported direction\n"); 1339 return -EINVAL; 1340 } 1341 1342 /* Get spdif iec60958 property */ 1343 sai->spdif = false; 1344 if (of_get_property(np, "st,iec60958", NULL)) { 1345 if (!STM_SAI_HAS_SPDIF(sai) || 1346 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 1347 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 1348 return -EINVAL; 1349 } 1350 stm32_sai_init_iec958_status(sai); 1351 sai->spdif = true; 1352 sai->master = true; 1353 } 1354 1355 /* Get synchronization property */ 1356 args.np = NULL; 1357 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1358 if (ret < 0 && ret != -ENOENT) { 1359 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1360 return ret; 1361 } 1362 1363 sai->sync = SAI_SYNC_NONE; 1364 if (args.np) { 1365 if (args.np == np) { 1366 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 1367 of_node_put(args.np); 1368 return -EINVAL; 1369 } 1370 1371 sai->np_sync_provider = of_get_parent(args.np); 1372 if (!sai->np_sync_provider) { 1373 dev_err(&pdev->dev, "%pOFn parent node not found\n", 1374 np); 1375 of_node_put(args.np); 1376 return -ENODEV; 1377 } 1378 1379 sai->sync = SAI_SYNC_INTERNAL; 1380 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1381 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1382 dev_err(&pdev->dev, 1383 "External synchro not supported\n"); 1384 of_node_put(args.np); 1385 return -EINVAL; 1386 } 1387 sai->sync = SAI_SYNC_EXTERNAL; 1388 1389 sai->synci = args.args[0]; 1390 if (sai->synci < 1 || 1391 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1392 dev_err(&pdev->dev, "Wrong SAI index\n"); 1393 of_node_put(args.np); 1394 return -EINVAL; 1395 } 1396 1397 if (of_property_match_string(args.np, "compatible", 1398 "st,stm32-sai-sub-a") >= 0) 1399 sai->synco = STM_SAI_SYNC_OUT_A; 1400 1401 if (of_property_match_string(args.np, "compatible", 1402 "st,stm32-sai-sub-b") >= 0) 1403 sai->synco = STM_SAI_SYNC_OUT_B; 1404 1405 if (!sai->synco) { 1406 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1407 of_node_put(args.np); 1408 return -EINVAL; 1409 } 1410 } 1411 1412 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1413 pdev->name, args.np->full_name); 1414 } 1415 1416 of_node_put(args.np); 1417 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1418 if (IS_ERR(sai->sai_ck)) { 1419 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n"); 1420 return PTR_ERR(sai->sai_ck); 1421 } 1422 1423 if (STM_SAI_IS_F4(sai->pdata)) 1424 return 0; 1425 1426 /* Register mclk provider if requested */ 1427 if (of_find_property(np, "#clock-cells", NULL)) { 1428 ret = stm32_sai_add_mclk_provider(sai); 1429 if (ret < 0) 1430 return ret; 1431 } else { 1432 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK"); 1433 if (IS_ERR(sai->sai_mclk)) { 1434 if (PTR_ERR(sai->sai_mclk) != -ENOENT) 1435 return PTR_ERR(sai->sai_mclk); 1436 sai->sai_mclk = NULL; 1437 } 1438 } 1439 1440 return 0; 1441 } 1442 1443 static int stm32_sai_sub_dais_init(struct platform_device *pdev, 1444 struct stm32_sai_sub_data *sai) 1445 { 1446 sai->cpu_dai_drv = devm_kzalloc(&pdev->dev, 1447 sizeof(struct snd_soc_dai_driver), 1448 GFP_KERNEL); 1449 if (!sai->cpu_dai_drv) 1450 return -ENOMEM; 1451 1452 if (STM_SAI_IS_PLAYBACK(sai)) { 1453 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai, 1454 sizeof(stm32_sai_playback_dai)); 1455 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name; 1456 } else { 1457 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai, 1458 sizeof(stm32_sai_capture_dai)); 1459 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name; 1460 } 1461 sai->cpu_dai_drv->name = dev_name(&pdev->dev); 1462 1463 return 0; 1464 } 1465 1466 static int stm32_sai_sub_probe(struct platform_device *pdev) 1467 { 1468 struct stm32_sai_sub_data *sai; 1469 const struct of_device_id *of_id; 1470 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1471 int ret; 1472 1473 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1474 if (!sai) 1475 return -ENOMEM; 1476 1477 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 1478 if (!of_id) 1479 return -EINVAL; 1480 sai->id = (uintptr_t)of_id->data; 1481 1482 sai->pdev = pdev; 1483 mutex_init(&sai->ctrl_lock); 1484 spin_lock_init(&sai->irq_lock); 1485 platform_set_drvdata(pdev, sai); 1486 1487 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1488 if (!sai->pdata) { 1489 dev_err(&pdev->dev, "Parent device data not available\n"); 1490 return -EINVAL; 1491 } 1492 1493 ret = stm32_sai_sub_parse_of(pdev, sai); 1494 if (ret) 1495 return ret; 1496 1497 ret = stm32_sai_sub_dais_init(pdev, sai); 1498 if (ret) 1499 return ret; 1500 1501 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1502 IRQF_SHARED, dev_name(&pdev->dev), sai); 1503 if (ret) { 1504 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1505 return ret; 1506 } 1507 1508 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component, 1509 sai->cpu_dai_drv, 1); 1510 if (ret) 1511 return ret; 1512 1513 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1514 conf = &stm32_sai_pcm_config_spdif; 1515 1516 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1517 if (ret) { 1518 dev_err(&pdev->dev, "Could not register pcm dma\n"); 1519 return ret; 1520 } 1521 1522 return 0; 1523 } 1524 1525 static struct platform_driver stm32_sai_sub_driver = { 1526 .driver = { 1527 .name = "st,stm32-sai-sub", 1528 .of_match_table = stm32_sai_sub_ids, 1529 }, 1530 .probe = stm32_sai_sub_probe, 1531 }; 1532 1533 module_platform_driver(stm32_sai_sub_driver); 1534 1535 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1536 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1537 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1538 MODULE_LICENSE("GPL v2"); 1539