1 /* 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 3 * 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 6 * 7 * License terms: GPL V2.0. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 */ 18 19 /******************** SAI Register Map **************************************/ 20 21 /* common register */ 22 #define STM_SAI_GCR 0x00 23 24 /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */ 25 #define STM_SAI_CR1_REGX 0x00 /* A offset: 0x04. B offset: 0x24 */ 26 #define STM_SAI_CR2_REGX 0x04 27 #define STM_SAI_FRCR_REGX 0x08 28 #define STM_SAI_SLOTR_REGX 0x0C 29 #define STM_SAI_IMR_REGX 0x10 30 #define STM_SAI_SR_REGX 0x14 31 #define STM_SAI_CLRFR_REGX 0x18 32 #define STM_SAI_DR_REGX 0x1C 33 34 /* Sub-block A registers, relative to sub-block A address */ 35 #define STM_SAI_PDMCR_REGX 0x40 36 #define STM_SAI_PDMLY_REGX 0x44 37 38 /******************** Bit definition for SAI_GCR register *******************/ 39 #define SAI_GCR_SYNCIN_SHIFT 0 40 #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT) 41 #define SAI_GCR_SYNCIN_SET(x) ((x) << SAI_GCR_SYNCIN_SHIFT) 42 43 #define SAI_GCR_SYNCOUT_SHIFT 4 44 #define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT) 45 #define SAI_GCR_SYNCOUT_SET(x) ((x) << SAI_GCR_SYNCOUT_SHIFT) 46 47 /******************* Bit definition for SAI_XCR1 register *******************/ 48 #define SAI_XCR1_RX_TX_SHIFT 0 49 #define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT) 50 #define SAI_XCR1_SLAVE_SHIFT 1 51 #define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT) 52 53 #define SAI_XCR1_PRTCFG_SHIFT 2 54 #define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT) 55 #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT) 56 57 #define SAI_XCR1_DS_SHIFT 5 58 #define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT) 59 #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT) 60 61 #define SAI_XCR1_LSBFIRST_SHIFT 8 62 #define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT) 63 #define SAI_XCR1_CKSTR_SHIFT 9 64 #define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT) 65 66 #define SAI_XCR1_SYNCEN_SHIFT 10 67 #define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT) 68 #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT) 69 70 #define SAI_XCR1_MONO_SHIFT 12 71 #define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT) 72 #define SAI_XCR1_OUTDRIV_SHIFT 13 73 #define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT) 74 #define SAI_XCR1_SAIEN_SHIFT 16 75 #define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT) 76 #define SAI_XCR1_DMAEN_SHIFT 17 77 #define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT) 78 #define SAI_XCR1_NODIV_SHIFT 19 79 #define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT) 80 81 #define SAI_XCR1_MCKDIV_SHIFT 20 82 #define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == SAI_STM32F4) ? 4 : 6) 83 #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\ 84 SAI_XCR1_MCKDIV_SHIFT) 85 #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT) 86 #define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1) 87 88 #define SAI_XCR1_OSR_SHIFT 26 89 #define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT) 90 91 /******************* Bit definition for SAI_XCR2 register *******************/ 92 #define SAI_XCR2_FTH_SHIFT 0 93 #define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT) 94 #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT) 95 96 #define SAI_XCR2_FFLUSH_SHIFT 3 97 #define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT) 98 #define SAI_XCR2_TRIS_SHIFT 4 99 #define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT) 100 #define SAI_XCR2_MUTE_SHIFT 5 101 #define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT) 102 #define SAI_XCR2_MUTEVAL_SHIFT 6 103 #define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT) 104 105 #define SAI_XCR2_MUTECNT_SHIFT 7 106 #define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT) 107 #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT) 108 109 #define SAI_XCR2_CPL_SHIFT 13 110 #define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT) 111 112 #define SAI_XCR2_COMP_SHIFT 14 113 #define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT) 114 #define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT) 115 116 /****************** Bit definition for SAI_XFRCR register *******************/ 117 #define SAI_XFRCR_FRL_SHIFT 0 118 #define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT) 119 #define SAI_XFRCR_FRL_SET(x) ((x) << SAI_XFRCR_FRL_SHIFT) 120 121 #define SAI_XFRCR_FSALL_SHIFT 8 122 #define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT) 123 #define SAI_XFRCR_FSALL_SET(x) ((x) << SAI_XFRCR_FSALL_SHIFT) 124 125 #define SAI_XFRCR_FSDEF_SHIFT 16 126 #define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT) 127 #define SAI_XFRCR_FSPOL_SHIFT 17 128 #define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT) 129 #define SAI_XFRCR_FSOFF_SHIFT 18 130 #define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT) 131 132 /****************** Bit definition for SAI_XSLOTR register ******************/ 133 #define SAI_XSLOTR_FBOFF_SHIFT 0 134 #define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT) 135 #define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT) 136 137 #define SAI_XSLOTR_SLOTSZ_SHIFT 6 138 #define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT) 139 #define SAI_XSLOTR_SLOTSZ_SET(x) ((x) << SAI_XSLOTR_SLOTSZ_SHIFT) 140 141 #define SAI_XSLOTR_NBSLOT_SHIFT 8 142 #define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT) 143 #define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT) 144 145 #define SAI_XSLOTR_SLOTEN_SHIFT 16 146 #define SAI_XSLOTR_SLOTEN_WIDTH 16 147 #define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT) 148 #define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT) 149 150 /******************* Bit definition for SAI_XIMR register *******************/ 151 #define SAI_XIMR_OVRUDRIE BIT(0) 152 #define SAI_XIMR_MUTEDETIE BIT(1) 153 #define SAI_XIMR_WCKCFGIE BIT(2) 154 #define SAI_XIMR_FREQIE BIT(3) 155 #define SAI_XIMR_CNRDYIE BIT(4) 156 #define SAI_XIMR_AFSDETIE BIT(5) 157 #define SAI_XIMR_LFSDETIE BIT(6) 158 159 #define SAI_XIMR_SHIFT 0 160 #define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT) 161 162 /******************** Bit definition for SAI_XSR register *******************/ 163 #define SAI_XSR_OVRUDR BIT(0) 164 #define SAI_XSR_MUTEDET BIT(1) 165 #define SAI_XSR_WCKCFG BIT(2) 166 #define SAI_XSR_FREQ BIT(3) 167 #define SAI_XSR_CNRDY BIT(4) 168 #define SAI_XSR_AFSDET BIT(5) 169 #define SAI_XSR_LFSDET BIT(6) 170 171 #define SAI_XSR_SHIFT 0 172 #define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT) 173 174 /****************** Bit definition for SAI_XCLRFR register ******************/ 175 #define SAI_XCLRFR_COVRUDR BIT(0) 176 #define SAI_XCLRFR_CMUTEDET BIT(1) 177 #define SAI_XCLRFR_CWCKCFG BIT(2) 178 #define SAI_XCLRFR_CFREQ BIT(3) 179 #define SAI_XCLRFR_CCNRDY BIT(4) 180 #define SAI_XCLRFR_CAFSDET BIT(5) 181 #define SAI_XCLRFR_CLFSDET BIT(6) 182 183 #define SAI_XCLRFR_SHIFT 0 184 #define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT) 185 186 /****************** Bit definition for SAI_PDMCR register ******************/ 187 #define SAI_PDMCR_PDMEN BIT(0) 188 189 #define SAI_PDMCR_MICNBR_SHIFT 4 190 #define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT) 191 #define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT) 192 193 #define SAI_PDMCR_CKEN1 BIT(8) 194 #define SAI_PDMCR_CKEN2 BIT(9) 195 #define SAI_PDMCR_CKEN3 BIT(10) 196 #define SAI_PDMCR_CKEN4 BIT(11) 197 198 /****************** Bit definition for (SAI_PDMDLY register ****************/ 199 #define SAI_PDMDLY_1L_SHIFT 0 200 #define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT) 201 #define SAI_PDMDLY_1L_WIDTH 3 202 203 #define SAI_PDMDLY_1R_SHIFT 4 204 #define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT) 205 #define SAI_PDMDLY_1R_WIDTH 3 206 207 #define SAI_PDMDLY_2L_SHIFT 8 208 #define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT) 209 #define SAI_PDMDLY_2L_WIDTH 3 210 211 #define SAI_PDMDLY_2R_SHIFT 12 212 #define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT) 213 #define SAI_PDMDLY_2R_WIDTH 3 214 215 #define SAI_PDMDLY_3L_SHIFT 16 216 #define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT) 217 #define SAI_PDMDLY_3L_WIDTH 3 218 219 #define SAI_PDMDLY_3R_SHIFT 20 220 #define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT) 221 #define SAI_PDMDLY_3R_WIDTH 3 222 223 #define SAI_PDMDLY_4L_SHIFT 24 224 #define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT) 225 #define SAI_PDMDLY_4L_WIDTH 3 226 227 #define SAI_PDMDLY_4R_SHIFT 28 228 #define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT) 229 #define SAI_PDMDLY_4R_WIDTH 3 230 231 #define STM_SAI_IS_F4(ip) ((ip)->conf->version == SAI_STM32F4) 232 #define STM_SAI_IS_H7(ip) ((ip)->conf->version == SAI_STM32H7) 233 234 enum stm32_sai_version { 235 SAI_STM32F4, 236 SAI_STM32H7 237 }; 238 239 /** 240 * struct stm32_sai_conf - SAI configuration 241 * @version: SAI version 242 */ 243 struct stm32_sai_conf { 244 int version; 245 }; 246 247 /** 248 * struct stm32_sai_data - private data of SAI instance driver 249 * @pdev: device data pointer 250 * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz 251 * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz 252 * @version: SOC version 253 * @irq: SAI interrupt line 254 */ 255 struct stm32_sai_data { 256 struct platform_device *pdev; 257 struct clk *clk_x8k; 258 struct clk *clk_x11k; 259 struct stm32_sai_conf *conf; 260 int irq; 261 }; 262