1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/bitfield.h> 10 11 /******************** SAI Register Map **************************************/ 12 13 /* Global configuration register */ 14 #define STM_SAI_GCR 0x00 15 16 /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */ 17 #define STM_SAI_CR1_REGX 0x00 /* A offset: 0x04. B offset: 0x24 */ 18 #define STM_SAI_CR2_REGX 0x04 19 #define STM_SAI_FRCR_REGX 0x08 20 #define STM_SAI_SLOTR_REGX 0x0C 21 #define STM_SAI_IMR_REGX 0x10 22 #define STM_SAI_SR_REGX 0x14 23 #define STM_SAI_CLRFR_REGX 0x18 24 #define STM_SAI_DR_REGX 0x1C 25 26 /* Sub-block A registers, relative to sub-block A address */ 27 #define STM_SAI_PDMCR_REGX 0x40 28 #define STM_SAI_PDMLY_REGX 0x44 29 30 /******************** Bit definition for SAI_GCR register *******************/ 31 #define SAI_GCR_SYNCIN_SHIFT 0 32 #define SAI_GCR_SYNCIN_WDTH 2 33 #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT) 34 #define SAI_GCR_SYNCIN_MAX FIELD_GET(SAI_GCR_SYNCIN_MASK,\ 35 SAI_GCR_SYNCIN_MASK) 36 37 #define SAI_GCR_SYNCOUT_SHIFT 4 38 #define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT) 39 40 /******************* Bit definition for SAI_XCR1 register *******************/ 41 #define SAI_XCR1_RX_TX_SHIFT 0 42 #define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT) 43 #define SAI_XCR1_SLAVE_SHIFT 1 44 #define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT) 45 46 #define SAI_XCR1_PRTCFG_SHIFT 2 47 #define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT) 48 #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT) 49 50 #define SAI_XCR1_DS_SHIFT 5 51 #define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT) 52 #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT) 53 54 #define SAI_XCR1_LSBFIRST_SHIFT 8 55 #define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT) 56 #define SAI_XCR1_CKSTR_SHIFT 9 57 #define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT) 58 59 #define SAI_XCR1_SYNCEN_SHIFT 10 60 #define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT) 61 #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT) 62 63 #define SAI_XCR1_MONO_SHIFT 12 64 #define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT) 65 #define SAI_XCR1_OUTDRIV_SHIFT 13 66 #define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT) 67 #define SAI_XCR1_SAIEN_SHIFT 16 68 #define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT) 69 #define SAI_XCR1_DMAEN_SHIFT 17 70 #define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT) 71 #define SAI_XCR1_NODIV_SHIFT 19 72 #define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT) 73 74 #define SAI_XCR1_MCKDIV_SHIFT 20 75 #define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == SAI_STM32F4) ? 4 : 6) 76 #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\ 77 SAI_XCR1_MCKDIV_SHIFT) 78 #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT) 79 #define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1) 80 81 #define SAI_XCR1_OSR_SHIFT 26 82 #define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT) 83 84 #define SAI_XCR1_MCKEN_SHIFT 27 85 #define SAI_XCR1_MCKEN BIT(SAI_XCR1_MCKEN_SHIFT) 86 87 /******************* Bit definition for SAI_XCR2 register *******************/ 88 #define SAI_XCR2_FTH_SHIFT 0 89 #define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT) 90 #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT) 91 92 #define SAI_XCR2_FFLUSH_SHIFT 3 93 #define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT) 94 #define SAI_XCR2_TRIS_SHIFT 4 95 #define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT) 96 #define SAI_XCR2_MUTE_SHIFT 5 97 #define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT) 98 #define SAI_XCR2_MUTEVAL_SHIFT 6 99 #define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT) 100 101 #define SAI_XCR2_MUTECNT_SHIFT 7 102 #define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT) 103 #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT) 104 105 #define SAI_XCR2_CPL_SHIFT 13 106 #define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT) 107 108 #define SAI_XCR2_COMP_SHIFT 14 109 #define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT) 110 #define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT) 111 112 /****************** Bit definition for SAI_XFRCR register *******************/ 113 #define SAI_XFRCR_FRL_SHIFT 0 114 #define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT) 115 #define SAI_XFRCR_FRL_SET(x) ((x) << SAI_XFRCR_FRL_SHIFT) 116 117 #define SAI_XFRCR_FSALL_SHIFT 8 118 #define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT) 119 #define SAI_XFRCR_FSALL_SET(x) ((x) << SAI_XFRCR_FSALL_SHIFT) 120 121 #define SAI_XFRCR_FSDEF_SHIFT 16 122 #define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT) 123 #define SAI_XFRCR_FSPOL_SHIFT 17 124 #define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT) 125 #define SAI_XFRCR_FSOFF_SHIFT 18 126 #define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT) 127 128 /****************** Bit definition for SAI_XSLOTR register ******************/ 129 #define SAI_XSLOTR_FBOFF_SHIFT 0 130 #define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT) 131 #define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT) 132 133 #define SAI_XSLOTR_SLOTSZ_SHIFT 6 134 #define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT) 135 #define SAI_XSLOTR_SLOTSZ_SET(x) ((x) << SAI_XSLOTR_SLOTSZ_SHIFT) 136 137 #define SAI_XSLOTR_NBSLOT_SHIFT 8 138 #define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT) 139 #define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT) 140 141 #define SAI_XSLOTR_SLOTEN_SHIFT 16 142 #define SAI_XSLOTR_SLOTEN_WIDTH 16 143 #define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT) 144 #define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT) 145 146 /******************* Bit definition for SAI_XIMR register *******************/ 147 #define SAI_XIMR_OVRUDRIE BIT(0) 148 #define SAI_XIMR_MUTEDETIE BIT(1) 149 #define SAI_XIMR_WCKCFGIE BIT(2) 150 #define SAI_XIMR_FREQIE BIT(3) 151 #define SAI_XIMR_CNRDYIE BIT(4) 152 #define SAI_XIMR_AFSDETIE BIT(5) 153 #define SAI_XIMR_LFSDETIE BIT(6) 154 155 #define SAI_XIMR_SHIFT 0 156 #define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT) 157 158 /******************** Bit definition for SAI_XSR register *******************/ 159 #define SAI_XSR_OVRUDR BIT(0) 160 #define SAI_XSR_MUTEDET BIT(1) 161 #define SAI_XSR_WCKCFG BIT(2) 162 #define SAI_XSR_FREQ BIT(3) 163 #define SAI_XSR_CNRDY BIT(4) 164 #define SAI_XSR_AFSDET BIT(5) 165 #define SAI_XSR_LFSDET BIT(6) 166 167 #define SAI_XSR_SHIFT 0 168 #define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT) 169 170 /****************** Bit definition for SAI_XCLRFR register ******************/ 171 #define SAI_XCLRFR_COVRUDR BIT(0) 172 #define SAI_XCLRFR_CMUTEDET BIT(1) 173 #define SAI_XCLRFR_CWCKCFG BIT(2) 174 #define SAI_XCLRFR_CFREQ BIT(3) 175 #define SAI_XCLRFR_CCNRDY BIT(4) 176 #define SAI_XCLRFR_CAFSDET BIT(5) 177 #define SAI_XCLRFR_CLFSDET BIT(6) 178 179 #define SAI_XCLRFR_SHIFT 0 180 #define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT) 181 182 /****************** Bit definition for SAI_PDMCR register ******************/ 183 #define SAI_PDMCR_PDMEN BIT(0) 184 185 #define SAI_PDMCR_MICNBR_SHIFT 4 186 #define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT) 187 #define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT) 188 189 #define SAI_PDMCR_CKEN1 BIT(8) 190 #define SAI_PDMCR_CKEN2 BIT(9) 191 #define SAI_PDMCR_CKEN3 BIT(10) 192 #define SAI_PDMCR_CKEN4 BIT(11) 193 194 /****************** Bit definition for (SAI_PDMDLY register ****************/ 195 #define SAI_PDMDLY_1L_SHIFT 0 196 #define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT) 197 #define SAI_PDMDLY_1L_WIDTH 3 198 199 #define SAI_PDMDLY_1R_SHIFT 4 200 #define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT) 201 #define SAI_PDMDLY_1R_WIDTH 3 202 203 #define SAI_PDMDLY_2L_SHIFT 8 204 #define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT) 205 #define SAI_PDMDLY_2L_WIDTH 3 206 207 #define SAI_PDMDLY_2R_SHIFT 12 208 #define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT) 209 #define SAI_PDMDLY_2R_WIDTH 3 210 211 #define SAI_PDMDLY_3L_SHIFT 16 212 #define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT) 213 #define SAI_PDMDLY_3L_WIDTH 3 214 215 #define SAI_PDMDLY_3R_SHIFT 20 216 #define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT) 217 #define SAI_PDMDLY_3R_WIDTH 3 218 219 #define SAI_PDMDLY_4L_SHIFT 24 220 #define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT) 221 #define SAI_PDMDLY_4L_WIDTH 3 222 223 #define SAI_PDMDLY_4R_SHIFT 28 224 #define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT) 225 #define SAI_PDMDLY_4R_WIDTH 3 226 227 #define STM_SAI_IS_F4(ip) ((ip)->conf->version == SAI_STM32F4) 228 #define STM_SAI_IS_H7(ip) ((ip)->conf->version == SAI_STM32H7) 229 230 enum stm32_sai_syncout { 231 STM_SAI_SYNC_OUT_NONE, 232 STM_SAI_SYNC_OUT_A, 233 STM_SAI_SYNC_OUT_B, 234 }; 235 236 enum stm32_sai_version { 237 SAI_STM32F4, 238 SAI_STM32H7 239 }; 240 241 /** 242 * struct stm32_sai_conf - SAI configuration 243 * @version: SAI version 244 * @has_spdif: SAI S/PDIF support flag 245 */ 246 struct stm32_sai_conf { 247 int version; 248 bool has_spdif; 249 }; 250 251 /** 252 * struct stm32_sai_data - private data of SAI instance driver 253 * @pdev: device data pointer 254 * @base: common register bank virtual base address 255 * @pclk: SAI bus clock 256 * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz 257 * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz 258 * @version: SOC version 259 * @irq: SAI interrupt line 260 * @set_sync: pointer to synchro mode configuration callback 261 * @gcr: SAI Global Configuration Register 262 */ 263 struct stm32_sai_data { 264 struct platform_device *pdev; 265 void __iomem *base; 266 struct clk *pclk; 267 struct clk *clk_x8k; 268 struct clk *clk_x11k; 269 struct stm32_sai_conf *conf; 270 int irq; 271 int (*set_sync)(struct stm32_sai_data *sai, 272 struct device_node *np_provider, int synco, int synci); 273 u32 gcr; 274 }; 275