13e086edfSolivier moysan /* 23e086edfSolivier moysan * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 33e086edfSolivier moysan * 43e086edfSolivier moysan * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 53e086edfSolivier moysan * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 63e086edfSolivier moysan * 73e086edfSolivier moysan * License terms: GPL V2.0. 83e086edfSolivier moysan * 93e086edfSolivier moysan * This program is free software; you can redistribute it and/or modify it 103e086edfSolivier moysan * under the terms of the GNU General Public License version 2 as published by 113e086edfSolivier moysan * the Free Software Foundation. 123e086edfSolivier moysan * 133e086edfSolivier moysan * This program is distributed in the hope that it will be useful, but 143e086edfSolivier moysan * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 153e086edfSolivier moysan * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 163e086edfSolivier moysan * details. 173e086edfSolivier moysan */ 183e086edfSolivier moysan 193e086edfSolivier moysan /******************** SAI Register Map **************************************/ 203e086edfSolivier moysan 213e086edfSolivier moysan /* common register */ 223e086edfSolivier moysan #define STM_SAI_GCR 0x00 233e086edfSolivier moysan 243e086edfSolivier moysan /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */ 253e086edfSolivier moysan #define STM_SAI_CR1_REGX 0x00 /* A offset: 0x04. B offset: 0x24 */ 263e086edfSolivier moysan #define STM_SAI_CR2_REGX 0x04 273e086edfSolivier moysan #define STM_SAI_FRCR_REGX 0x08 283e086edfSolivier moysan #define STM_SAI_SLOTR_REGX 0x0C 293e086edfSolivier moysan #define STM_SAI_IMR_REGX 0x10 303e086edfSolivier moysan #define STM_SAI_SR_REGX 0x14 313e086edfSolivier moysan #define STM_SAI_CLRFR_REGX 0x18 323e086edfSolivier moysan #define STM_SAI_DR_REGX 0x1C 333e086edfSolivier moysan 34*03e78a24Solivier moysan /* Sub-block A registers, relative to sub-block A address */ 35*03e78a24Solivier moysan #define STM_SAI_PDMCR_REGX 0x40 36*03e78a24Solivier moysan #define STM_SAI_PDMLY_REGX 0x44 37*03e78a24Solivier moysan 383e086edfSolivier moysan /******************** Bit definition for SAI_GCR register *******************/ 393e086edfSolivier moysan #define SAI_GCR_SYNCIN_SHIFT 0 403e086edfSolivier moysan #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT) 413e086edfSolivier moysan #define SAI_GCR_SYNCIN_SET(x) ((x) << SAI_GCR_SYNCIN_SHIFT) 423e086edfSolivier moysan 433e086edfSolivier moysan #define SAI_GCR_SYNCOUT_SHIFT 4 443e086edfSolivier moysan #define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT) 453e086edfSolivier moysan #define SAI_GCR_SYNCOUT_SET(x) ((x) << SAI_GCR_SYNCOUT_SHIFT) 463e086edfSolivier moysan 473e086edfSolivier moysan /******************* Bit definition for SAI_XCR1 register *******************/ 483e086edfSolivier moysan #define SAI_XCR1_RX_TX_SHIFT 0 493e086edfSolivier moysan #define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT) 503e086edfSolivier moysan #define SAI_XCR1_SLAVE_SHIFT 1 513e086edfSolivier moysan #define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT) 523e086edfSolivier moysan 533e086edfSolivier moysan #define SAI_XCR1_PRTCFG_SHIFT 2 543e086edfSolivier moysan #define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT) 553e086edfSolivier moysan #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT) 563e086edfSolivier moysan 573e086edfSolivier moysan #define SAI_XCR1_DS_SHIFT 5 583e086edfSolivier moysan #define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT) 593e086edfSolivier moysan #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT) 603e086edfSolivier moysan 613e086edfSolivier moysan #define SAI_XCR1_LSBFIRST_SHIFT 8 623e086edfSolivier moysan #define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT) 633e086edfSolivier moysan #define SAI_XCR1_CKSTR_SHIFT 9 643e086edfSolivier moysan #define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT) 653e086edfSolivier moysan 663e086edfSolivier moysan #define SAI_XCR1_SYNCEN_SHIFT 10 673e086edfSolivier moysan #define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT) 683e086edfSolivier moysan #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT) 693e086edfSolivier moysan 703e086edfSolivier moysan #define SAI_XCR1_MONO_SHIFT 12 713e086edfSolivier moysan #define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT) 723e086edfSolivier moysan #define SAI_XCR1_OUTDRIV_SHIFT 13 733e086edfSolivier moysan #define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT) 743e086edfSolivier moysan #define SAI_XCR1_SAIEN_SHIFT 16 753e086edfSolivier moysan #define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT) 763e086edfSolivier moysan #define SAI_XCR1_DMAEN_SHIFT 17 773e086edfSolivier moysan #define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT) 783e086edfSolivier moysan #define SAI_XCR1_NODIV_SHIFT 19 793e086edfSolivier moysan #define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT) 803e086edfSolivier moysan 813e086edfSolivier moysan #define SAI_XCR1_MCKDIV_SHIFT 20 82*03e78a24Solivier moysan #define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == SAI_STM32F4) ? 4 : 6) 83*03e78a24Solivier moysan #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\ 84*03e78a24Solivier moysan SAI_XCR1_MCKDIV_SHIFT) 853e086edfSolivier moysan #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT) 86*03e78a24Solivier moysan #define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1) 873e086edfSolivier moysan 883e086edfSolivier moysan #define SAI_XCR1_OSR_SHIFT 26 893e086edfSolivier moysan #define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT) 903e086edfSolivier moysan 913e086edfSolivier moysan /******************* Bit definition for SAI_XCR2 register *******************/ 923e086edfSolivier moysan #define SAI_XCR2_FTH_SHIFT 0 933e086edfSolivier moysan #define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT) 943e086edfSolivier moysan #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT) 953e086edfSolivier moysan 963e086edfSolivier moysan #define SAI_XCR2_FFLUSH_SHIFT 3 973e086edfSolivier moysan #define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT) 983e086edfSolivier moysan #define SAI_XCR2_TRIS_SHIFT 4 993e086edfSolivier moysan #define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT) 1003e086edfSolivier moysan #define SAI_XCR2_MUTE_SHIFT 5 1013e086edfSolivier moysan #define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT) 1023e086edfSolivier moysan #define SAI_XCR2_MUTEVAL_SHIFT 6 1033e086edfSolivier moysan #define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT) 1043e086edfSolivier moysan 1053e086edfSolivier moysan #define SAI_XCR2_MUTECNT_SHIFT 7 1063e086edfSolivier moysan #define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT) 1073e086edfSolivier moysan #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT) 1083e086edfSolivier moysan 1093e086edfSolivier moysan #define SAI_XCR2_CPL_SHIFT 13 1103e086edfSolivier moysan #define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT) 1113e086edfSolivier moysan 1123e086edfSolivier moysan #define SAI_XCR2_COMP_SHIFT 14 1133e086edfSolivier moysan #define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT) 1143e086edfSolivier moysan #define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT) 1153e086edfSolivier moysan 1163e086edfSolivier moysan /****************** Bit definition for SAI_XFRCR register *******************/ 1173e086edfSolivier moysan #define SAI_XFRCR_FRL_SHIFT 0 1183e086edfSolivier moysan #define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT) 1193e086edfSolivier moysan #define SAI_XFRCR_FRL_SET(x) ((x) << SAI_XFRCR_FRL_SHIFT) 1203e086edfSolivier moysan 1213e086edfSolivier moysan #define SAI_XFRCR_FSALL_SHIFT 8 1223e086edfSolivier moysan #define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT) 1233e086edfSolivier moysan #define SAI_XFRCR_FSALL_SET(x) ((x) << SAI_XFRCR_FSALL_SHIFT) 1243e086edfSolivier moysan 1253e086edfSolivier moysan #define SAI_XFRCR_FSDEF_SHIFT 16 1263e086edfSolivier moysan #define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT) 1273e086edfSolivier moysan #define SAI_XFRCR_FSPOL_SHIFT 17 1283e086edfSolivier moysan #define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT) 1293e086edfSolivier moysan #define SAI_XFRCR_FSOFF_SHIFT 18 1303e086edfSolivier moysan #define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT) 1313e086edfSolivier moysan 1323e086edfSolivier moysan /****************** Bit definition for SAI_XSLOTR register ******************/ 1333e086edfSolivier moysan #define SAI_XSLOTR_FBOFF_SHIFT 0 1343e086edfSolivier moysan #define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT) 1353e086edfSolivier moysan #define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT) 1363e086edfSolivier moysan 1373e086edfSolivier moysan #define SAI_XSLOTR_SLOTSZ_SHIFT 6 1383e086edfSolivier moysan #define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT) 1393e086edfSolivier moysan #define SAI_XSLOTR_SLOTSZ_SET(x) ((x) << SAI_XSLOTR_SLOTSZ_SHIFT) 1403e086edfSolivier moysan 1413e086edfSolivier moysan #define SAI_XSLOTR_NBSLOT_SHIFT 8 1423e086edfSolivier moysan #define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT) 1433e086edfSolivier moysan #define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT) 1443e086edfSolivier moysan 1453e086edfSolivier moysan #define SAI_XSLOTR_SLOTEN_SHIFT 16 1463e086edfSolivier moysan #define SAI_XSLOTR_SLOTEN_WIDTH 16 1473e086edfSolivier moysan #define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT) 1483e086edfSolivier moysan #define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT) 1493e086edfSolivier moysan 1503e086edfSolivier moysan /******************* Bit definition for SAI_XIMR register *******************/ 1513e086edfSolivier moysan #define SAI_XIMR_OVRUDRIE BIT(0) 1523e086edfSolivier moysan #define SAI_XIMR_MUTEDETIE BIT(1) 1533e086edfSolivier moysan #define SAI_XIMR_WCKCFGIE BIT(2) 1543e086edfSolivier moysan #define SAI_XIMR_FREQIE BIT(3) 1553e086edfSolivier moysan #define SAI_XIMR_CNRDYIE BIT(4) 1563e086edfSolivier moysan #define SAI_XIMR_AFSDETIE BIT(5) 1573e086edfSolivier moysan #define SAI_XIMR_LFSDETIE BIT(6) 1583e086edfSolivier moysan 1593e086edfSolivier moysan #define SAI_XIMR_SHIFT 0 1603e086edfSolivier moysan #define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT) 1613e086edfSolivier moysan 1623e086edfSolivier moysan /******************** Bit definition for SAI_XSR register *******************/ 1633e086edfSolivier moysan #define SAI_XSR_OVRUDR BIT(0) 1643e086edfSolivier moysan #define SAI_XSR_MUTEDET BIT(1) 1653e086edfSolivier moysan #define SAI_XSR_WCKCFG BIT(2) 1663e086edfSolivier moysan #define SAI_XSR_FREQ BIT(3) 1673e086edfSolivier moysan #define SAI_XSR_CNRDY BIT(4) 1683e086edfSolivier moysan #define SAI_XSR_AFSDET BIT(5) 1693e086edfSolivier moysan #define SAI_XSR_LFSDET BIT(6) 1703e086edfSolivier moysan 1713e086edfSolivier moysan #define SAI_XSR_SHIFT 0 1723e086edfSolivier moysan #define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT) 1733e086edfSolivier moysan 1743e086edfSolivier moysan /****************** Bit definition for SAI_XCLRFR register ******************/ 1753e086edfSolivier moysan #define SAI_XCLRFR_COVRUDR BIT(0) 1763e086edfSolivier moysan #define SAI_XCLRFR_CMUTEDET BIT(1) 1773e086edfSolivier moysan #define SAI_XCLRFR_CWCKCFG BIT(2) 1783e086edfSolivier moysan #define SAI_XCLRFR_CFREQ BIT(3) 1793e086edfSolivier moysan #define SAI_XCLRFR_CCNRDY BIT(4) 1803e086edfSolivier moysan #define SAI_XCLRFR_CAFSDET BIT(5) 1813e086edfSolivier moysan #define SAI_XCLRFR_CLFSDET BIT(6) 1823e086edfSolivier moysan 1833e086edfSolivier moysan #define SAI_XCLRFR_SHIFT 0 1843e086edfSolivier moysan #define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT) 1853e086edfSolivier moysan 186*03e78a24Solivier moysan /****************** Bit definition for SAI_PDMCR register ******************/ 187*03e78a24Solivier moysan #define SAI_PDMCR_PDMEN BIT(0) 188*03e78a24Solivier moysan 189*03e78a24Solivier moysan #define SAI_PDMCR_MICNBR_SHIFT 4 190*03e78a24Solivier moysan #define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT) 191*03e78a24Solivier moysan #define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT) 192*03e78a24Solivier moysan 193*03e78a24Solivier moysan #define SAI_PDMCR_CKEN1 BIT(8) 194*03e78a24Solivier moysan #define SAI_PDMCR_CKEN2 BIT(9) 195*03e78a24Solivier moysan #define SAI_PDMCR_CKEN3 BIT(10) 196*03e78a24Solivier moysan #define SAI_PDMCR_CKEN4 BIT(11) 197*03e78a24Solivier moysan 198*03e78a24Solivier moysan /****************** Bit definition for (SAI_PDMDLY register ****************/ 199*03e78a24Solivier moysan #define SAI_PDMDLY_1L_SHIFT 0 200*03e78a24Solivier moysan #define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT) 201*03e78a24Solivier moysan #define SAI_PDMDLY_1L_WIDTH 3 202*03e78a24Solivier moysan 203*03e78a24Solivier moysan #define SAI_PDMDLY_1R_SHIFT 4 204*03e78a24Solivier moysan #define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT) 205*03e78a24Solivier moysan #define SAI_PDMDLY_1R_WIDTH 3 206*03e78a24Solivier moysan 207*03e78a24Solivier moysan #define SAI_PDMDLY_2L_SHIFT 8 208*03e78a24Solivier moysan #define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT) 209*03e78a24Solivier moysan #define SAI_PDMDLY_2L_WIDTH 3 210*03e78a24Solivier moysan 211*03e78a24Solivier moysan #define SAI_PDMDLY_2R_SHIFT 12 212*03e78a24Solivier moysan #define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT) 213*03e78a24Solivier moysan #define SAI_PDMDLY_2R_WIDTH 3 214*03e78a24Solivier moysan 215*03e78a24Solivier moysan #define SAI_PDMDLY_3L_SHIFT 16 216*03e78a24Solivier moysan #define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT) 217*03e78a24Solivier moysan #define SAI_PDMDLY_3L_WIDTH 3 218*03e78a24Solivier moysan 219*03e78a24Solivier moysan #define SAI_PDMDLY_3R_SHIFT 20 220*03e78a24Solivier moysan #define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT) 221*03e78a24Solivier moysan #define SAI_PDMDLY_3R_WIDTH 3 222*03e78a24Solivier moysan 223*03e78a24Solivier moysan #define SAI_PDMDLY_4L_SHIFT 24 224*03e78a24Solivier moysan #define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT) 225*03e78a24Solivier moysan #define SAI_PDMDLY_4L_WIDTH 3 226*03e78a24Solivier moysan 227*03e78a24Solivier moysan #define SAI_PDMDLY_4R_SHIFT 28 228*03e78a24Solivier moysan #define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT) 229*03e78a24Solivier moysan #define SAI_PDMDLY_4R_WIDTH 3 230*03e78a24Solivier moysan 231*03e78a24Solivier moysan #define STM_SAI_IS_F4(ip) ((ip)->conf->version == SAI_STM32F4) 232*03e78a24Solivier moysan #define STM_SAI_IS_H7(ip) ((ip)->conf->version == SAI_STM32H7) 233*03e78a24Solivier moysan 2343e086edfSolivier moysan enum stm32_sai_version { 235*03e78a24Solivier moysan SAI_STM32F4, 236*03e78a24Solivier moysan SAI_STM32H7 237*03e78a24Solivier moysan }; 238*03e78a24Solivier moysan 239*03e78a24Solivier moysan /** 240*03e78a24Solivier moysan * struct stm32_sai_conf - SAI configuration 241*03e78a24Solivier moysan * @version: SAI version 242*03e78a24Solivier moysan */ 243*03e78a24Solivier moysan struct stm32_sai_conf { 244*03e78a24Solivier moysan int version; 2453e086edfSolivier moysan }; 2463e086edfSolivier moysan 2473e086edfSolivier moysan /** 2483e086edfSolivier moysan * struct stm32_sai_data - private data of SAI instance driver 2493e086edfSolivier moysan * @pdev: device data pointer 2503e086edfSolivier moysan * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz 2513e086edfSolivier moysan * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz 2523e086edfSolivier moysan * @version: SOC version 2533e086edfSolivier moysan * @irq: SAI interrupt line 2543e086edfSolivier moysan */ 2553e086edfSolivier moysan struct stm32_sai_data { 2563e086edfSolivier moysan struct platform_device *pdev; 2573e086edfSolivier moysan struct clk *clk_x8k; 2583e086edfSolivier moysan struct clk *clk_x11k; 259*03e78a24Solivier moysan struct stm32_sai_conf *conf; 2603e086edfSolivier moysan int irq; 2613e086edfSolivier moysan }; 262