11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 23e086edfSolivier moysan /* 33e086edfSolivier moysan * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 43e086edfSolivier moysan * 53e086edfSolivier moysan * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 63e086edfSolivier moysan * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 73e086edfSolivier moysan */ 83e086edfSolivier moysan 95914d285SOlivier Moysan #include <linux/bitfield.h> 105914d285SOlivier Moysan 113e086edfSolivier moysan /******************** SAI Register Map **************************************/ 123e086edfSolivier moysan 135914d285SOlivier Moysan /* Global configuration register */ 143e086edfSolivier moysan #define STM_SAI_GCR 0x00 153e086edfSolivier moysan 163e086edfSolivier moysan /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */ 173e086edfSolivier moysan #define STM_SAI_CR1_REGX 0x00 /* A offset: 0x04. B offset: 0x24 */ 183e086edfSolivier moysan #define STM_SAI_CR2_REGX 0x04 193e086edfSolivier moysan #define STM_SAI_FRCR_REGX 0x08 203e086edfSolivier moysan #define STM_SAI_SLOTR_REGX 0x0C 213e086edfSolivier moysan #define STM_SAI_IMR_REGX 0x10 223e086edfSolivier moysan #define STM_SAI_SR_REGX 0x14 233e086edfSolivier moysan #define STM_SAI_CLRFR_REGX 0x18 243e086edfSolivier moysan #define STM_SAI_DR_REGX 0x1C 253e086edfSolivier moysan 2603e78a24Solivier moysan /* Sub-block A registers, relative to sub-block A address */ 2703e78a24Solivier moysan #define STM_SAI_PDMCR_REGX 0x40 2803e78a24Solivier moysan #define STM_SAI_PDMLY_REGX 0x44 2903e78a24Solivier moysan 30*1d9c95c1SOlivier Moysan /* Hardware configuration registers */ 31*1d9c95c1SOlivier Moysan #define STM_SAI_HWCFGR 0x3F0 32*1d9c95c1SOlivier Moysan #define STM_SAI_VERR 0x3F4 33*1d9c95c1SOlivier Moysan #define STM_SAI_IDR 0x3F8 34*1d9c95c1SOlivier Moysan #define STM_SAI_SIDR 0x3FC 35*1d9c95c1SOlivier Moysan 363e086edfSolivier moysan /******************** Bit definition for SAI_GCR register *******************/ 373e086edfSolivier moysan #define SAI_GCR_SYNCIN_SHIFT 0 385914d285SOlivier Moysan #define SAI_GCR_SYNCIN_WDTH 2 393e086edfSolivier moysan #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT) 405914d285SOlivier Moysan #define SAI_GCR_SYNCIN_MAX FIELD_GET(SAI_GCR_SYNCIN_MASK,\ 415914d285SOlivier Moysan SAI_GCR_SYNCIN_MASK) 423e086edfSolivier moysan 433e086edfSolivier moysan #define SAI_GCR_SYNCOUT_SHIFT 4 443e086edfSolivier moysan #define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT) 453e086edfSolivier moysan 463e086edfSolivier moysan /******************* Bit definition for SAI_XCR1 register *******************/ 473e086edfSolivier moysan #define SAI_XCR1_RX_TX_SHIFT 0 483e086edfSolivier moysan #define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT) 493e086edfSolivier moysan #define SAI_XCR1_SLAVE_SHIFT 1 503e086edfSolivier moysan #define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT) 513e086edfSolivier moysan 523e086edfSolivier moysan #define SAI_XCR1_PRTCFG_SHIFT 2 533e086edfSolivier moysan #define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT) 543e086edfSolivier moysan #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT) 553e086edfSolivier moysan 563e086edfSolivier moysan #define SAI_XCR1_DS_SHIFT 5 573e086edfSolivier moysan #define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT) 583e086edfSolivier moysan #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT) 593e086edfSolivier moysan 603e086edfSolivier moysan #define SAI_XCR1_LSBFIRST_SHIFT 8 613e086edfSolivier moysan #define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT) 623e086edfSolivier moysan #define SAI_XCR1_CKSTR_SHIFT 9 633e086edfSolivier moysan #define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT) 643e086edfSolivier moysan 653e086edfSolivier moysan #define SAI_XCR1_SYNCEN_SHIFT 10 663e086edfSolivier moysan #define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT) 673e086edfSolivier moysan #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT) 683e086edfSolivier moysan 693e086edfSolivier moysan #define SAI_XCR1_MONO_SHIFT 12 703e086edfSolivier moysan #define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT) 713e086edfSolivier moysan #define SAI_XCR1_OUTDRIV_SHIFT 13 723e086edfSolivier moysan #define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT) 733e086edfSolivier moysan #define SAI_XCR1_SAIEN_SHIFT 16 743e086edfSolivier moysan #define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT) 753e086edfSolivier moysan #define SAI_XCR1_DMAEN_SHIFT 17 763e086edfSolivier moysan #define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT) 773e086edfSolivier moysan #define SAI_XCR1_NODIV_SHIFT 19 783e086edfSolivier moysan #define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT) 793e086edfSolivier moysan 803e086edfSolivier moysan #define SAI_XCR1_MCKDIV_SHIFT 20 81*1d9c95c1SOlivier Moysan #define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == STM_SAI_STM32F4) ? 4 : 6) 8203e78a24Solivier moysan #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\ 8303e78a24Solivier moysan SAI_XCR1_MCKDIV_SHIFT) 843e086edfSolivier moysan #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT) 8503e78a24Solivier moysan #define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1) 863e086edfSolivier moysan 873e086edfSolivier moysan #define SAI_XCR1_OSR_SHIFT 26 883e086edfSolivier moysan #define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT) 893e086edfSolivier moysan 908307b2afSOlivier Moysan #define SAI_XCR1_MCKEN_SHIFT 27 918307b2afSOlivier Moysan #define SAI_XCR1_MCKEN BIT(SAI_XCR1_MCKEN_SHIFT) 928307b2afSOlivier Moysan 933e086edfSolivier moysan /******************* Bit definition for SAI_XCR2 register *******************/ 943e086edfSolivier moysan #define SAI_XCR2_FTH_SHIFT 0 953e086edfSolivier moysan #define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT) 963e086edfSolivier moysan #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT) 973e086edfSolivier moysan 983e086edfSolivier moysan #define SAI_XCR2_FFLUSH_SHIFT 3 993e086edfSolivier moysan #define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT) 1003e086edfSolivier moysan #define SAI_XCR2_TRIS_SHIFT 4 1013e086edfSolivier moysan #define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT) 1023e086edfSolivier moysan #define SAI_XCR2_MUTE_SHIFT 5 1033e086edfSolivier moysan #define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT) 1043e086edfSolivier moysan #define SAI_XCR2_MUTEVAL_SHIFT 6 1053e086edfSolivier moysan #define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT) 1063e086edfSolivier moysan 1073e086edfSolivier moysan #define SAI_XCR2_MUTECNT_SHIFT 7 1083e086edfSolivier moysan #define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT) 1093e086edfSolivier moysan #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT) 1103e086edfSolivier moysan 1113e086edfSolivier moysan #define SAI_XCR2_CPL_SHIFT 13 1123e086edfSolivier moysan #define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT) 1133e086edfSolivier moysan 1143e086edfSolivier moysan #define SAI_XCR2_COMP_SHIFT 14 1153e086edfSolivier moysan #define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT) 1163e086edfSolivier moysan #define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT) 1173e086edfSolivier moysan 1183e086edfSolivier moysan /****************** Bit definition for SAI_XFRCR register *******************/ 1193e086edfSolivier moysan #define SAI_XFRCR_FRL_SHIFT 0 1203e086edfSolivier moysan #define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT) 1213e086edfSolivier moysan #define SAI_XFRCR_FRL_SET(x) ((x) << SAI_XFRCR_FRL_SHIFT) 1223e086edfSolivier moysan 1233e086edfSolivier moysan #define SAI_XFRCR_FSALL_SHIFT 8 1243e086edfSolivier moysan #define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT) 1253e086edfSolivier moysan #define SAI_XFRCR_FSALL_SET(x) ((x) << SAI_XFRCR_FSALL_SHIFT) 1263e086edfSolivier moysan 1273e086edfSolivier moysan #define SAI_XFRCR_FSDEF_SHIFT 16 1283e086edfSolivier moysan #define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT) 1293e086edfSolivier moysan #define SAI_XFRCR_FSPOL_SHIFT 17 1303e086edfSolivier moysan #define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT) 1313e086edfSolivier moysan #define SAI_XFRCR_FSOFF_SHIFT 18 1323e086edfSolivier moysan #define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT) 1333e086edfSolivier moysan 1343e086edfSolivier moysan /****************** Bit definition for SAI_XSLOTR register ******************/ 1353e086edfSolivier moysan #define SAI_XSLOTR_FBOFF_SHIFT 0 1363e086edfSolivier moysan #define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT) 1373e086edfSolivier moysan #define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT) 1383e086edfSolivier moysan 1393e086edfSolivier moysan #define SAI_XSLOTR_SLOTSZ_SHIFT 6 1403e086edfSolivier moysan #define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT) 1413e086edfSolivier moysan #define SAI_XSLOTR_SLOTSZ_SET(x) ((x) << SAI_XSLOTR_SLOTSZ_SHIFT) 1423e086edfSolivier moysan 1433e086edfSolivier moysan #define SAI_XSLOTR_NBSLOT_SHIFT 8 1443e086edfSolivier moysan #define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT) 1453e086edfSolivier moysan #define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT) 1463e086edfSolivier moysan 1473e086edfSolivier moysan #define SAI_XSLOTR_SLOTEN_SHIFT 16 1483e086edfSolivier moysan #define SAI_XSLOTR_SLOTEN_WIDTH 16 1493e086edfSolivier moysan #define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT) 1503e086edfSolivier moysan #define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT) 1513e086edfSolivier moysan 1523e086edfSolivier moysan /******************* Bit definition for SAI_XIMR register *******************/ 1533e086edfSolivier moysan #define SAI_XIMR_OVRUDRIE BIT(0) 1543e086edfSolivier moysan #define SAI_XIMR_MUTEDETIE BIT(1) 1553e086edfSolivier moysan #define SAI_XIMR_WCKCFGIE BIT(2) 1563e086edfSolivier moysan #define SAI_XIMR_FREQIE BIT(3) 1573e086edfSolivier moysan #define SAI_XIMR_CNRDYIE BIT(4) 1583e086edfSolivier moysan #define SAI_XIMR_AFSDETIE BIT(5) 1593e086edfSolivier moysan #define SAI_XIMR_LFSDETIE BIT(6) 1603e086edfSolivier moysan 1613e086edfSolivier moysan #define SAI_XIMR_SHIFT 0 1623e086edfSolivier moysan #define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT) 1633e086edfSolivier moysan 1643e086edfSolivier moysan /******************** Bit definition for SAI_XSR register *******************/ 1653e086edfSolivier moysan #define SAI_XSR_OVRUDR BIT(0) 1663e086edfSolivier moysan #define SAI_XSR_MUTEDET BIT(1) 1673e086edfSolivier moysan #define SAI_XSR_WCKCFG BIT(2) 1683e086edfSolivier moysan #define SAI_XSR_FREQ BIT(3) 1693e086edfSolivier moysan #define SAI_XSR_CNRDY BIT(4) 1703e086edfSolivier moysan #define SAI_XSR_AFSDET BIT(5) 1713e086edfSolivier moysan #define SAI_XSR_LFSDET BIT(6) 1723e086edfSolivier moysan 1733e086edfSolivier moysan #define SAI_XSR_SHIFT 0 1743e086edfSolivier moysan #define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT) 1753e086edfSolivier moysan 1763e086edfSolivier moysan /****************** Bit definition for SAI_XCLRFR register ******************/ 1773e086edfSolivier moysan #define SAI_XCLRFR_COVRUDR BIT(0) 1783e086edfSolivier moysan #define SAI_XCLRFR_CMUTEDET BIT(1) 1793e086edfSolivier moysan #define SAI_XCLRFR_CWCKCFG BIT(2) 1803e086edfSolivier moysan #define SAI_XCLRFR_CFREQ BIT(3) 1813e086edfSolivier moysan #define SAI_XCLRFR_CCNRDY BIT(4) 1823e086edfSolivier moysan #define SAI_XCLRFR_CAFSDET BIT(5) 1833e086edfSolivier moysan #define SAI_XCLRFR_CLFSDET BIT(6) 1843e086edfSolivier moysan 1853e086edfSolivier moysan #define SAI_XCLRFR_SHIFT 0 1863e086edfSolivier moysan #define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT) 1873e086edfSolivier moysan 18803e78a24Solivier moysan /****************** Bit definition for SAI_PDMCR register ******************/ 18903e78a24Solivier moysan #define SAI_PDMCR_PDMEN BIT(0) 19003e78a24Solivier moysan 19103e78a24Solivier moysan #define SAI_PDMCR_MICNBR_SHIFT 4 19203e78a24Solivier moysan #define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT) 19303e78a24Solivier moysan #define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT) 19403e78a24Solivier moysan 19503e78a24Solivier moysan #define SAI_PDMCR_CKEN1 BIT(8) 19603e78a24Solivier moysan #define SAI_PDMCR_CKEN2 BIT(9) 19703e78a24Solivier moysan #define SAI_PDMCR_CKEN3 BIT(10) 19803e78a24Solivier moysan #define SAI_PDMCR_CKEN4 BIT(11) 19903e78a24Solivier moysan 20003e78a24Solivier moysan /****************** Bit definition for (SAI_PDMDLY register ****************/ 20103e78a24Solivier moysan #define SAI_PDMDLY_1L_SHIFT 0 20203e78a24Solivier moysan #define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT) 20303e78a24Solivier moysan #define SAI_PDMDLY_1L_WIDTH 3 20403e78a24Solivier moysan 20503e78a24Solivier moysan #define SAI_PDMDLY_1R_SHIFT 4 20603e78a24Solivier moysan #define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT) 20703e78a24Solivier moysan #define SAI_PDMDLY_1R_WIDTH 3 20803e78a24Solivier moysan 20903e78a24Solivier moysan #define SAI_PDMDLY_2L_SHIFT 8 21003e78a24Solivier moysan #define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT) 21103e78a24Solivier moysan #define SAI_PDMDLY_2L_WIDTH 3 21203e78a24Solivier moysan 21303e78a24Solivier moysan #define SAI_PDMDLY_2R_SHIFT 12 21403e78a24Solivier moysan #define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT) 21503e78a24Solivier moysan #define SAI_PDMDLY_2R_WIDTH 3 21603e78a24Solivier moysan 21703e78a24Solivier moysan #define SAI_PDMDLY_3L_SHIFT 16 21803e78a24Solivier moysan #define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT) 21903e78a24Solivier moysan #define SAI_PDMDLY_3L_WIDTH 3 22003e78a24Solivier moysan 22103e78a24Solivier moysan #define SAI_PDMDLY_3R_SHIFT 20 22203e78a24Solivier moysan #define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT) 22303e78a24Solivier moysan #define SAI_PDMDLY_3R_WIDTH 3 22403e78a24Solivier moysan 22503e78a24Solivier moysan #define SAI_PDMDLY_4L_SHIFT 24 22603e78a24Solivier moysan #define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT) 22703e78a24Solivier moysan #define SAI_PDMDLY_4L_WIDTH 3 22803e78a24Solivier moysan 22903e78a24Solivier moysan #define SAI_PDMDLY_4R_SHIFT 28 23003e78a24Solivier moysan #define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT) 23103e78a24Solivier moysan #define SAI_PDMDLY_4R_WIDTH 3 23203e78a24Solivier moysan 233*1d9c95c1SOlivier Moysan /* Registers below apply to SAI version 2.1 and more */ 234*1d9c95c1SOlivier Moysan 235*1d9c95c1SOlivier Moysan /* Bit definition for SAI_HWCFGR register */ 236*1d9c95c1SOlivier Moysan #define SAI_HWCFGR_FIFO_SIZE GENMASK(7, 0) 237*1d9c95c1SOlivier Moysan #define SAI_HWCFGR_SPDIF_PDM GENMASK(11, 8) 238*1d9c95c1SOlivier Moysan #define SAI_HWCFGR_REGOUT GENMASK(19, 12) 239*1d9c95c1SOlivier Moysan 240*1d9c95c1SOlivier Moysan /* Bit definition for SAI_VERR register */ 241*1d9c95c1SOlivier Moysan #define SAI_VERR_MIN_MASK GENMASK(3, 0) 242*1d9c95c1SOlivier Moysan #define SAI_VERR_MAJ_MASK GENMASK(7, 4) 243*1d9c95c1SOlivier Moysan 244*1d9c95c1SOlivier Moysan /* Bit definition for SAI_IDR register */ 245*1d9c95c1SOlivier Moysan #define SAI_IDR_ID_MASK GENMASK(31, 0) 246*1d9c95c1SOlivier Moysan 247*1d9c95c1SOlivier Moysan /* Bit definition for SAI_SIDR register */ 248*1d9c95c1SOlivier Moysan #define SAI_SIDR_ID_MASK GENMASK(31, 0) 249*1d9c95c1SOlivier Moysan 250*1d9c95c1SOlivier Moysan #define SAI_IPIDR_NUMBER 0x00130031 251*1d9c95c1SOlivier Moysan 252*1d9c95c1SOlivier Moysan /* SAI version numbers are 1.x for F4. Major version number set to 1 for F4 */ 253*1d9c95c1SOlivier Moysan #define STM_SAI_STM32F4 BIT(4) 254*1d9c95c1SOlivier Moysan /* Dummy version number for H7 socs and next */ 255*1d9c95c1SOlivier Moysan #define STM_SAI_STM32H7 0x0 256*1d9c95c1SOlivier Moysan 257*1d9c95c1SOlivier Moysan #define STM_SAI_IS_F4(ip) ((ip)->conf.version == STM_SAI_STM32F4) 258*1d9c95c1SOlivier Moysan #define STM_SAI_HAS_SPDIF_PDM(ip)\ 259*1d9c95c1SOlivier Moysan ((ip)->pdata->conf.has_spdif_pdm) 26003e78a24Solivier moysan 2615914d285SOlivier Moysan enum stm32_sai_syncout { 2625914d285SOlivier Moysan STM_SAI_SYNC_OUT_NONE, 2635914d285SOlivier Moysan STM_SAI_SYNC_OUT_A, 2645914d285SOlivier Moysan STM_SAI_SYNC_OUT_B, 2655914d285SOlivier Moysan }; 2665914d285SOlivier Moysan 26703e78a24Solivier moysan /** 26803e78a24Solivier moysan * struct stm32_sai_conf - SAI configuration 26903e78a24Solivier moysan * @version: SAI version 270*1d9c95c1SOlivier Moysan * @fifo_size: SAI fifo size as words number 271*1d9c95c1SOlivier Moysan * @has_spdif_pdm: SAI S/PDIF and PDM features support flag 27203e78a24Solivier moysan */ 27303e78a24Solivier moysan struct stm32_sai_conf { 274*1d9c95c1SOlivier Moysan u32 version; 275*1d9c95c1SOlivier Moysan u32 fifo_size; 276*1d9c95c1SOlivier Moysan bool has_spdif_pdm; 2773e086edfSolivier moysan }; 2783e086edfSolivier moysan 2793e086edfSolivier moysan /** 2803e086edfSolivier moysan * struct stm32_sai_data - private data of SAI instance driver 2813e086edfSolivier moysan * @pdev: device data pointer 2825914d285SOlivier Moysan * @base: common register bank virtual base address 2835914d285SOlivier Moysan * @pclk: SAI bus clock 2843e086edfSolivier moysan * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz 2853e086edfSolivier moysan * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz 286*1d9c95c1SOlivier Moysan * @conf: SAI hardware capabitilites 2873e086edfSolivier moysan * @irq: SAI interrupt line 2885914d285SOlivier Moysan * @set_sync: pointer to synchro mode configuration callback 289cf881773SOlivier Moysan * @gcr: SAI Global Configuration Register 2903e086edfSolivier moysan */ 2913e086edfSolivier moysan struct stm32_sai_data { 2923e086edfSolivier moysan struct platform_device *pdev; 2935914d285SOlivier Moysan void __iomem *base; 2945914d285SOlivier Moysan struct clk *pclk; 2953e086edfSolivier moysan struct clk *clk_x8k; 2963e086edfSolivier moysan struct clk *clk_x11k; 297*1d9c95c1SOlivier Moysan struct stm32_sai_conf conf; 2983e086edfSolivier moysan int irq; 2995914d285SOlivier Moysan int (*set_sync)(struct stm32_sai_data *sai, 3005914d285SOlivier Moysan struct device_node *np_provider, int synco, int synci); 301cf881773SOlivier Moysan u32 gcr; 3023e086edfSolivier moysan }; 303