1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (I2S) driver. 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/module.h> 12 #include <linux/of_irq.h> 13 #include <linux/of_platform.h> 14 #include <linux/regmap.h> 15 #include <linux/reset.h> 16 #include <linux/spinlock.h> 17 18 #include <sound/dmaengine_pcm.h> 19 #include <sound/pcm_params.h> 20 21 #define STM32_I2S_CR1_REG 0x0 22 #define STM32_I2S_CFG1_REG 0x08 23 #define STM32_I2S_CFG2_REG 0x0C 24 #define STM32_I2S_IER_REG 0x10 25 #define STM32_I2S_SR_REG 0x14 26 #define STM32_I2S_IFCR_REG 0x18 27 #define STM32_I2S_TXDR_REG 0X20 28 #define STM32_I2S_RXDR_REG 0x30 29 #define STM32_I2S_CGFR_REG 0X50 30 31 /* Bit definition for SPI2S_CR1 register */ 32 #define I2S_CR1_SPE BIT(0) 33 #define I2S_CR1_CSTART BIT(9) 34 #define I2S_CR1_CSUSP BIT(10) 35 #define I2S_CR1_HDDIR BIT(11) 36 #define I2S_CR1_SSI BIT(12) 37 #define I2S_CR1_CRC33_17 BIT(13) 38 #define I2S_CR1_RCRCI BIT(14) 39 #define I2S_CR1_TCRCI BIT(15) 40 41 /* Bit definition for SPI_CFG2 register */ 42 #define I2S_CFG2_IOSWP_SHIFT 15 43 #define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT) 44 #define I2S_CFG2_LSBFRST BIT(23) 45 #define I2S_CFG2_AFCNTR BIT(31) 46 47 /* Bit definition for SPI_CFG1 register */ 48 #define I2S_CFG1_FTHVL_SHIFT 5 49 #define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT) 50 #define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT) 51 52 #define I2S_CFG1_TXDMAEN BIT(15) 53 #define I2S_CFG1_RXDMAEN BIT(14) 54 55 /* Bit definition for SPI2S_IER register */ 56 #define I2S_IER_RXPIE BIT(0) 57 #define I2S_IER_TXPIE BIT(1) 58 #define I2S_IER_DPXPIE BIT(2) 59 #define I2S_IER_EOTIE BIT(3) 60 #define I2S_IER_TXTFIE BIT(4) 61 #define I2S_IER_UDRIE BIT(5) 62 #define I2S_IER_OVRIE BIT(6) 63 #define I2S_IER_CRCEIE BIT(7) 64 #define I2S_IER_TIFREIE BIT(8) 65 #define I2S_IER_MODFIE BIT(9) 66 #define I2S_IER_TSERFIE BIT(10) 67 68 /* Bit definition for SPI2S_SR register */ 69 #define I2S_SR_RXP BIT(0) 70 #define I2S_SR_TXP BIT(1) 71 #define I2S_SR_DPXP BIT(2) 72 #define I2S_SR_EOT BIT(3) 73 #define I2S_SR_TXTF BIT(4) 74 #define I2S_SR_UDR BIT(5) 75 #define I2S_SR_OVR BIT(6) 76 #define I2S_SR_CRCERR BIT(7) 77 #define I2S_SR_TIFRE BIT(8) 78 #define I2S_SR_MODF BIT(9) 79 #define I2S_SR_TSERF BIT(10) 80 #define I2S_SR_SUSP BIT(11) 81 #define I2S_SR_TXC BIT(12) 82 #define I2S_SR_RXPLVL GENMASK(14, 13) 83 #define I2S_SR_RXWNE BIT(15) 84 85 #define I2S_SR_MASK GENMASK(15, 0) 86 87 /* Bit definition for SPI_IFCR register */ 88 #define I2S_IFCR_EOTC BIT(3) 89 #define I2S_IFCR_TXTFC BIT(4) 90 #define I2S_IFCR_UDRC BIT(5) 91 #define I2S_IFCR_OVRC BIT(6) 92 #define I2S_IFCR_CRCEC BIT(7) 93 #define I2S_IFCR_TIFREC BIT(8) 94 #define I2S_IFCR_MODFC BIT(9) 95 #define I2S_IFCR_TSERFC BIT(10) 96 #define I2S_IFCR_SUSPC BIT(11) 97 98 #define I2S_IFCR_MASK GENMASK(11, 3) 99 100 /* Bit definition for SPI_I2SCGFR register */ 101 #define I2S_CGFR_I2SMOD BIT(0) 102 103 #define I2S_CGFR_I2SCFG_SHIFT 1 104 #define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT) 105 #define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT) 106 107 #define I2S_CGFR_I2SSTD_SHIFT 4 108 #define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT) 109 #define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT) 110 111 #define I2S_CGFR_PCMSYNC BIT(7) 112 113 #define I2S_CGFR_DATLEN_SHIFT 8 114 #define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT) 115 #define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT) 116 117 #define I2S_CGFR_CHLEN_SHIFT 10 118 #define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT) 119 #define I2S_CGFR_CKPOL BIT(11) 120 #define I2S_CGFR_FIXCH BIT(12) 121 #define I2S_CGFR_WSINV BIT(13) 122 #define I2S_CGFR_DATFMT BIT(14) 123 124 #define I2S_CGFR_I2SDIV_SHIFT 16 125 #define I2S_CGFR_I2SDIV_BIT_H 23 126 #define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\ 127 I2S_CGFR_I2SDIV_SHIFT) 128 #define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT) 129 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\ 130 I2S_CGFR_I2SDIV_SHIFT)) - 1) 131 132 #define I2S_CGFR_ODD_SHIFT 24 133 #define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT) 134 #define I2S_CGFR_MCKOE BIT(25) 135 136 enum i2s_master_mode { 137 I2S_MS_NOT_SET, 138 I2S_MS_MASTER, 139 I2S_MS_SLAVE, 140 }; 141 142 enum i2s_mode { 143 I2S_I2SMOD_TX_SLAVE, 144 I2S_I2SMOD_RX_SLAVE, 145 I2S_I2SMOD_TX_MASTER, 146 I2S_I2SMOD_RX_MASTER, 147 I2S_I2SMOD_FD_SLAVE, 148 I2S_I2SMOD_FD_MASTER, 149 }; 150 151 enum i2s_fifo_th { 152 I2S_FIFO_TH_NONE, 153 I2S_FIFO_TH_ONE_QUARTER, 154 I2S_FIFO_TH_HALF, 155 I2S_FIFO_TH_THREE_QUARTER, 156 I2S_FIFO_TH_FULL, 157 }; 158 159 enum i2s_std { 160 I2S_STD_I2S, 161 I2S_STD_LEFT_J, 162 I2S_STD_RIGHT_J, 163 I2S_STD_DSP, 164 }; 165 166 enum i2s_datlen { 167 I2S_I2SMOD_DATLEN_16, 168 I2S_I2SMOD_DATLEN_24, 169 I2S_I2SMOD_DATLEN_32, 170 }; 171 172 #define STM32_I2S_FIFO_SIZE 16 173 174 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER) 175 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE) 176 177 /** 178 * struct stm32_i2s_data - private data of I2S 179 * @regmap_conf: I2S register map configuration pointer 180 * @regmap: I2S register map pointer 181 * @pdev: device data pointer 182 * @dai_drv: DAI driver pointer 183 * @dma_data_tx: dma configuration data for tx channel 184 * @dma_data_rx: dma configuration data for tx channel 185 * @substream: PCM substream data pointer 186 * @i2sclk: kernel clock feeding the I2S clock generator 187 * @pclk: peripheral clock driving bus interface 188 * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz 189 * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz 190 * @base: mmio register base virtual address 191 * @phys_addr: I2S registers physical base address 192 * @lock_fd: lock to manage race conditions in full duplex mode 193 * @irq_lock: prevent race condition with IRQ 194 * @mclk_rate: master clock frequency (Hz) 195 * @fmt: DAI protocol 196 * @refcount: keep count of opened streams on I2S 197 * @ms_flg: master mode flag. 198 */ 199 struct stm32_i2s_data { 200 const struct regmap_config *regmap_conf; 201 struct regmap *regmap; 202 struct platform_device *pdev; 203 struct snd_soc_dai_driver *dai_drv; 204 struct snd_dmaengine_dai_dma_data dma_data_tx; 205 struct snd_dmaengine_dai_dma_data dma_data_rx; 206 struct snd_pcm_substream *substream; 207 struct clk *i2sclk; 208 struct clk *pclk; 209 struct clk *x8kclk; 210 struct clk *x11kclk; 211 void __iomem *base; 212 dma_addr_t phys_addr; 213 spinlock_t lock_fd; /* Manage race conditions for full duplex */ 214 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 215 unsigned int mclk_rate; 216 unsigned int fmt; 217 int refcount; 218 int ms_flg; 219 }; 220 221 static irqreturn_t stm32_i2s_isr(int irq, void *devid) 222 { 223 struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid; 224 struct platform_device *pdev = i2s->pdev; 225 u32 sr, ier; 226 unsigned long flags; 227 int err = 0; 228 229 regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr); 230 regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier); 231 232 flags = sr & ier; 233 if (!flags) { 234 dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n", 235 sr, ier); 236 return IRQ_NONE; 237 } 238 239 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, 240 I2S_IFCR_MASK, flags); 241 242 if (flags & I2S_SR_OVR) { 243 dev_dbg(&pdev->dev, "Overrun\n"); 244 err = 1; 245 } 246 247 if (flags & I2S_SR_UDR) { 248 dev_dbg(&pdev->dev, "Underrun\n"); 249 err = 1; 250 } 251 252 if (flags & I2S_SR_TIFRE) 253 dev_dbg(&pdev->dev, "Frame error\n"); 254 255 spin_lock(&i2s->irq_lock); 256 if (err && i2s->substream) 257 snd_pcm_stop_xrun(i2s->substream); 258 spin_unlock(&i2s->irq_lock); 259 260 return IRQ_HANDLED; 261 } 262 263 static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg) 264 { 265 switch (reg) { 266 case STM32_I2S_CR1_REG: 267 case STM32_I2S_CFG1_REG: 268 case STM32_I2S_CFG2_REG: 269 case STM32_I2S_IER_REG: 270 case STM32_I2S_SR_REG: 271 case STM32_I2S_RXDR_REG: 272 case STM32_I2S_CGFR_REG: 273 return true; 274 default: 275 return false; 276 } 277 } 278 279 static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg) 280 { 281 switch (reg) { 282 case STM32_I2S_SR_REG: 283 case STM32_I2S_RXDR_REG: 284 return true; 285 default: 286 return false; 287 } 288 } 289 290 static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg) 291 { 292 switch (reg) { 293 case STM32_I2S_CR1_REG: 294 case STM32_I2S_CFG1_REG: 295 case STM32_I2S_CFG2_REG: 296 case STM32_I2S_IER_REG: 297 case STM32_I2S_IFCR_REG: 298 case STM32_I2S_TXDR_REG: 299 case STM32_I2S_CGFR_REG: 300 return true; 301 default: 302 return false; 303 } 304 } 305 306 static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 307 { 308 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 309 u32 cgfr; 310 u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL | 311 I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK; 312 313 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 314 315 /* 316 * winv = 0 : default behavior (high/low) for all standards 317 * ckpol = 0 for all standards. 318 */ 319 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 320 case SND_SOC_DAIFMT_I2S: 321 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S); 322 break; 323 case SND_SOC_DAIFMT_MSB: 324 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J); 325 break; 326 case SND_SOC_DAIFMT_LSB: 327 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J); 328 break; 329 case SND_SOC_DAIFMT_DSP_A: 330 cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP); 331 break; 332 /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */ 333 default: 334 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 335 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 336 return -EINVAL; 337 } 338 339 /* DAI clock strobing */ 340 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 341 case SND_SOC_DAIFMT_NB_NF: 342 break; 343 case SND_SOC_DAIFMT_IB_NF: 344 cgfr |= I2S_CGFR_CKPOL; 345 break; 346 case SND_SOC_DAIFMT_NB_IF: 347 cgfr |= I2S_CGFR_WSINV; 348 break; 349 case SND_SOC_DAIFMT_IB_IF: 350 cgfr |= I2S_CGFR_CKPOL; 351 cgfr |= I2S_CGFR_WSINV; 352 break; 353 default: 354 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 355 fmt & SND_SOC_DAIFMT_INV_MASK); 356 return -EINVAL; 357 } 358 359 /* DAI clock master masks */ 360 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 361 case SND_SOC_DAIFMT_CBM_CFM: 362 i2s->ms_flg = I2S_MS_SLAVE; 363 break; 364 case SND_SOC_DAIFMT_CBS_CFS: 365 i2s->ms_flg = I2S_MS_MASTER; 366 break; 367 default: 368 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 369 fmt & SND_SOC_DAIFMT_MASTER_MASK); 370 return -EINVAL; 371 } 372 373 i2s->fmt = fmt; 374 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 375 cgfr_mask, cgfr); 376 } 377 378 static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, 379 int clk_id, unsigned int freq, int dir) 380 { 381 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 382 383 dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq); 384 385 if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) { 386 i2s->mclk_rate = freq; 387 388 /* Enable master clock if master mode and mclk-fs are set */ 389 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 390 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE); 391 } 392 393 return 0; 394 } 395 396 static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai, 397 struct snd_pcm_hw_params *params) 398 { 399 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 400 unsigned long i2s_clock_rate; 401 unsigned int tmp, div, real_div, nb_bits, frame_len; 402 unsigned int rate = params_rate(params); 403 int ret; 404 u32 cgfr, cgfr_mask; 405 bool odd; 406 407 if (!(rate % 11025)) 408 clk_set_parent(i2s->i2sclk, i2s->x11kclk); 409 else 410 clk_set_parent(i2s->i2sclk, i2s->x8kclk); 411 i2s_clock_rate = clk_get_rate(i2s->i2sclk); 412 413 /* 414 * mckl = mclk_ratio x ws 415 * i2s mode : mclk_ratio = 256 416 * dsp mode : mclk_ratio = 128 417 * 418 * mclk on 419 * i2s mode : div = i2s_clk / (mclk_ratio * ws) 420 * dsp mode : div = i2s_clk / (mclk_ratio * ws) 421 * mclk off 422 * i2s mode : div = i2s_clk / (nb_bits x ws) 423 * dsp mode : div = i2s_clk / (nb_bits x ws) 424 */ 425 if (i2s->mclk_rate) { 426 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate); 427 } else { 428 frame_len = 32; 429 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 430 SND_SOC_DAIFMT_DSP_A) 431 frame_len = 16; 432 433 /* master clock not enabled */ 434 ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr); 435 if (ret < 0) 436 return ret; 437 438 nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1); 439 tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate)); 440 } 441 442 /* Check the parity of the divider */ 443 odd = tmp & 0x1; 444 445 /* Compute the div prescaler */ 446 div = tmp >> 1; 447 448 cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT); 449 cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD; 450 451 real_div = ((2 * div) + odd); 452 dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n", 453 i2s_clock_rate, rate); 454 dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n", 455 div, odd, real_div); 456 457 if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) { 458 dev_err(cpu_dai->dev, "Wrong divider setting\n"); 459 return -EINVAL; 460 } 461 462 if (!div && !odd) 463 dev_warn(cpu_dai->dev, "real divider forced to 1\n"); 464 465 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 466 cgfr_mask, cgfr); 467 if (ret < 0) 468 return ret; 469 470 /* Set bitclock and frameclock to their inactive state */ 471 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG, 472 I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR); 473 } 474 475 static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai, 476 struct snd_pcm_hw_params *params, 477 struct snd_pcm_substream *substream) 478 { 479 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 480 int format = params_width(params); 481 u32 cfgr, cfgr_mask, cfg1; 482 unsigned int fthlv; 483 int ret; 484 485 switch (format) { 486 case 16: 487 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16); 488 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN; 489 break; 490 case 32: 491 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) | 492 I2S_CGFR_CHLEN; 493 cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN; 494 break; 495 default: 496 dev_err(cpu_dai->dev, "Unexpected format %d", format); 497 return -EINVAL; 498 } 499 500 if (STM32_I2S_IS_SLAVE(i2s)) { 501 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE); 502 503 /* As data length is either 16 or 32 bits, fixch always set */ 504 cfgr |= I2S_CGFR_FIXCH; 505 cfgr_mask |= I2S_CGFR_FIXCH; 506 } else { 507 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER); 508 } 509 cfgr_mask |= I2S_CGFR_I2SCFG_MASK; 510 511 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 512 cfgr_mask, cfgr); 513 if (ret < 0) 514 return ret; 515 516 fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4; 517 cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1); 518 519 return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG, 520 I2S_CFG1_FTHVL_MASK, cfg1); 521 } 522 523 static int stm32_i2s_startup(struct snd_pcm_substream *substream, 524 struct snd_soc_dai *cpu_dai) 525 { 526 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 527 unsigned long flags; 528 int ret; 529 530 spin_lock_irqsave(&i2s->irq_lock, flags); 531 i2s->substream = substream; 532 spin_unlock_irqrestore(&i2s->irq_lock, flags); 533 534 if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A) 535 snd_pcm_hw_constraint_single(substream->runtime, 536 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 537 538 ret = clk_prepare_enable(i2s->i2sclk); 539 if (ret < 0) { 540 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 541 return ret; 542 } 543 544 return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, 545 I2S_IFCR_MASK, I2S_IFCR_MASK); 546 } 547 548 static int stm32_i2s_hw_params(struct snd_pcm_substream *substream, 549 struct snd_pcm_hw_params *params, 550 struct snd_soc_dai *cpu_dai) 551 { 552 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 553 int ret; 554 555 ret = stm32_i2s_configure(cpu_dai, params, substream); 556 if (ret < 0) { 557 dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret); 558 return ret; 559 } 560 561 if (STM32_I2S_IS_MASTER(i2s)) 562 ret = stm32_i2s_configure_clock(cpu_dai, params); 563 564 return ret; 565 } 566 567 static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 568 struct snd_soc_dai *cpu_dai) 569 { 570 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 571 bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 572 u32 cfg1_mask, ier; 573 int ret; 574 575 switch (cmd) { 576 case SNDRV_PCM_TRIGGER_START: 577 case SNDRV_PCM_TRIGGER_RESUME: 578 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 579 /* Enable i2s */ 580 dev_dbg(cpu_dai->dev, "start I2S %s\n", 581 playback_flg ? "playback" : "capture"); 582 583 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN; 584 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG, 585 cfg1_mask, cfg1_mask); 586 587 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG, 588 I2S_CR1_SPE, I2S_CR1_SPE); 589 if (ret < 0) { 590 dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret); 591 return ret; 592 } 593 594 ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG, 595 I2S_CR1_CSTART, I2S_CR1_CSTART); 596 if (ret < 0) { 597 dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret); 598 return ret; 599 } 600 601 regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, 602 I2S_IFCR_MASK, I2S_IFCR_MASK); 603 604 spin_lock(&i2s->lock_fd); 605 i2s->refcount++; 606 if (playback_flg) { 607 ier = I2S_IER_UDRIE; 608 } else { 609 ier = I2S_IER_OVRIE; 610 611 if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1) 612 /* dummy write to gate bus clocks */ 613 regmap_write(i2s->regmap, 614 STM32_I2S_TXDR_REG, 0); 615 } 616 spin_unlock(&i2s->lock_fd); 617 618 if (STM32_I2S_IS_SLAVE(i2s)) 619 ier |= I2S_IER_TIFREIE; 620 621 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier); 622 break; 623 case SNDRV_PCM_TRIGGER_STOP: 624 case SNDRV_PCM_TRIGGER_SUSPEND: 625 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 626 dev_dbg(cpu_dai->dev, "stop I2S %s\n", 627 playback_flg ? "playback" : "capture"); 628 629 if (playback_flg) 630 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, 631 I2S_IER_UDRIE, 632 (unsigned int)~I2S_IER_UDRIE); 633 else 634 regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, 635 I2S_IER_OVRIE, 636 (unsigned int)~I2S_IER_OVRIE); 637 638 spin_lock(&i2s->lock_fd); 639 i2s->refcount--; 640 if (i2s->refcount) { 641 spin_unlock(&i2s->lock_fd); 642 break; 643 } 644 645 ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG, 646 I2S_CR1_SPE, 0); 647 if (ret < 0) { 648 dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret); 649 spin_unlock(&i2s->lock_fd); 650 return ret; 651 } 652 spin_unlock(&i2s->lock_fd); 653 654 cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN; 655 regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG, 656 cfg1_mask, 0); 657 break; 658 default: 659 return -EINVAL; 660 } 661 662 return 0; 663 } 664 665 static void stm32_i2s_shutdown(struct snd_pcm_substream *substream, 666 struct snd_soc_dai *cpu_dai) 667 { 668 struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); 669 unsigned long flags; 670 671 regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 672 I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE); 673 674 clk_disable_unprepare(i2s->i2sclk); 675 676 spin_lock_irqsave(&i2s->irq_lock, flags); 677 i2s->substream = NULL; 678 spin_unlock_irqrestore(&i2s->irq_lock, flags); 679 } 680 681 static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai) 682 { 683 struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev); 684 struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx; 685 struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx; 686 687 /* Buswidth will be set by framework */ 688 dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 689 dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG; 690 dma_data_tx->maxburst = 1; 691 dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 692 dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG; 693 dma_data_rx->maxburst = 1; 694 695 snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx); 696 697 return 0; 698 } 699 700 static const struct regmap_config stm32_h7_i2s_regmap_conf = { 701 .reg_bits = 32, 702 .reg_stride = 4, 703 .val_bits = 32, 704 .max_register = STM32_I2S_CGFR_REG, 705 .readable_reg = stm32_i2s_readable_reg, 706 .volatile_reg = stm32_i2s_volatile_reg, 707 .writeable_reg = stm32_i2s_writeable_reg, 708 .fast_io = true, 709 .cache_type = REGCACHE_FLAT, 710 }; 711 712 static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = { 713 .set_sysclk = stm32_i2s_set_sysclk, 714 .set_fmt = stm32_i2s_set_dai_fmt, 715 .startup = stm32_i2s_startup, 716 .hw_params = stm32_i2s_hw_params, 717 .trigger = stm32_i2s_trigger, 718 .shutdown = stm32_i2s_shutdown, 719 }; 720 721 static const struct snd_pcm_hardware stm32_i2s_pcm_hw = { 722 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 723 .buffer_bytes_max = 8 * PAGE_SIZE, 724 .period_bytes_min = 1024, 725 .period_bytes_max = 4 * PAGE_SIZE, 726 .periods_min = 2, 727 .periods_max = 8, 728 }; 729 730 static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = { 731 .pcm_hardware = &stm32_i2s_pcm_hw, 732 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 733 .prealloc_buffer_size = PAGE_SIZE * 8, 734 }; 735 736 static const struct snd_soc_component_driver stm32_i2s_component = { 737 .name = "stm32-i2s", 738 }; 739 740 static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream, 741 char *stream_name) 742 { 743 stream->stream_name = stream_name; 744 stream->channels_min = 1; 745 stream->channels_max = 2; 746 stream->rates = SNDRV_PCM_RATE_8000_192000; 747 stream->formats = SNDRV_PCM_FMTBIT_S16_LE | 748 SNDRV_PCM_FMTBIT_S32_LE; 749 } 750 751 static int stm32_i2s_dais_init(struct platform_device *pdev, 752 struct stm32_i2s_data *i2s) 753 { 754 struct snd_soc_dai_driver *dai_ptr; 755 756 dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver), 757 GFP_KERNEL); 758 if (!dai_ptr) 759 return -ENOMEM; 760 761 dai_ptr->probe = stm32_i2s_dai_probe; 762 dai_ptr->ops = &stm32_i2s_pcm_dai_ops; 763 dai_ptr->id = 1; 764 stm32_i2s_dai_init(&dai_ptr->playback, "playback"); 765 stm32_i2s_dai_init(&dai_ptr->capture, "capture"); 766 i2s->dai_drv = dai_ptr; 767 768 return 0; 769 } 770 771 static const struct of_device_id stm32_i2s_ids[] = { 772 { 773 .compatible = "st,stm32h7-i2s", 774 .data = &stm32_h7_i2s_regmap_conf 775 }, 776 {}, 777 }; 778 779 static int stm32_i2s_parse_dt(struct platform_device *pdev, 780 struct stm32_i2s_data *i2s) 781 { 782 struct device_node *np = pdev->dev.of_node; 783 const struct of_device_id *of_id; 784 struct reset_control *rst; 785 struct resource *res; 786 int irq, ret; 787 788 if (!np) 789 return -ENODEV; 790 791 of_id = of_match_device(stm32_i2s_ids, &pdev->dev); 792 if (of_id) 793 i2s->regmap_conf = (const struct regmap_config *)of_id->data; 794 else 795 return -EINVAL; 796 797 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 798 i2s->base = devm_ioremap_resource(&pdev->dev, res); 799 if (IS_ERR(i2s->base)) 800 return PTR_ERR(i2s->base); 801 802 i2s->phys_addr = res->start; 803 804 /* Get clocks */ 805 i2s->pclk = devm_clk_get(&pdev->dev, "pclk"); 806 if (IS_ERR(i2s->pclk)) { 807 dev_err(&pdev->dev, "Could not get pclk\n"); 808 return PTR_ERR(i2s->pclk); 809 } 810 811 i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk"); 812 if (IS_ERR(i2s->i2sclk)) { 813 dev_err(&pdev->dev, "Could not get i2sclk\n"); 814 return PTR_ERR(i2s->i2sclk); 815 } 816 817 i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k"); 818 if (IS_ERR(i2s->x8kclk)) { 819 dev_err(&pdev->dev, "missing x8k parent clock\n"); 820 return PTR_ERR(i2s->x8kclk); 821 } 822 823 i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k"); 824 if (IS_ERR(i2s->x11kclk)) { 825 dev_err(&pdev->dev, "missing x11k parent clock\n"); 826 return PTR_ERR(i2s->x11kclk); 827 } 828 829 /* Get irqs */ 830 irq = platform_get_irq(pdev, 0); 831 if (irq < 0) { 832 if (irq != -EPROBE_DEFER) 833 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 834 return irq; 835 } 836 837 ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT, 838 dev_name(&pdev->dev), i2s); 839 if (ret) { 840 dev_err(&pdev->dev, "irq request returned %d\n", ret); 841 return ret; 842 } 843 844 /* Reset */ 845 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 846 if (!IS_ERR(rst)) { 847 reset_control_assert(rst); 848 udelay(2); 849 reset_control_deassert(rst); 850 } 851 852 return 0; 853 } 854 855 static int stm32_i2s_probe(struct platform_device *pdev) 856 { 857 struct stm32_i2s_data *i2s; 858 int ret; 859 860 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 861 if (!i2s) 862 return -ENOMEM; 863 864 ret = stm32_i2s_parse_dt(pdev, i2s); 865 if (ret) 866 return ret; 867 868 i2s->pdev = pdev; 869 i2s->ms_flg = I2S_MS_NOT_SET; 870 spin_lock_init(&i2s->lock_fd); 871 spin_lock_init(&i2s->irq_lock); 872 platform_set_drvdata(pdev, i2s); 873 874 ret = stm32_i2s_dais_init(pdev, i2s); 875 if (ret) 876 return ret; 877 878 i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk", 879 i2s->base, i2s->regmap_conf); 880 if (IS_ERR(i2s->regmap)) { 881 dev_err(&pdev->dev, "regmap init failed\n"); 882 return PTR_ERR(i2s->regmap); 883 } 884 885 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_i2s_component, 886 i2s->dai_drv, 1); 887 if (ret) 888 return ret; 889 890 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, 891 &stm32_i2s_pcm_config, 0); 892 if (ret) 893 return ret; 894 895 /* Set SPI/I2S in i2s mode */ 896 return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, 897 I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD); 898 } 899 900 MODULE_DEVICE_TABLE(of, stm32_i2s_ids); 901 902 #ifdef CONFIG_PM_SLEEP 903 static int stm32_i2s_suspend(struct device *dev) 904 { 905 struct stm32_i2s_data *i2s = dev_get_drvdata(dev); 906 907 regcache_cache_only(i2s->regmap, true); 908 regcache_mark_dirty(i2s->regmap); 909 910 return 0; 911 } 912 913 static int stm32_i2s_resume(struct device *dev) 914 { 915 struct stm32_i2s_data *i2s = dev_get_drvdata(dev); 916 917 regcache_cache_only(i2s->regmap, false); 918 return regcache_sync(i2s->regmap); 919 } 920 #endif /* CONFIG_PM_SLEEP */ 921 922 static const struct dev_pm_ops stm32_i2s_pm_ops = { 923 SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume) 924 }; 925 926 static struct platform_driver stm32_i2s_driver = { 927 .driver = { 928 .name = "st,stm32-i2s", 929 .of_match_table = stm32_i2s_ids, 930 .pm = &stm32_i2s_pm_ops, 931 }, 932 .probe = stm32_i2s_probe, 933 }; 934 935 module_platform_driver(stm32_i2s_driver); 936 937 MODULE_DESCRIPTION("STM32 Soc i2s Interface"); 938 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 939 MODULE_ALIAS("platform:stm32-i2s"); 940 MODULE_LICENSE("GPL v2"); 941