1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2021 Mediatek Inc. All rights reserved. 4 // 5 // Author: YC Hung <yc.hung@mediatek.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on mt8195 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/firmware.h> 14 #include <linux/io.h> 15 #include <linux/of_platform.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_reserved_mem.h> 20 #include <linux/module.h> 21 22 #include <sound/sof.h> 23 #include <sound/sof/xtensa.h> 24 #include "../../ops.h" 25 #include "../../sof-of-dev.h" 26 #include "../../sof-audio.h" 27 #include "../adsp_helper.h" 28 #include "../mtk-adsp-common.h" 29 #include "mt8195.h" 30 #include "mt8195-clk.h" 31 32 static int mt8195_get_mailbox_offset(struct snd_sof_dev *sdev) 33 { 34 return MBOX_OFFSET; 35 } 36 37 static int mt8195_get_window_offset(struct snd_sof_dev *sdev, u32 id) 38 { 39 return MBOX_OFFSET; 40 } 41 42 static int mt8195_send_msg(struct snd_sof_dev *sdev, 43 struct snd_sof_ipc_msg *msg) 44 { 45 struct adsp_priv *priv = sdev->pdata->hw_pdata; 46 47 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 48 msg->msg_size); 49 50 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ); 51 } 52 53 static void mt8195_get_reply(struct snd_sof_dev *sdev) 54 { 55 struct snd_sof_ipc_msg *msg = sdev->msg; 56 struct sof_ipc_reply reply; 57 int ret = 0; 58 59 if (!msg) { 60 dev_warn(sdev->dev, "unexpected ipc interrupt\n"); 61 return; 62 } 63 64 /* get reply */ 65 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 66 if (reply.error < 0) { 67 memcpy(msg->reply_data, &reply, sizeof(reply)); 68 ret = reply.error; 69 } else { 70 /* reply has correct size? */ 71 if (reply.hdr.size != msg->reply_size) { 72 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 73 msg->reply_size, reply.hdr.size); 74 ret = -EINVAL; 75 } 76 77 /* read the message */ 78 if (msg->reply_size > 0) 79 sof_mailbox_read(sdev, sdev->host_box.offset, 80 msg->reply_data, msg->reply_size); 81 } 82 83 msg->reply_error = ret; 84 } 85 86 static void mt8195_dsp_handle_reply(struct mtk_adsp_ipc *ipc) 87 { 88 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc); 89 unsigned long flags; 90 91 spin_lock_irqsave(&priv->sdev->ipc_lock, flags); 92 mt8195_get_reply(priv->sdev); 93 snd_sof_ipc_reply(priv->sdev, 0); 94 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); 95 } 96 97 static void mt8195_dsp_handle_request(struct mtk_adsp_ipc *ipc) 98 { 99 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc); 100 u32 p; /* panic code */ 101 int ret; 102 103 /* Read the message from the debug box. */ 104 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, 105 &p, sizeof(p)); 106 107 /* Check to see if the message is a panic code 0x0dead*** */ 108 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 109 snd_sof_dsp_panic(priv->sdev, p, true); 110 } else { 111 snd_sof_ipc_msgs_rx(priv->sdev); 112 113 /* tell DSP cmd is done */ 114 ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP); 115 if (ret) 116 dev_err(priv->dev, "request send ipc failed"); 117 } 118 } 119 120 static struct mtk_adsp_ipc_ops dsp_ops = { 121 .handle_reply = mt8195_dsp_handle_reply, 122 .handle_request = mt8195_dsp_handle_request, 123 }; 124 125 static int platform_parse_resource(struct platform_device *pdev, void *data) 126 { 127 struct resource *mmio; 128 struct resource res; 129 struct device_node *mem_region; 130 struct device *dev = &pdev->dev; 131 struct mtk_adsp_chip_info *adsp = data; 132 int ret; 133 134 mem_region = of_parse_phandle(dev->of_node, "memory-region", 0); 135 if (!mem_region) { 136 dev_err(dev, "no dma memory-region phandle\n"); 137 return -ENODEV; 138 } 139 140 ret = of_address_to_resource(mem_region, 0, &res); 141 of_node_put(mem_region); 142 if (ret) { 143 dev_err(dev, "of_address_to_resource dma failed\n"); 144 return ret; 145 } 146 147 dev_dbg(dev, "DMA %pR\n", &res); 148 149 ret = of_reserved_mem_device_init(dev); 150 if (ret) { 151 dev_err(dev, "of_reserved_mem_device_init failed\n"); 152 return ret; 153 } 154 155 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1); 156 if (!mem_region) { 157 dev_err(dev, "no memory-region sysmem phandle\n"); 158 return -ENODEV; 159 } 160 161 ret = of_address_to_resource(mem_region, 0, &res); 162 of_node_put(mem_region); 163 if (ret) { 164 dev_err(dev, "of_address_to_resource sysmem failed\n"); 165 return ret; 166 } 167 168 adsp->pa_dram = (phys_addr_t)res.start; 169 adsp->dramsize = resource_size(&res); 170 if (adsp->pa_dram & DRAM_REMAP_MASK) { 171 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n", 172 (u32)adsp->pa_dram); 173 return -EINVAL; 174 } 175 176 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) { 177 dev_err(dev, "adsp memory(%#x) is not enough for share\n", 178 adsp->dramsize); 179 return -EINVAL; 180 } 181 182 dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n", 183 &adsp->pa_dram, adsp->dramsize); 184 185 /* Parse CFG base */ 186 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 187 if (!mmio) { 188 dev_err(dev, "no ADSP-CFG register resource\n"); 189 return -ENXIO; 190 } 191 /* remap for DSP register accessing */ 192 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio); 193 if (IS_ERR(adsp->va_cfgreg)) 194 return PTR_ERR(adsp->va_cfgreg); 195 196 adsp->pa_cfgreg = (phys_addr_t)mmio->start; 197 adsp->cfgregsize = resource_size(mmio); 198 199 dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n", 200 adsp->va_cfgreg, adsp->cfgregsize); 201 202 /* Parse SRAM */ 203 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); 204 if (!mmio) { 205 dev_err(dev, "no SRAM resource\n"); 206 return -ENXIO; 207 } 208 209 adsp->pa_sram = (phys_addr_t)mmio->start; 210 adsp->sramsize = resource_size(mmio); 211 if (adsp->sramsize < TOTAL_SIZE_SHARED_SRAM_FROM_TAIL) { 212 dev_err(dev, "adsp SRAM(%#x) is not enough for share\n", 213 adsp->sramsize); 214 return -EINVAL; 215 } 216 217 dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize); 218 219 return ret; 220 } 221 222 static int adsp_sram_power_on(struct device *dev, bool on) 223 { 224 void __iomem *va_dspsysreg; 225 u32 srampool_con; 226 227 va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4); 228 if (!va_dspsysreg) { 229 dev_err(dev, "failed to ioremap sram pool base %#x\n", 230 ADSP_SRAM_POOL_CON); 231 return -ENOMEM; 232 } 233 234 srampool_con = readl(va_dspsysreg); 235 if (on) 236 writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg); 237 else 238 writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg); 239 240 iounmap(va_dspsysreg); 241 return 0; 242 } 243 244 /* Init the basic DSP DRAM address */ 245 static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp) 246 { 247 void __iomem *vaddr_emi_map; 248 int offset; 249 250 if (!adsp) 251 return -ENXIO; 252 253 vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4); 254 if (!vaddr_emi_map) { 255 dev_err(dev, "failed to ioremap emi map base %#x\n", 256 DSP_EMI_MAP_ADDR); 257 return -ENOMEM; 258 } 259 260 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW; 261 adsp->dram_offset = offset; 262 offset >>= DRAM_REMAP_SHIFT; 263 dev_dbg(dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset); 264 writel(offset, vaddr_emi_map); 265 if (offset != readl(vaddr_emi_map)) { 266 dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map)); 267 return -EIO; 268 } 269 270 return 0; 271 } 272 273 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data) 274 { 275 struct device *dev = &pdev->dev; 276 struct mtk_adsp_chip_info *adsp = data; 277 u32 shared_size; 278 279 /* remap shared-dram base to be non-cachable */ 280 shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL; 281 adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size; 282 if (adsp->va_dram) { 283 adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size; 284 } else { 285 adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram, 286 shared_size); 287 if (!adsp->shared_dram) { 288 dev_err(dev, "ioremap failed for shared DRAM\n"); 289 return -ENOMEM; 290 } 291 } 292 dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n", 293 adsp->shared_dram, &adsp->pa_shared_dram, shared_size); 294 295 return 0; 296 } 297 298 static int mt8195_run(struct snd_sof_dev *sdev) 299 { 300 u32 adsp_bootup_addr; 301 302 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW; 303 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr); 304 sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr); 305 306 return 0; 307 } 308 309 static int mt8195_dsp_probe(struct snd_sof_dev *sdev) 310 { 311 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 312 struct adsp_priv *priv; 313 int ret; 314 315 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 316 if (!priv) 317 return -ENOMEM; 318 319 sdev->pdata->hw_pdata = priv; 320 priv->dev = sdev->dev; 321 priv->sdev = sdev; 322 323 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL); 324 if (!priv->adsp) 325 return -ENOMEM; 326 327 ret = platform_parse_resource(pdev, priv->adsp); 328 if (ret) 329 return ret; 330 331 ret = mt8195_adsp_init_clock(sdev); 332 if (ret) { 333 dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n"); 334 return -EINVAL; 335 } 336 337 ret = adsp_clock_on(sdev); 338 if (ret) { 339 dev_err(sdev->dev, "adsp_clock_on fail!\n"); 340 return -EINVAL; 341 } 342 343 ret = adsp_sram_power_on(sdev->dev, true); 344 if (ret) { 345 dev_err(sdev->dev, "adsp_sram_power_on fail!\n"); 346 goto exit_clk_disable; 347 } 348 349 ret = adsp_memory_remap_init(&pdev->dev, priv->adsp); 350 if (ret) { 351 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n"); 352 goto err_adsp_sram_power_off; 353 } 354 355 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, 356 priv->adsp->pa_sram, 357 priv->adsp->sramsize); 358 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { 359 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 360 &priv->adsp->pa_sram, priv->adsp->sramsize); 361 ret = -EINVAL; 362 goto err_adsp_sram_power_off; 363 } 364 365 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, 366 priv->adsp->pa_dram, 367 priv->adsp->dramsize); 368 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { 369 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n", 370 &priv->adsp->pa_dram, priv->adsp->dramsize); 371 ret = -EINVAL; 372 goto err_adsp_sram_power_off; 373 } 374 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM]; 375 376 ret = adsp_shared_base_ioremap(pdev, priv->adsp); 377 if (ret) { 378 dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n"); 379 goto err_adsp_sram_power_off; 380 } 381 382 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg; 383 384 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM; 385 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 386 387 /* set default mailbox offset for FW ready message */ 388 sdev->dsp_box.offset = mt8195_get_mailbox_offset(sdev); 389 390 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc", 391 PLATFORM_DEVID_NONE, 392 pdev, sizeof(*pdev)); 393 if (IS_ERR(priv->ipc_dev)) { 394 ret = PTR_ERR(priv->ipc_dev); 395 dev_err(sdev->dev, "failed to register mtk-adsp-ipc device\n"); 396 goto err_adsp_sram_power_off; 397 } 398 399 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); 400 if (!priv->dsp_ipc) { 401 ret = -EPROBE_DEFER; 402 dev_err(sdev->dev, "failed to get drvdata\n"); 403 goto exit_pdev_unregister; 404 } 405 406 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv); 407 priv->dsp_ipc->ops = &dsp_ops; 408 409 return 0; 410 411 exit_pdev_unregister: 412 platform_device_unregister(priv->ipc_dev); 413 err_adsp_sram_power_off: 414 adsp_sram_power_on(&pdev->dev, false); 415 exit_clk_disable: 416 adsp_clock_off(sdev); 417 418 return ret; 419 } 420 421 static int mt8195_dsp_shutdown(struct snd_sof_dev *sdev) 422 { 423 return snd_sof_suspend(sdev->dev); 424 } 425 426 static int mt8195_dsp_remove(struct snd_sof_dev *sdev) 427 { 428 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 429 struct adsp_priv *priv = sdev->pdata->hw_pdata; 430 431 platform_device_unregister(priv->ipc_dev); 432 adsp_sram_power_on(&pdev->dev, false); 433 adsp_clock_off(sdev); 434 435 return 0; 436 } 437 438 static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 439 { 440 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev); 441 int ret; 442 443 /* stall and reset dsp */ 444 sof_hifixdsp_shutdown(sdev); 445 446 /* power down adsp sram */ 447 ret = adsp_sram_power_on(&pdev->dev, false); 448 if (ret) { 449 dev_err(sdev->dev, "adsp_sram_power_off fail!\n"); 450 return ret; 451 } 452 453 /* turn off adsp clock */ 454 return adsp_clock_off(sdev); 455 } 456 457 static int mt8195_dsp_resume(struct snd_sof_dev *sdev) 458 { 459 int ret; 460 461 /* turn on adsp clock */ 462 ret = adsp_clock_on(sdev); 463 if (ret) { 464 dev_err(sdev->dev, "adsp_clock_on fail!\n"); 465 return ret; 466 } 467 468 /* power on adsp sram */ 469 ret = adsp_sram_power_on(sdev->dev, true); 470 if (ret) 471 dev_err(sdev->dev, "adsp_sram_power_on fail!\n"); 472 473 return ret; 474 } 475 476 /* on mt8195 there is 1 to 1 match between type and BAR idx */ 477 static int mt8195_get_bar_index(struct snd_sof_dev *sdev, u32 type) 478 { 479 return type; 480 } 481 482 static int mt8195_ipc_msg_data(struct snd_sof_dev *sdev, 483 struct snd_pcm_substream *substream, 484 void *p, size_t sz) 485 { 486 sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz); 487 return 0; 488 } 489 490 static void mt8195_adsp_dump(struct snd_sof_dev *sdev, u32 flags) 491 { 492 u32 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, dbg_inst; 493 u32 dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo, swrest; 494 495 /* dump debug registers */ 496 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC); 497 dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA); 498 dbg_bus0 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0); 499 dbg_bus1 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS1); 500 dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST); 501 dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT); 502 dbg_ls1stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS1STAT); 503 faultbus = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTBUS); 504 faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO); 505 swrest = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_RESET_SW); 506 507 dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, bus0 %#x, bus1 %#x, swrest %#x", 508 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, swrest); 509 dev_info(sdev->dev, "dbg_inst %#x, ls0stat %#x, ls1stat %#x, faultbus %#x, faultinfo %#x", 510 dbg_inst, dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo); 511 512 mtk_adsp_dump(sdev, flags); 513 } 514 515 static struct snd_soc_dai_driver mt8195_dai[] = { 516 { 517 .name = "SOF_DL2", 518 .playback = { 519 .channels_min = 1, 520 .channels_max = 2, 521 }, 522 }, 523 { 524 .name = "SOF_DL3", 525 .playback = { 526 .channels_min = 1, 527 .channels_max = 2, 528 }, 529 }, 530 { 531 .name = "SOF_UL4", 532 .capture = { 533 .channels_min = 1, 534 .channels_max = 2, 535 }, 536 }, 537 { 538 .name = "SOF_UL5", 539 .capture = { 540 .channels_min = 1, 541 .channels_max = 2, 542 }, 543 }, 544 }; 545 546 /* mt8195 ops */ 547 static struct snd_sof_dsp_ops sof_mt8195_ops = { 548 /* probe and remove */ 549 .probe = mt8195_dsp_probe, 550 .remove = mt8195_dsp_remove, 551 .shutdown = mt8195_dsp_shutdown, 552 553 /* DSP core boot */ 554 .run = mt8195_run, 555 556 /* Block IO */ 557 .block_read = sof_block_read, 558 .block_write = sof_block_write, 559 560 /* Register IO */ 561 .write = sof_io_write, 562 .read = sof_io_read, 563 .write64 = sof_io_write64, 564 .read64 = sof_io_read64, 565 566 /* ipc */ 567 .send_msg = mt8195_send_msg, 568 .get_mailbox_offset = mt8195_get_mailbox_offset, 569 .get_window_offset = mt8195_get_window_offset, 570 .ipc_msg_data = mt8195_ipc_msg_data, 571 .set_stream_data_offset = sof_set_stream_data_offset, 572 573 /* misc */ 574 .get_bar_index = mt8195_get_bar_index, 575 576 /* firmware loading */ 577 .load_firmware = snd_sof_load_firmware_memcpy, 578 579 /* Firmware ops */ 580 .dsp_arch_ops = &sof_xtensa_arch_ops, 581 582 /* Debug information */ 583 .dbg_dump = mt8195_adsp_dump, 584 585 /* DAI drivers */ 586 .drv = mt8195_dai, 587 .num_drv = ARRAY_SIZE(mt8195_dai), 588 589 /* PM */ 590 .suspend = mt8195_dsp_suspend, 591 .resume = mt8195_dsp_resume, 592 593 /* ALSA HW info flags */ 594 .hw_info = SNDRV_PCM_INFO_MMAP | 595 SNDRV_PCM_INFO_MMAP_VALID | 596 SNDRV_PCM_INFO_INTERLEAVED | 597 SNDRV_PCM_INFO_PAUSE | 598 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 599 }; 600 601 static const struct sof_dev_desc sof_of_mt8195_desc = { 602 .ipc_supported_mask = BIT(SOF_IPC), 603 .ipc_default = SOF_IPC, 604 .default_fw_path = { 605 [SOF_IPC] = "mediatek/sof", 606 }, 607 .default_tplg_path = { 608 [SOF_IPC] = "mediatek/sof-tplg", 609 }, 610 .default_fw_filename = { 611 [SOF_IPC] = "sof-mt8195.ri", 612 }, 613 .nocodec_tplg_filename = "sof-mt8195-nocodec.tplg", 614 .ops = &sof_mt8195_ops, 615 .ipc_timeout = 1000, 616 }; 617 618 static const struct of_device_id sof_of_mt8195_ids[] = { 619 { .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc}, 620 { } 621 }; 622 MODULE_DEVICE_TABLE(of, sof_of_mt8195_ids); 623 624 /* DT driver definition */ 625 static struct platform_driver snd_sof_of_mt8195_driver = { 626 .probe = sof_of_probe, 627 .remove = sof_of_remove, 628 .shutdown = sof_of_shutdown, 629 .driver = { 630 .name = "sof-audio-of-mt8195", 631 .pm = &sof_of_pm, 632 .of_match_table = sof_of_mt8195_ids, 633 }, 634 }; 635 module_platform_driver(snd_sof_of_mt8195_driver); 636 637 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 638 MODULE_LICENSE("Dual BSD/GPL"); 639