1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2022 Intel Corporation. All rights reserved. 7 // 8 // Authors: Rander Wang <rander.wang@linux.intel.com> 9 // Peter Ujfalusi <peter.ujfalusi@linux.intel.com> 10 // 11 #include <linux/firmware.h> 12 #include <sound/sof/header.h> 13 #include <sound/sof/ipc4/header.h> 14 #include "sof-priv.h" 15 #include "sof-audio.h" 16 #include "ipc4-fw-reg.h" 17 #include "ipc4-priv.h" 18 #include "ops.h" 19 20 #ifdef DEBUG_VERBOSE 21 #define sof_ipc4_dump_payload(sdev, ipc_data, size) \ 22 print_hex_dump_debug("Message payload: ", \ 23 DUMP_PREFIX_OFFSET, \ 24 16, 4, ipc_data, size, false) 25 #else 26 #define sof_ipc4_dump_payload(sdev, ipc_data, size) do { } while (0) 27 #endif 28 29 static const struct sof_ipc4_fw_status { 30 int status; 31 char *msg; 32 } ipc4_status[] = { 33 {0, "The operation was successful"}, 34 {1, "Invalid parameter specified"}, 35 {2, "Unknown message type specified"}, 36 {3, "Not enough space in the IPC reply buffer to complete the request"}, 37 {4, "The system or resource is busy"}, 38 {5, "Replaced ADSP IPC PENDING (unused)"}, 39 {6, "Unknown error while processing the request"}, 40 {7, "Unsupported operation requested"}, 41 {8, "Reserved (ADSP_STAGE_UNINITIALIZED removed)"}, 42 {9, "Specified resource not found"}, 43 {10, "A resource's ID requested to be created is already assigned"}, 44 {11, "Reserved (ADSP_IPC_OUT_OF_MIPS removed)"}, 45 {12, "Required resource is in invalid state"}, 46 {13, "Requested power transition failed to complete"}, 47 {14, "Manifest of the library being loaded is invalid"}, 48 {15, "Requested service or data is unavailable on the target platform"}, 49 {42, "Library target address is out of storage memory range"}, 50 {43, "Reserved"}, 51 {44, "Image verification by CSE failed"}, 52 {100, "General module management error"}, 53 {101, "Module loading failed"}, 54 {102, "Integrity check of the loaded module content failed"}, 55 {103, "Attempt to unload code of the module in use"}, 56 {104, "Other failure of module instance initialization request"}, 57 {105, "Reserved (ADSP_IPC_OUT_OF_MIPS removed)"}, 58 {106, "Reserved (ADSP_IPC_CONFIG_GET_ERROR removed)"}, 59 {107, "Reserved (ADSP_IPC_CONFIG_SET_ERROR removed)"}, 60 {108, "Reserved (ADSP_IPC_LARGE_CONFIG_GET_ERROR removed)"}, 61 {109, "Reserved (ADSP_IPC_LARGE_CONFIG_SET_ERROR removed)"}, 62 {110, "Invalid (out of range) module ID provided"}, 63 {111, "Invalid module instance ID provided"}, 64 {112, "Invalid queue (pin) ID provided"}, 65 {113, "Invalid destination queue (pin) ID provided"}, 66 {114, "Reserved (ADSP_IPC_BIND_UNBIND_DST_SINK_UNSUPPORTED removed)"}, 67 {115, "Reserved (ADSP_IPC_UNLOAD_INST_EXISTS removed)"}, 68 {116, "Invalid target code ID provided"}, 69 {117, "Injection DMA buffer is too small for probing the input pin"}, 70 {118, "Extraction DMA buffer is too small for probing the output pin"}, 71 {120, "Invalid ID of configuration item provided in TLV list"}, 72 {121, "Invalid length of configuration item provided in TLV list"}, 73 {122, "Invalid structure of configuration item provided"}, 74 {140, "Initialization of DMA Gateway failed"}, 75 {141, "Invalid ID of gateway provided"}, 76 {142, "Setting state of DMA Gateway failed"}, 77 {143, "DMA_CONTROL message targeting gateway not allocated yet"}, 78 {150, "Attempt to configure SCLK while I2S port is running"}, 79 {151, "Attempt to configure MCLK while I2S port is running"}, 80 {152, "Attempt to stop SCLK that is not running"}, 81 {153, "Attempt to stop MCLK that is not running"}, 82 {160, "Reserved (ADSP_IPC_PIPELINE_NOT_INITIALIZED removed)"}, 83 {161, "Reserved (ADSP_IPC_PIPELINE_NOT_EXIST removed)"}, 84 {162, "Reserved (ADSP_IPC_PIPELINE_SAVE_FAILED removed)"}, 85 {163, "Reserved (ADSP_IPC_PIPELINE_RESTORE_FAILED removed)"}, 86 {165, "Reserved (ADSP_IPC_PIPELINE_ALREADY_EXISTS removed)"}, 87 }; 88 89 static int sof_ipc4_check_reply_status(struct snd_sof_dev *sdev, u32 status) 90 { 91 int i, ret; 92 93 status &= SOF_IPC4_REPLY_STATUS; 94 95 if (!status) 96 return 0; 97 98 for (i = 0; i < ARRAY_SIZE(ipc4_status); i++) { 99 if (ipc4_status[i].status == status) { 100 dev_err(sdev->dev, "FW reported error: %u - %s\n", 101 status, ipc4_status[i].msg); 102 goto to_errno; 103 } 104 } 105 106 if (i == ARRAY_SIZE(ipc4_status)) 107 dev_err(sdev->dev, "FW reported error: %u - Unknown\n", status); 108 109 to_errno: 110 switch (status) { 111 case 8: 112 case 11: 113 case 105 ... 109: 114 case 114 ... 115: 115 case 160 ... 163: 116 case 165: 117 ret = -ENOENT; 118 break; 119 case 4: 120 case 150: 121 case 151: 122 ret = -EBUSY; 123 break; 124 default: 125 ret = -EINVAL; 126 break; 127 } 128 129 return ret; 130 } 131 132 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC) 133 #define DBG_IPC4_MSG_TYPE_ENTRY(type) [SOF_IPC4_##type] = #type 134 static const char * const ipc4_dbg_mod_msg_type[] = { 135 DBG_IPC4_MSG_TYPE_ENTRY(MOD_INIT_INSTANCE), 136 DBG_IPC4_MSG_TYPE_ENTRY(MOD_CONFIG_GET), 137 DBG_IPC4_MSG_TYPE_ENTRY(MOD_CONFIG_SET), 138 DBG_IPC4_MSG_TYPE_ENTRY(MOD_LARGE_CONFIG_GET), 139 DBG_IPC4_MSG_TYPE_ENTRY(MOD_LARGE_CONFIG_SET), 140 DBG_IPC4_MSG_TYPE_ENTRY(MOD_BIND), 141 DBG_IPC4_MSG_TYPE_ENTRY(MOD_UNBIND), 142 DBG_IPC4_MSG_TYPE_ENTRY(MOD_SET_DX), 143 DBG_IPC4_MSG_TYPE_ENTRY(MOD_SET_D0IX), 144 DBG_IPC4_MSG_TYPE_ENTRY(MOD_ENTER_MODULE_RESTORE), 145 DBG_IPC4_MSG_TYPE_ENTRY(MOD_EXIT_MODULE_RESTORE), 146 DBG_IPC4_MSG_TYPE_ENTRY(MOD_DELETE_INSTANCE), 147 }; 148 149 static const char * const ipc4_dbg_glb_msg_type[] = { 150 DBG_IPC4_MSG_TYPE_ENTRY(GLB_BOOT_CONFIG), 151 DBG_IPC4_MSG_TYPE_ENTRY(GLB_ROM_CONTROL), 152 DBG_IPC4_MSG_TYPE_ENTRY(GLB_IPCGATEWAY_CMD), 153 DBG_IPC4_MSG_TYPE_ENTRY(GLB_PERF_MEASUREMENTS_CMD), 154 DBG_IPC4_MSG_TYPE_ENTRY(GLB_CHAIN_DMA), 155 DBG_IPC4_MSG_TYPE_ENTRY(GLB_LOAD_MULTIPLE_MODULES), 156 DBG_IPC4_MSG_TYPE_ENTRY(GLB_UNLOAD_MULTIPLE_MODULES), 157 DBG_IPC4_MSG_TYPE_ENTRY(GLB_CREATE_PIPELINE), 158 DBG_IPC4_MSG_TYPE_ENTRY(GLB_DELETE_PIPELINE), 159 DBG_IPC4_MSG_TYPE_ENTRY(GLB_SET_PIPELINE_STATE), 160 DBG_IPC4_MSG_TYPE_ENTRY(GLB_GET_PIPELINE_STATE), 161 DBG_IPC4_MSG_TYPE_ENTRY(GLB_GET_PIPELINE_CONTEXT_SIZE), 162 DBG_IPC4_MSG_TYPE_ENTRY(GLB_SAVE_PIPELINE), 163 DBG_IPC4_MSG_TYPE_ENTRY(GLB_RESTORE_PIPELINE), 164 DBG_IPC4_MSG_TYPE_ENTRY(GLB_LOAD_LIBRARY), 165 DBG_IPC4_MSG_TYPE_ENTRY(GLB_INTERNAL_MESSAGE), 166 DBG_IPC4_MSG_TYPE_ENTRY(GLB_NOTIFICATION), 167 }; 168 169 #define DBG_IPC4_NOTIFICATION_TYPE_ENTRY(type) [SOF_IPC4_NOTIFY_##type] = #type 170 static const char * const ipc4_dbg_notification_type[] = { 171 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(PHRASE_DETECTED), 172 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(RESOURCE_EVENT), 173 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(LOG_BUFFER_STATUS), 174 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(TIMESTAMP_CAPTURED), 175 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(FW_READY), 176 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(FW_AUD_CLASS_RESULT), 177 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(EXCEPTION_CAUGHT), 178 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(MODULE_NOTIFICATION), 179 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(PROBE_DATA_AVAILABLE), 180 DBG_IPC4_NOTIFICATION_TYPE_ENTRY(ASYNC_MSG_SRVC_MESSAGE), 181 }; 182 183 static void sof_ipc4_log_header(struct device *dev, u8 *text, struct sof_ipc4_msg *msg, 184 bool data_size_valid) 185 { 186 u32 val, type; 187 const u8 *str2 = NULL; 188 const u8 *str = NULL; 189 190 val = msg->primary & SOF_IPC4_MSG_TARGET_MASK; 191 type = SOF_IPC4_MSG_TYPE_GET(msg->primary); 192 193 if (val == SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG)) { 194 /* Module message */ 195 if (type < SOF_IPC4_MOD_TYPE_LAST) 196 str = ipc4_dbg_mod_msg_type[type]; 197 if (!str) 198 str = "Unknown Module message type"; 199 } else { 200 /* Global FW message */ 201 if (type < SOF_IPC4_GLB_TYPE_LAST) 202 str = ipc4_dbg_glb_msg_type[type]; 203 if (!str) 204 str = "Unknown Global message type"; 205 206 if (type == SOF_IPC4_GLB_NOTIFICATION) { 207 /* Notification message */ 208 u32 notif = SOF_IPC4_NOTIFICATION_TYPE_GET(msg->primary); 209 210 /* Do not print log buffer notification if not desired */ 211 if (notif == SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS && 212 !sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS)) 213 return; 214 215 if (notif < SOF_IPC4_NOTIFY_TYPE_LAST) 216 str2 = ipc4_dbg_notification_type[notif]; 217 if (!str2) 218 str2 = "Unknown Global notification"; 219 } 220 } 221 222 if (str2) { 223 if (data_size_valid && msg->data_size) 224 dev_dbg(dev, "%s: %#x|%#x: %s|%s [data size: %zu]\n", 225 text, msg->primary, msg->extension, str, str2, 226 msg->data_size); 227 else 228 dev_dbg(dev, "%s: %#x|%#x: %s|%s\n", text, msg->primary, 229 msg->extension, str, str2); 230 } else { 231 if (data_size_valid && msg->data_size) 232 dev_dbg(dev, "%s: %#x|%#x: %s [data size: %zu]\n", 233 text, msg->primary, msg->extension, str, 234 msg->data_size); 235 else 236 dev_dbg(dev, "%s: %#x|%#x: %s\n", text, msg->primary, 237 msg->extension, str); 238 } 239 } 240 #else /* CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC */ 241 static void sof_ipc4_log_header(struct device *dev, u8 *text, struct sof_ipc4_msg *msg, 242 bool data_size_valid) 243 { 244 /* Do not print log buffer notification if not desired */ 245 if (!sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS) && 246 !SOF_IPC4_MSG_IS_MODULE_MSG(msg->primary) && 247 SOF_IPC4_MSG_TYPE_GET(msg->primary) == SOF_IPC4_GLB_NOTIFICATION && 248 SOF_IPC4_NOTIFICATION_TYPE_GET(msg->primary) == SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS) 249 return; 250 251 if (data_size_valid && msg->data_size) 252 dev_dbg(dev, "%s: %#x|%#x [data size: %zu]\n", text, 253 msg->primary, msg->extension, msg->data_size); 254 else 255 dev_dbg(dev, "%s: %#x|%#x\n", text, msg->primary, msg->extension); 256 } 257 #endif 258 259 static int sof_ipc4_get_reply(struct snd_sof_dev *sdev) 260 { 261 struct snd_sof_ipc_msg *msg = sdev->msg; 262 struct sof_ipc4_msg *ipc4_reply; 263 int ret; 264 265 /* get the generic reply */ 266 ipc4_reply = msg->reply_data; 267 268 sof_ipc4_log_header(sdev->dev, "ipc tx reply", ipc4_reply, false); 269 270 ret = sof_ipc4_check_reply_status(sdev, ipc4_reply->primary); 271 if (ret) 272 return ret; 273 274 /* No other information is expected for non large config get replies */ 275 if (!msg->reply_size || !SOF_IPC4_MSG_IS_MODULE_MSG(ipc4_reply->primary) || 276 (SOF_IPC4_MSG_TYPE_GET(ipc4_reply->primary) != SOF_IPC4_MOD_LARGE_CONFIG_GET)) 277 return 0; 278 279 /* Read the requested payload */ 280 snd_sof_dsp_mailbox_read(sdev, sdev->dsp_box.offset, ipc4_reply->data_ptr, 281 msg->reply_size); 282 283 return 0; 284 } 285 286 /* wait for IPC message reply */ 287 static int ipc4_wait_tx_done(struct snd_sof_ipc *ipc, void *reply_data) 288 { 289 struct snd_sof_ipc_msg *msg = &ipc->msg; 290 struct sof_ipc4_msg *ipc4_msg = msg->msg_data; 291 struct snd_sof_dev *sdev = ipc->sdev; 292 int ret; 293 294 /* wait for DSP IPC completion */ 295 ret = wait_event_timeout(msg->waitq, msg->ipc_complete, 296 msecs_to_jiffies(sdev->ipc_timeout)); 297 if (ret == 0) { 298 dev_err(sdev->dev, "ipc timed out for %#x|%#x\n", 299 ipc4_msg->primary, ipc4_msg->extension); 300 snd_sof_handle_fw_exception(ipc->sdev, "IPC timeout"); 301 return -ETIMEDOUT; 302 } 303 304 if (msg->reply_error) { 305 dev_err(sdev->dev, "ipc error for msg %#x|%#x\n", 306 ipc4_msg->primary, ipc4_msg->extension); 307 ret = msg->reply_error; 308 } else { 309 if (reply_data) { 310 struct sof_ipc4_msg *ipc4_reply = msg->reply_data; 311 struct sof_ipc4_msg *ipc4_reply_data = reply_data; 312 313 /* Copy the header */ 314 ipc4_reply_data->header_u64 = ipc4_reply->header_u64; 315 if (msg->reply_size && ipc4_reply_data->data_ptr) { 316 /* copy the payload returned from DSP */ 317 memcpy(ipc4_reply_data->data_ptr, ipc4_reply->data_ptr, 318 msg->reply_size); 319 ipc4_reply_data->data_size = msg->reply_size; 320 } 321 } 322 323 ret = 0; 324 sof_ipc4_log_header(sdev->dev, "ipc tx done ", ipc4_msg, true); 325 } 326 327 /* re-enable dumps after successful IPC tx */ 328 if (sdev->ipc_dump_printed) { 329 sdev->dbg_dump_printed = false; 330 sdev->ipc_dump_printed = false; 331 } 332 333 return ret; 334 } 335 336 static int ipc4_tx_msg_unlocked(struct snd_sof_ipc *ipc, 337 void *msg_data, size_t msg_bytes, 338 void *reply_data, size_t reply_bytes) 339 { 340 struct sof_ipc4_msg *ipc4_msg = msg_data; 341 struct snd_sof_dev *sdev = ipc->sdev; 342 int ret; 343 344 if (msg_bytes > ipc->max_payload_size || reply_bytes > ipc->max_payload_size) 345 return -EINVAL; 346 347 sof_ipc4_log_header(sdev->dev, "ipc tx ", msg_data, true); 348 349 ret = sof_ipc_send_msg(sdev, msg_data, msg_bytes, reply_bytes); 350 if (ret) { 351 dev_err_ratelimited(sdev->dev, 352 "%s: ipc message send for %#x|%#x failed: %d\n", 353 __func__, ipc4_msg->primary, ipc4_msg->extension, ret); 354 return ret; 355 } 356 357 /* now wait for completion */ 358 return ipc4_wait_tx_done(ipc, reply_data); 359 } 360 361 static int sof_ipc4_tx_msg(struct snd_sof_dev *sdev, void *msg_data, size_t msg_bytes, 362 void *reply_data, size_t reply_bytes, bool no_pm) 363 { 364 struct snd_sof_ipc *ipc = sdev->ipc; 365 #ifdef DEBUG_VERBOSE 366 struct sof_ipc4_msg *msg = NULL; 367 #endif 368 int ret; 369 370 if (!msg_data) 371 return -EINVAL; 372 373 if (!no_pm) { 374 const struct sof_dsp_power_state target_state = { 375 .state = SOF_DSP_PM_D0, 376 }; 377 378 /* ensure the DSP is in D0i0 before sending a new IPC */ 379 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 380 if (ret < 0) 381 return ret; 382 } 383 384 /* Serialise IPC TX */ 385 mutex_lock(&ipc->tx_mutex); 386 387 ret = ipc4_tx_msg_unlocked(ipc, msg_data, msg_bytes, reply_data, reply_bytes); 388 389 mutex_unlock(&ipc->tx_mutex); 390 391 #ifdef DEBUG_VERBOSE 392 /* payload is indicated by non zero msg/reply_bytes */ 393 if (msg_bytes) 394 msg = msg_data; 395 else if (reply_bytes) 396 msg = reply_data; 397 398 if (msg) 399 sof_ipc4_dump_payload(sdev, msg->data_ptr, msg->data_size); 400 #endif 401 402 return ret; 403 } 404 405 static int sof_ipc4_set_get_data(struct snd_sof_dev *sdev, void *data, 406 size_t payload_bytes, bool set) 407 { 408 size_t payload_limit = sdev->ipc->max_payload_size; 409 struct sof_ipc4_msg *ipc4_msg = data; 410 struct sof_ipc4_msg tx = {{ 0 }}; 411 struct sof_ipc4_msg rx = {{ 0 }}; 412 size_t remaining = payload_bytes; 413 size_t offset = 0; 414 size_t chunk_size; 415 int ret; 416 417 if (!data) 418 return -EINVAL; 419 420 if ((ipc4_msg->primary & SOF_IPC4_MSG_TARGET_MASK) != 421 SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG)) 422 return -EINVAL; 423 424 ipc4_msg->primary &= ~SOF_IPC4_MSG_TYPE_MASK; 425 tx.primary = ipc4_msg->primary; 426 tx.extension = ipc4_msg->extension; 427 428 if (set) 429 tx.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_LARGE_CONFIG_SET); 430 else 431 tx.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_LARGE_CONFIG_GET); 432 433 tx.extension &= ~SOF_IPC4_MOD_EXT_MSG_SIZE_MASK; 434 tx.extension |= SOF_IPC4_MOD_EXT_MSG_SIZE(payload_bytes); 435 436 tx.extension |= SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(1); 437 438 /* Serialise IPC TX */ 439 mutex_lock(&sdev->ipc->tx_mutex); 440 441 do { 442 size_t tx_size, rx_size; 443 444 if (remaining > payload_limit) { 445 chunk_size = payload_limit; 446 } else { 447 chunk_size = remaining; 448 if (set) 449 tx.extension |= SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(1); 450 } 451 452 if (offset) { 453 tx.extension &= ~SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK; 454 tx.extension &= ~SOF_IPC4_MOD_EXT_MSG_SIZE_MASK; 455 tx.extension |= SOF_IPC4_MOD_EXT_MSG_SIZE(offset); 456 } 457 458 if (set) { 459 tx.data_size = chunk_size; 460 tx.data_ptr = ipc4_msg->data_ptr + offset; 461 462 tx_size = chunk_size; 463 rx_size = 0; 464 } else { 465 rx.primary = 0; 466 rx.extension = 0; 467 rx.data_size = chunk_size; 468 rx.data_ptr = ipc4_msg->data_ptr + offset; 469 470 tx_size = 0; 471 rx_size = chunk_size; 472 } 473 474 /* Send the message for the current chunk */ 475 ret = ipc4_tx_msg_unlocked(sdev->ipc, &tx, tx_size, &rx, rx_size); 476 if (ret < 0) { 477 dev_err(sdev->dev, 478 "%s: large config %s failed at offset %zu: %d\n", 479 __func__, set ? "set" : "get", offset, ret); 480 goto out; 481 } 482 483 if (!set && rx.extension & SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK) { 484 /* Verify the firmware reported total payload size */ 485 rx_size = rx.extension & SOF_IPC4_MOD_EXT_MSG_SIZE_MASK; 486 487 if (rx_size > payload_bytes) { 488 dev_err(sdev->dev, 489 "%s: Receive buffer (%zu) is too small for %zu\n", 490 __func__, payload_bytes, rx_size); 491 ret = -ENOMEM; 492 goto out; 493 } 494 495 if (rx_size < chunk_size) { 496 chunk_size = rx_size; 497 remaining = rx_size; 498 } else if (rx_size < payload_bytes) { 499 remaining = rx_size; 500 } 501 } 502 503 offset += chunk_size; 504 remaining -= chunk_size; 505 } while (remaining); 506 507 /* Adjust the received data size if needed */ 508 if (!set && payload_bytes != offset) 509 ipc4_msg->data_size = offset; 510 511 sof_ipc4_dump_payload(sdev, ipc4_msg->data_ptr, ipc4_msg->data_size); 512 513 out: 514 mutex_unlock(&sdev->ipc->tx_mutex); 515 516 return ret; 517 } 518 519 static int sof_ipc4_init_msg_memory(struct snd_sof_dev *sdev) 520 { 521 struct sof_ipc4_msg *ipc4_msg; 522 struct snd_sof_ipc_msg *msg = &sdev->ipc->msg; 523 524 /* TODO: get max_payload_size from firmware */ 525 sdev->ipc->max_payload_size = SOF_IPC4_MSG_MAX_SIZE; 526 527 /* Allocate memory for the ipc4 container and the maximum payload */ 528 msg->reply_data = devm_kzalloc(sdev->dev, sdev->ipc->max_payload_size + 529 sizeof(struct sof_ipc4_msg), GFP_KERNEL); 530 if (!msg->reply_data) 531 return -ENOMEM; 532 533 ipc4_msg = msg->reply_data; 534 ipc4_msg->data_ptr = msg->reply_data + sizeof(struct sof_ipc4_msg); 535 536 return 0; 537 } 538 539 static int ipc4_fw_ready(struct snd_sof_dev *sdev, struct sof_ipc4_msg *ipc4_msg) 540 { 541 int inbox_offset, inbox_size, outbox_offset, outbox_size; 542 543 /* no need to re-check version/ABI for subsequent boots */ 544 if (!sdev->first_boot) 545 return 0; 546 547 /* Set up the windows for IPC communication */ 548 inbox_offset = snd_sof_dsp_get_mailbox_offset(sdev); 549 if (inbox_offset < 0) { 550 dev_err(sdev->dev, "%s: No mailbox offset\n", __func__); 551 return inbox_offset; 552 } 553 inbox_size = SOF_IPC4_MSG_MAX_SIZE; 554 outbox_offset = snd_sof_dsp_get_window_offset(sdev, SOF_IPC4_OUTBOX_WINDOW_IDX); 555 outbox_size = SOF_IPC4_MSG_MAX_SIZE; 556 557 sdev->fw_info_box.offset = snd_sof_dsp_get_window_offset(sdev, SOF_IPC4_INBOX_WINDOW_IDX); 558 sdev->fw_info_box.size = sizeof(struct sof_ipc4_fw_registers); 559 sdev->dsp_box.offset = inbox_offset; 560 sdev->dsp_box.size = inbox_size; 561 sdev->host_box.offset = outbox_offset; 562 sdev->host_box.size = outbox_size; 563 564 sdev->debug_box.offset = snd_sof_dsp_get_window_offset(sdev, 565 SOF_IPC4_DEBUG_WINDOW_IDX); 566 567 dev_dbg(sdev->dev, "mailbox upstream 0x%x - size 0x%x\n", 568 inbox_offset, inbox_size); 569 dev_dbg(sdev->dev, "mailbox downstream 0x%x - size 0x%x\n", 570 outbox_offset, outbox_size); 571 dev_dbg(sdev->dev, "debug box 0x%x\n", sdev->debug_box.offset); 572 573 return sof_ipc4_init_msg_memory(sdev); 574 } 575 576 static void sof_ipc4_rx_msg(struct snd_sof_dev *sdev) 577 { 578 struct sof_ipc4_msg *ipc4_msg = sdev->ipc->msg.rx_data; 579 size_t data_size = 0; 580 int err; 581 582 if (!ipc4_msg || !SOF_IPC4_MSG_IS_NOTIFICATION(ipc4_msg->primary)) 583 return; 584 585 ipc4_msg->data_ptr = NULL; 586 ipc4_msg->data_size = 0; 587 588 sof_ipc4_log_header(sdev->dev, "ipc rx ", ipc4_msg, false); 589 590 switch (SOF_IPC4_NOTIFICATION_TYPE_GET(ipc4_msg->primary)) { 591 case SOF_IPC4_NOTIFY_FW_READY: 592 /* check for FW boot completion */ 593 if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) { 594 err = ipc4_fw_ready(sdev, ipc4_msg); 595 if (err < 0) 596 sof_set_fw_state(sdev, SOF_FW_BOOT_READY_FAILED); 597 else 598 sof_set_fw_state(sdev, SOF_FW_BOOT_READY_OK); 599 600 /* wake up firmware loader */ 601 wake_up(&sdev->boot_wait); 602 } 603 604 break; 605 case SOF_IPC4_NOTIFY_RESOURCE_EVENT: 606 data_size = sizeof(struct sof_ipc4_notify_resource_data); 607 break; 608 case SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS: 609 sof_ipc4_mtrace_update_pos(sdev, SOF_IPC4_LOG_CORE_GET(ipc4_msg->primary)); 610 break; 611 default: 612 dev_dbg(sdev->dev, "Unhandled DSP message: %#x|%#x\n", 613 ipc4_msg->primary, ipc4_msg->extension); 614 break; 615 } 616 617 if (data_size) { 618 ipc4_msg->data_ptr = kmalloc(data_size, GFP_KERNEL); 619 if (!ipc4_msg->data_ptr) 620 return; 621 622 ipc4_msg->data_size = data_size; 623 snd_sof_ipc_msg_data(sdev, NULL, ipc4_msg->data_ptr, ipc4_msg->data_size); 624 } 625 626 sof_ipc4_log_header(sdev->dev, "ipc rx done ", ipc4_msg, true); 627 628 if (data_size) { 629 kfree(ipc4_msg->data_ptr); 630 ipc4_msg->data_ptr = NULL; 631 ipc4_msg->data_size = 0; 632 } 633 } 634 635 static int sof_ipc4_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on) 636 { 637 struct sof_ipc4_dx_state_info dx_state; 638 struct sof_ipc4_msg msg; 639 640 dx_state.core_mask = BIT(core_idx); 641 if (on) 642 dx_state.dx_mask = BIT(core_idx); 643 else 644 dx_state.dx_mask = 0; 645 646 msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_DX); 647 msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST); 648 msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG); 649 msg.extension = 0; 650 msg.data_ptr = &dx_state; 651 msg.data_size = sizeof(dx_state); 652 653 return sof_ipc4_tx_msg(sdev, &msg, msg.data_size, NULL, 0, false); 654 } 655 656 /* 657 * The context save callback is used to send a message to the firmware notifying 658 * it that the primary core is going to be turned off, which is used as an 659 * indication to prepare for a full power down, thus preparing for IMR boot 660 * (when supported) 661 * 662 * Note: in IPC4 there is no message used to restore context, thus no context 663 * restore callback is implemented 664 */ 665 static int sof_ipc4_ctx_save(struct snd_sof_dev *sdev) 666 { 667 return sof_ipc4_set_core_state(sdev, SOF_DSP_PRIMARY_CORE, false); 668 } 669 670 static int sof_ipc4_set_pm_gate(struct snd_sof_dev *sdev, u32 flags) 671 { 672 struct sof_ipc4_msg msg = {{0}}; 673 674 msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_D0IX); 675 msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST); 676 msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG); 677 msg.extension = flags; 678 679 return sof_ipc4_tx_msg(sdev, &msg, 0, NULL, 0, true); 680 } 681 682 static const struct sof_ipc_pm_ops ipc4_pm_ops = { 683 .ctx_save = sof_ipc4_ctx_save, 684 .set_core_state = sof_ipc4_set_core_state, 685 .set_pm_gate = sof_ipc4_set_pm_gate, 686 }; 687 688 static int sof_ipc4_init(struct snd_sof_dev *sdev) 689 { 690 struct sof_ipc4_fw_data *ipc4_data = sdev->private; 691 692 mutex_init(&ipc4_data->pipeline_state_mutex); 693 694 xa_init_flags(&ipc4_data->fw_lib_xa, XA_FLAGS_ALLOC); 695 696 return 0; 697 } 698 699 static void sof_ipc4_exit(struct snd_sof_dev *sdev) 700 { 701 struct sof_ipc4_fw_data *ipc4_data = sdev->private; 702 struct sof_ipc4_fw_library *fw_lib; 703 unsigned long lib_id; 704 705 xa_for_each(&ipc4_data->fw_lib_xa, lib_id, fw_lib) { 706 /* 707 * The basefw (ID == 0) is handled by generic code, it is not 708 * loaded by IPC4 code. 709 */ 710 if (lib_id != 0) 711 release_firmware(fw_lib->sof_fw.fw); 712 713 fw_lib->sof_fw.fw = NULL; 714 } 715 716 xa_destroy(&ipc4_data->fw_lib_xa); 717 } 718 719 static int sof_ipc4_post_boot(struct snd_sof_dev *sdev) 720 { 721 if (sdev->first_boot) 722 return sof_ipc4_query_fw_configuration(sdev); 723 724 return sof_ipc4_reload_fw_libraries(sdev); 725 } 726 727 const struct sof_ipc_ops ipc4_ops = { 728 .init = sof_ipc4_init, 729 .exit = sof_ipc4_exit, 730 .post_fw_boot = sof_ipc4_post_boot, 731 .tx_msg = sof_ipc4_tx_msg, 732 .rx_msg = sof_ipc4_rx_msg, 733 .set_get_data = sof_ipc4_set_get_data, 734 .get_reply = sof_ipc4_get_reply, 735 .pm = &ipc4_pm_ops, 736 .fw_loader = &ipc4_loader_ops, 737 .tplg = &ipc4_tplg_ops, 738 .pcm = &ipc4_pcm_ops, 739 .fw_tracing = &ipc4_mtrace_ops, 740 }; 741