1ab05061dSRander Wang /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2ab05061dSRander Wang /* 3ab05061dSRander Wang * This file is provided under a dual BSD/GPLv2 license. When using or 4ab05061dSRander Wang * redistributing this file, you may do so under either license. 5ab05061dSRander Wang * 6*293ad281SPierre-Louis Bossart * Copyright(c) 2023 Intel Corporation 7ab05061dSRander Wang */ 8ab05061dSRander Wang 9ab05061dSRander Wang #ifndef __SOUND_SOC_SOF_IPC4_TELEMETRY_H 10ab05061dSRander Wang #define __SOUND_SOC_SOF_IPC4_TELEMETRY_H 11ab05061dSRander Wang 12ab05061dSRander Wang /* Target code */ 13ab05061dSRander Wang enum sof_ipc4_coredump_tgt_code { 14ab05061dSRander Wang COREDUMP_TGT_UNKNOWN = 0, 15ab05061dSRander Wang COREDUMP_TGT_X86, 16ab05061dSRander Wang COREDUMP_TGT_X86_64, 17ab05061dSRander Wang COREDUMP_TGT_ARM_CORTEX_M, 18ab05061dSRander Wang COREDUMP_TGT_RISC_V, 19ab05061dSRander Wang COREDUMP_TGT_XTENSA, 20ab05061dSRander Wang }; 21ab05061dSRander Wang 22ab05061dSRander Wang #define COREDUMP_ARCH_HDR_ID 'A' 23ab05061dSRander Wang #define COREDUMP_HDR_ID0 'Z' 24ab05061dSRander Wang #define COREDUMP_HDR_ID1 'E' 25ab05061dSRander Wang 26ab05061dSRander Wang #define XTENSA_BLOCK_HDR_VER 2 27ab05061dSRander Wang #define XTENSA_CORE_DUMP_SEPARATOR 0x0DEC0DEB 28ab05061dSRander Wang #define XTENSA_CORE_AR_REGS_COUNT 16 29ab05061dSRander Wang #define XTENSA_SOC_INTEL_ADSP 3 30ab05061dSRander Wang #define XTENSA_TOOL_CHAIN_ZEPHYR 1 31ab05061dSRander Wang #define XTENSA_TOOL_CHAIN_XCC 2 32ab05061dSRander Wang 33ab05061dSRander Wang /* Coredump header */ 34ab05061dSRander Wang struct sof_ipc4_coredump_hdr { 35ab05061dSRander Wang /* 'Z', 'E' as identifier of file */ 36ab05061dSRander Wang char id[2]; 37ab05061dSRander Wang 38ab05061dSRander Wang /* Identify the version of the header */ 39ab05061dSRander Wang u16 hdr_version; 40ab05061dSRander Wang 41ab05061dSRander Wang /* Indicate which target (e.g. architecture or SoC) */ 42ab05061dSRander Wang u16 tgt_code; 43ab05061dSRander Wang 44ab05061dSRander Wang /* Size of uintptr_t in power of 2. (e.g. 5 for 32-bit, 6 for 64-bit) */ 45ab05061dSRander Wang u8 ptr_size_bits; 46ab05061dSRander Wang 47ab05061dSRander Wang u8 flag; 48ab05061dSRander Wang 49ab05061dSRander Wang /* Reason for the fatal error */ 50ab05061dSRander Wang u32 reason; 51ab05061dSRander Wang } __packed; 52ab05061dSRander Wang 53ab05061dSRander Wang /* Architecture-specific block header */ 54ab05061dSRander Wang struct sof_ipc4_coredump_arch_hdr { 55ab05061dSRander Wang /* COREDUMP_ARCH_HDR_ID to indicate this is a architecture-specific block */ 56ab05061dSRander Wang char id; 57ab05061dSRander Wang 58ab05061dSRander Wang /* Identify the version of this block */ 59ab05061dSRander Wang u16 hdr_version; 60ab05061dSRander Wang 61ab05061dSRander Wang /* Number of bytes following the header */ 62ab05061dSRander Wang u16 num_bytes; 63ab05061dSRander Wang } __packed; 64ab05061dSRander Wang 65ab05061dSRander Wang struct sof_ipc4_telemetry_slot_data { 66ab05061dSRander Wang u32 separator; 67ab05061dSRander Wang struct sof_ipc4_coredump_hdr hdr; 68ab05061dSRander Wang struct sof_ipc4_coredump_arch_hdr arch_hdr; 69ab05061dSRander Wang u32 arch_data[]; 70ab05061dSRander Wang } __packed; 71ab05061dSRander Wang 72ab05061dSRander Wang void sof_ipc4_create_exception_debugfs_node(struct snd_sof_dev *sdev); 73ab05061dSRander Wang #endif 74