1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2022 Intel Corporation 7 // 8 9 #include <sound/pcm_params.h> 10 #include <sound/sof/ipc4/header.h> 11 #include "sof-audio.h" 12 #include "sof-priv.h" 13 #include "ops.h" 14 #include "ipc4-priv.h" 15 #include "ipc4-topology.h" 16 #include "ipc4-fw-reg.h" 17 18 /** 19 * struct sof_ipc4_timestamp_info - IPC4 timestamp info 20 * @host_copier: the host copier of the pcm stream 21 * @dai_copier: the dai copier of the pcm stream 22 * @stream_start_offset: reported by fw in memory window (converted to 23 * frames at host_copier sampling rate) 24 * @stream_end_offset: reported by fw in memory window (converted to 25 * frames at host_copier sampling rate) 26 * @llp_offset: llp offset in memory window 27 * @delay: Calculated and stored in pointer callback. The stored value is 28 * returned in the delay callback. Expressed in frames at host copier 29 * sampling rate. 30 */ 31 struct sof_ipc4_timestamp_info { 32 struct sof_ipc4_copier *host_copier; 33 struct sof_ipc4_copier *dai_copier; 34 u64 stream_start_offset; 35 u64 stream_end_offset; 36 u32 llp_offset; 37 38 snd_pcm_sframes_t delay; 39 }; 40 41 /** 42 * struct sof_ipc4_pcm_stream_priv - IPC4 specific private data 43 * @time_info: pointer to time info struct if it is supported, otherwise NULL 44 * @chain_dma_allocated: indicates the ChainDMA allocation state 45 */ 46 struct sof_ipc4_pcm_stream_priv { 47 struct sof_ipc4_timestamp_info *time_info; 48 49 bool chain_dma_allocated; 50 }; 51 52 /* 53 * Modulus to use to compare host and link position counters. The sampling 54 * rates may be different, so the raw hardware counters will wrap 55 * around at different times. To calculate differences, use 56 * DELAY_BOUNDARY as a common modulus. This value must be smaller than 57 * the wrap-around point of any hardware counter, and larger than any 58 * valid delay measurement. 59 */ 60 #define DELAY_BOUNDARY U32_MAX 61 62 #define DELAY_MAX (DELAY_BOUNDARY >> 1) 63 64 static inline struct sof_ipc4_timestamp_info * 65 sof_ipc4_sps_to_time_info(struct snd_sof_pcm_stream *sps) 66 { 67 struct sof_ipc4_pcm_stream_priv *stream_priv = sps->private; 68 69 return stream_priv->time_info; 70 } 71 72 static 73 char *sof_ipc4_set_multi_pipeline_state_debug(struct snd_sof_dev *sdev, char *buf, size_t size, 74 struct ipc4_pipeline_set_state_data *trigger_list) 75 { 76 int i, offset = 0; 77 78 for (i = 0; i < trigger_list->count; i++) { 79 offset += snprintf(buf + offset, size - offset, " %d", 80 trigger_list->pipeline_instance_ids[i]); 81 82 if (offset >= size - 1) { 83 buf[size - 1] = '\0'; 84 break; 85 } 86 } 87 return buf; 88 } 89 90 static int sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev *sdev, u32 state, 91 struct ipc4_pipeline_set_state_data *trigger_list) 92 { 93 struct sof_ipc4_msg msg = {{ 0 }}; 94 u32 primary, ipc_size; 95 char debug_buf[32]; 96 97 /* trigger a single pipeline */ 98 if (trigger_list->count == 1) 99 return sof_ipc4_set_pipeline_state(sdev, trigger_list->pipeline_instance_ids[0], 100 state); 101 102 dev_dbg(sdev->dev, "Set pipelines %s to state %d%s", 103 sof_ipc4_set_multi_pipeline_state_debug(sdev, debug_buf, sizeof(debug_buf), 104 trigger_list), 105 state, sof_ipc4_pipeline_state_str(state)); 106 107 primary = state; 108 primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE); 109 primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST); 110 primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG); 111 msg.primary = primary; 112 113 /* trigger multiple pipelines with a single IPC */ 114 msg.extension = SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI; 115 116 /* ipc_size includes the count and the pipeline IDs for the number of pipelines */ 117 ipc_size = sizeof(u32) * (trigger_list->count + 1); 118 msg.data_size = ipc_size; 119 msg.data_ptr = trigger_list; 120 121 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, ipc_size); 122 } 123 124 int sof_ipc4_set_pipeline_state(struct snd_sof_dev *sdev, u32 instance_id, u32 state) 125 { 126 struct sof_ipc4_msg msg = {{ 0 }}; 127 u32 primary; 128 129 dev_dbg(sdev->dev, "Set pipeline %d to state %d%s", instance_id, state, 130 sof_ipc4_pipeline_state_str(state)); 131 132 primary = state; 133 primary |= SOF_IPC4_GLB_PIPE_STATE_ID(instance_id); 134 primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE); 135 primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST); 136 primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG); 137 138 msg.primary = primary; 139 140 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0); 141 } 142 EXPORT_SYMBOL(sof_ipc4_set_pipeline_state); 143 144 static void sof_ipc4_add_pipeline_by_priority(struct ipc4_pipeline_set_state_data *trigger_list, 145 struct snd_sof_widget *pipe_widget, 146 s8 *pipe_priority, bool ascend) 147 { 148 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; 149 int i, j; 150 151 for (i = 0; i < trigger_list->count; i++) { 152 /* add pipeline from low priority to high */ 153 if (ascend && pipeline->priority < pipe_priority[i]) 154 break; 155 /* add pipeline from high priority to low */ 156 else if (!ascend && pipeline->priority > pipe_priority[i]) 157 break; 158 } 159 160 for (j = trigger_list->count - 1; j >= i; j--) { 161 trigger_list->pipeline_instance_ids[j + 1] = trigger_list->pipeline_instance_ids[j]; 162 pipe_priority[j + 1] = pipe_priority[j]; 163 } 164 165 trigger_list->pipeline_instance_ids[i] = pipe_widget->instance_id; 166 trigger_list->count++; 167 pipe_priority[i] = pipeline->priority; 168 } 169 170 static void 171 sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev *sdev, int state, 172 struct snd_sof_pipeline *spipe, 173 struct ipc4_pipeline_set_state_data *trigger_list, 174 s8 *pipe_priority) 175 { 176 struct snd_sof_widget *pipe_widget = spipe->pipe_widget; 177 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; 178 179 if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET) 180 return; 181 182 switch (state) { 183 case SOF_IPC4_PIPE_RUNNING: 184 /* 185 * Trigger pipeline if all PCMs containing it are paused or if it is RUNNING 186 * for the first time 187 */ 188 if (spipe->started_count == spipe->paused_count) 189 sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority, 190 false); 191 break; 192 case SOF_IPC4_PIPE_RESET: 193 /* RESET if the pipeline is neither running nor paused */ 194 if (!spipe->started_count && !spipe->paused_count) 195 sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority, 196 true); 197 break; 198 case SOF_IPC4_PIPE_PAUSED: 199 /* Pause the pipeline only when its started_count is 1 more than paused_count */ 200 if (spipe->paused_count == (spipe->started_count - 1)) 201 sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority, 202 true); 203 break; 204 default: 205 break; 206 } 207 } 208 209 static void 210 sof_ipc4_update_pipeline_state(struct snd_sof_dev *sdev, int state, int cmd, 211 struct snd_sof_pipeline *spipe, 212 struct ipc4_pipeline_set_state_data *trigger_list) 213 { 214 struct snd_sof_widget *pipe_widget = spipe->pipe_widget; 215 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; 216 int i; 217 218 if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET) 219 return; 220 221 /* set state for pipeline if it was just triggered */ 222 for (i = 0; i < trigger_list->count; i++) { 223 if (trigger_list->pipeline_instance_ids[i] == pipe_widget->instance_id) { 224 pipeline->state = state; 225 break; 226 } 227 } 228 229 switch (state) { 230 case SOF_IPC4_PIPE_PAUSED: 231 switch (cmd) { 232 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 233 /* 234 * increment paused_count if the PAUSED is the final state during 235 * the PAUSE trigger 236 */ 237 spipe->paused_count++; 238 break; 239 case SNDRV_PCM_TRIGGER_STOP: 240 case SNDRV_PCM_TRIGGER_SUSPEND: 241 /* 242 * decrement started_count if PAUSED is the final state during the 243 * STOP trigger 244 */ 245 spipe->started_count--; 246 break; 247 default: 248 break; 249 } 250 break; 251 case SOF_IPC4_PIPE_RUNNING: 252 switch (cmd) { 253 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 254 /* decrement paused_count for RELEASE */ 255 spipe->paused_count--; 256 break; 257 case SNDRV_PCM_TRIGGER_START: 258 case SNDRV_PCM_TRIGGER_RESUME: 259 /* increment started_count for START/RESUME */ 260 spipe->started_count++; 261 break; 262 default: 263 break; 264 } 265 break; 266 default: 267 break; 268 } 269 } 270 271 /* 272 * The picture below represents the pipeline state machine wrt PCM actions corresponding to the 273 * triggers and ioctls 274 * +---------------+ 275 * | | 276 * | INIT | 277 * | | 278 * +-------+-------+ 279 * | 280 * | 281 * | START 282 * | 283 * | 284 * +----------------+ +------v-------+ +-------------+ 285 * | | START | | HW_FREE | | 286 * | RUNNING <-------------+ PAUSED +--------------> + RESET | 287 * | | PAUSE | | | | 288 * +------+---------+ RELEASE +---------+----+ +-------------+ 289 * | ^ 290 * | | 291 * | | 292 * | | 293 * | PAUSE | 294 * +---------------------------------+ 295 * STOP/SUSPEND 296 * 297 * Note that during system suspend, the suspend trigger is followed by a hw_free in 298 * sof_pcm_trigger(). So, the final state during suspend would be RESET. 299 * Also, since the SOF driver doesn't support full resume, streams would be restarted with the 300 * prepare ioctl before the START trigger. 301 */ 302 303 /* 304 * Chained DMA is a special case where there is no processing on 305 * DSP. The samples are just moved over by host side DMA to a single 306 * buffer on DSP and directly from there to link DMA. However, the 307 * model on SOF driver has two notional pipelines, one at host DAI, 308 * and another at link DAI. They both shall have the use_chain_dma 309 * attribute. 310 */ 311 312 static int sof_ipc4_chain_dma_trigger(struct snd_sof_dev *sdev, 313 struct snd_sof_pcm *spcm, int direction, 314 struct snd_sof_pcm_stream_pipeline_list *pipeline_list, 315 int state, int cmd) 316 { 317 struct sof_ipc4_fw_data *ipc4_data = sdev->private; 318 struct sof_ipc4_pcm_stream_priv *stream_priv; 319 bool allocate, enable, set_fifo_size; 320 struct sof_ipc4_msg msg = {{ 0 }}; 321 int ret, i; 322 323 stream_priv = spcm->stream[direction].private; 324 325 switch (state) { 326 case SOF_IPC4_PIPE_RUNNING: /* Allocate and start chained dma */ 327 allocate = true; 328 enable = true; 329 /* 330 * SOF assumes creation of a new stream from the presence of fifo_size 331 * in the message, so we must leave it out in pause release case. 332 */ 333 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) 334 set_fifo_size = false; 335 else 336 set_fifo_size = true; 337 break; 338 case SOF_IPC4_PIPE_PAUSED: /* Disable chained DMA. */ 339 allocate = true; 340 enable = false; 341 set_fifo_size = false; 342 break; 343 case SOF_IPC4_PIPE_RESET: /* Disable and free chained DMA. */ 344 345 /* ChainDMA can only be reset if it has been allocated */ 346 if (!stream_priv->chain_dma_allocated) 347 return 0; 348 349 allocate = false; 350 enable = false; 351 set_fifo_size = false; 352 break; 353 default: 354 spcm_err(spcm, direction, "Unexpected pipeline state %d\n", state); 355 return -EINVAL; 356 } 357 358 msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_CHAIN_DMA); 359 msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST); 360 msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG); 361 362 /* 363 * To set-up the DMA chain, the host DMA ID and SCS setting 364 * are retrieved from the host pipeline configuration. Likewise 365 * the link DMA ID and fifo_size are retrieved from the link 366 * pipeline configuration. 367 */ 368 for (i = 0; i < pipeline_list->count; i++) { 369 struct snd_sof_pipeline *spipe = pipeline_list->pipelines[i]; 370 struct snd_sof_widget *pipe_widget = spipe->pipe_widget; 371 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; 372 373 if (!pipeline->use_chain_dma) { 374 spcm_err(spcm, direction, 375 "All pipelines in chained DMA path should have use_chain_dma attribute set."); 376 return -EINVAL; 377 } 378 379 msg.primary |= pipeline->msg.primary; 380 381 /* Add fifo_size (actually DMA buffer size) field to the message */ 382 if (set_fifo_size) 383 msg.extension |= pipeline->msg.extension; 384 } 385 386 if (direction == SNDRV_PCM_STREAM_CAPTURE) { 387 /* 388 * For ChainDMA the DMA ids are unique with the following mapping: 389 * playback: 0 - (num_playback_streams - 1) 390 * capture: num_playback_streams - (num_playback_streams + 391 * num_capture_streams - 1) 392 * 393 * Add the num_playback_streams offset to the DMA ids stored in 394 * msg.primary in case capture 395 */ 396 msg.primary += SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(ipc4_data->num_playback_streams); 397 msg.primary += SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(ipc4_data->num_playback_streams); 398 } 399 400 if (allocate) 401 msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK; 402 403 if (enable) 404 msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK; 405 406 ret = sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0); 407 /* Update the ChainDMA allocation state */ 408 if (!ret) 409 stream_priv->chain_dma_allocated = allocate; 410 411 return ret; 412 } 413 414 static int sof_ipc4_trigger_pipelines(struct snd_soc_component *component, 415 struct snd_pcm_substream *substream, int state, int cmd) 416 { 417 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component); 418 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 419 struct snd_sof_pcm_stream_pipeline_list *pipeline_list; 420 struct sof_ipc4_fw_data *ipc4_data = sdev->private; 421 struct ipc4_pipeline_set_state_data *trigger_list; 422 struct snd_sof_widget *pipe_widget; 423 struct sof_ipc4_pipeline *pipeline; 424 struct snd_sof_pipeline *spipe; 425 struct snd_sof_pcm *spcm; 426 u8 *pipe_priority; 427 int ret; 428 int i; 429 430 spcm = snd_sof_find_spcm_dai(component, rtd); 431 if (!spcm) 432 return -EINVAL; 433 434 spcm_dbg(spcm, substream->stream, "cmd: %d, state: %d\n", cmd, state); 435 436 pipeline_list = &spcm->stream[substream->stream].pipeline_list; 437 438 /* nothing to trigger if the list is empty */ 439 if (!pipeline_list->pipelines || !pipeline_list->count) 440 return 0; 441 442 spipe = pipeline_list->pipelines[0]; 443 pipe_widget = spipe->pipe_widget; 444 pipeline = pipe_widget->private; 445 446 /* 447 * If use_chain_dma attribute is set we proceed to chained DMA 448 * trigger function that handles the rest for the substream. 449 */ 450 if (pipeline->use_chain_dma) { 451 struct sof_ipc4_timestamp_info *time_info; 452 453 time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]); 454 455 ret = sof_ipc4_chain_dma_trigger(sdev, spcm, substream->stream, 456 pipeline_list, state, cmd); 457 if (ret || !time_info) 458 return ret; 459 460 if (state == SOF_IPC4_PIPE_PAUSED) { 461 /* 462 * Record the DAI position for delay reporting 463 * To handle multiple pause/resume/xrun we need to add 464 * the positions to simulate how the firmware behaves 465 */ 466 u64 pos = snd_sof_pcm_get_dai_frame_counter(sdev, component, 467 substream); 468 469 time_info->stream_end_offset += pos; 470 } else if (state == SOF_IPC4_PIPE_RESET) { 471 /* Reset the end offset as the stream is stopped */ 472 time_info->stream_end_offset = 0; 473 } 474 475 return 0; 476 } 477 478 /* allocate memory for the pipeline data */ 479 trigger_list = kzalloc(struct_size(trigger_list, pipeline_instance_ids, 480 pipeline_list->count), GFP_KERNEL); 481 if (!trigger_list) 482 return -ENOMEM; 483 484 pipe_priority = kzalloc(pipeline_list->count, GFP_KERNEL); 485 if (!pipe_priority) { 486 kfree(trigger_list); 487 return -ENOMEM; 488 } 489 490 guard(mutex)(&ipc4_data->pipeline_state_mutex); 491 492 /* 493 * IPC4 requires pipelines to be triggered in order starting at the sink and 494 * walking all the way to the source. So traverse the pipeline_list in the order 495 * sink->source when starting PCM's and in the reverse order to pause/stop PCM's. 496 * Skip the pipelines that have their skip_during_fe_trigger flag set. If there is a fork 497 * in the pipeline, the order of triggering between the left/right paths will be 498 * indeterministic. But the sink->source trigger order sink->source would still be 499 * guaranteed for each fork independently. 500 */ 501 if (state == SOF_IPC4_PIPE_RUNNING || state == SOF_IPC4_PIPE_RESET) 502 for (i = pipeline_list->count - 1; i >= 0; i--) { 503 spipe = pipeline_list->pipelines[i]; 504 sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list, 505 pipe_priority); 506 } 507 else 508 for (i = 0; i < pipeline_list->count; i++) { 509 spipe = pipeline_list->pipelines[i]; 510 sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list, 511 pipe_priority); 512 } 513 514 /* return if all pipelines are in the requested state already */ 515 if (!trigger_list->count) { 516 ret = 0; 517 goto free; 518 } 519 520 /* no need to pause before reset or before pause release */ 521 if (state == SOF_IPC4_PIPE_RESET || cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) 522 goto skip_pause_transition; 523 524 /* 525 * set paused state for pipelines if the final state is PAUSED or when the pipeline 526 * is set to RUNNING for the first time after the PCM is started. 527 */ 528 ret = sof_ipc4_set_multi_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, trigger_list); 529 if (ret < 0) { 530 spcm_err(spcm, substream->stream, "failed to pause all pipelines\n"); 531 goto free; 532 } 533 534 /* update PAUSED state for all pipelines just triggered */ 535 for (i = 0; i < pipeline_list->count ; i++) { 536 spipe = pipeline_list->pipelines[i]; 537 sof_ipc4_update_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, cmd, spipe, 538 trigger_list); 539 } 540 541 /* return if this is the final state */ 542 if (state == SOF_IPC4_PIPE_PAUSED) { 543 struct sof_ipc4_timestamp_info *time_info; 544 545 /* 546 * Invalidate the stream_start_offset to make sure that it is 547 * going to be updated if the stream resumes 548 */ 549 time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]); 550 if (time_info) 551 time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION; 552 553 goto free; 554 } 555 skip_pause_transition: 556 /* else set the RUNNING/RESET state in the DSP */ 557 ret = sof_ipc4_set_multi_pipeline_state(sdev, state, trigger_list); 558 if (ret < 0) { 559 spcm_err(spcm, substream->stream, 560 "failed to set final state %d for all pipelines\n", 561 state); 562 /* 563 * workaround: if the firmware is crashed while setting the 564 * pipelines to reset state we must ignore the error code and 565 * reset it to 0. 566 * Since the firmware is crashed we will not send IPC messages 567 * and we are going to see errors printed, but the state of the 568 * widgets will be correct for the next boot. 569 */ 570 if (sdev->fw_state != SOF_FW_CRASHED || state != SOF_IPC4_PIPE_RESET) 571 goto free; 572 573 ret = 0; 574 } 575 576 /* update RUNNING/RESET state for all pipelines that were just triggered */ 577 for (i = 0; i < pipeline_list->count; i++) { 578 spipe = pipeline_list->pipelines[i]; 579 sof_ipc4_update_pipeline_state(sdev, state, cmd, spipe, trigger_list); 580 } 581 582 free: 583 kfree(trigger_list); 584 kfree(pipe_priority); 585 return ret; 586 } 587 588 static int sof_ipc4_pcm_trigger(struct snd_soc_component *component, 589 struct snd_pcm_substream *substream, int cmd) 590 { 591 int state; 592 593 /* determine the pipeline state */ 594 switch (cmd) { 595 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 596 case SNDRV_PCM_TRIGGER_RESUME: 597 case SNDRV_PCM_TRIGGER_START: 598 state = SOF_IPC4_PIPE_RUNNING; 599 break; 600 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 601 case SNDRV_PCM_TRIGGER_SUSPEND: 602 case SNDRV_PCM_TRIGGER_STOP: 603 state = SOF_IPC4_PIPE_PAUSED; 604 break; 605 default: 606 dev_err(component->dev, "%s: unhandled trigger cmd %d\n", __func__, cmd); 607 return -EINVAL; 608 } 609 610 /* set the pipeline state */ 611 return sof_ipc4_trigger_pipelines(component, substream, state, cmd); 612 } 613 614 static int sof_ipc4_pcm_hw_free(struct snd_soc_component *component, 615 struct snd_pcm_substream *substream) 616 { 617 /* command is not relevant with RESET, so just pass 0 */ 618 return sof_ipc4_trigger_pipelines(component, substream, SOF_IPC4_PIPE_RESET, 0); 619 } 620 621 static int ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev *sdev, 622 const char *link_name, 623 struct snd_pcm_hw_params *params) 624 { 625 struct snd_sof_dai_link *slink; 626 struct snd_sof_dai *dai; 627 bool dai_link_found = false; 628 int current_config = -1; 629 bool partial_match; 630 int i; 631 632 list_for_each_entry(slink, &sdev->dai_link_list, list) { 633 if (!strcmp(slink->link->name, link_name)) { 634 dai_link_found = true; 635 break; 636 } 637 } 638 639 if (!dai_link_found) 640 return 0; 641 642 /* 643 * Find the first best matching hardware config: 644 * rate + format + channels are matching 645 * rate + channel are matching 646 * 647 * The copier cannot do rate and/or channel conversion. 648 */ 649 for (i = 0; i < slink->num_hw_configs; i++) { 650 struct snd_soc_tplg_hw_config *hw_config = &slink->hw_configs[i]; 651 652 if (params_rate(params) == le32_to_cpu(hw_config->fsync_rate) && 653 params_width(params) == le32_to_cpu(hw_config->tdm_slot_width) && 654 params_channels(params) <= le32_to_cpu(hw_config->tdm_slots)) { 655 current_config = le32_to_cpu(hw_config->id); 656 partial_match = false; 657 /* best match found */ 658 break; 659 } else if (current_config < 0 && 660 params_rate(params) == le32_to_cpu(hw_config->fsync_rate) && 661 params_channels(params) <= le32_to_cpu(hw_config->tdm_slots)) { 662 current_config = le32_to_cpu(hw_config->id); 663 partial_match = true; 664 /* keep looking for better match */ 665 } 666 } 667 668 if (current_config < 0) { 669 dev_err(sdev->dev, 670 "%s: No suitable hw_config found for %s (num_hw_configs: %d)\n", 671 __func__, slink->link->name, slink->num_hw_configs); 672 return -EINVAL; 673 } 674 675 dev_dbg(sdev->dev, 676 "hw_config for %s: %d (num_hw_configs: %d) with %s match\n", 677 slink->link->name, current_config, slink->num_hw_configs, 678 partial_match ? "partial" : "full"); 679 list_for_each_entry(dai, &sdev->dai_list, list) 680 if (!strcmp(slink->link->name, dai->name)) 681 dai->current_config = current_config; 682 683 return 0; 684 } 685 686 /* 687 * Fixup DAI link parameters for sampling rate based on 688 * DAI copier configuration. 689 */ 690 static int sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev *sdev, 691 struct snd_pcm_hw_params *params, 692 struct sof_ipc4_copier *ipc4_copier) 693 { 694 struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts; 695 struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 696 int num_input_formats = ipc4_copier->available_fmt.num_input_formats; 697 unsigned int fe_rate = params_rate(params); 698 bool fe_be_rate_match = false; 699 bool single_be_rate = true; 700 unsigned int be_rate; 701 int i; 702 703 if (WARN_ON_ONCE(!num_input_formats)) 704 return -EINVAL; 705 706 /* 707 * Copier does not change sampling rate, so we 708 * need to only consider the input pin information. 709 */ 710 be_rate = pin_fmts[0].audio_fmt.sampling_frequency; 711 for (i = 0; i < num_input_formats; i++) { 712 unsigned int val = pin_fmts[i].audio_fmt.sampling_frequency; 713 714 if (val != be_rate) 715 single_be_rate = false; 716 717 if (val == fe_rate) { 718 fe_be_rate_match = true; 719 break; 720 } 721 } 722 723 /* 724 * If rate is different than FE rate, topology must 725 * contain an SRC. But we do require topology to 726 * define a single rate in the DAI copier config in 727 * this case (FE rate may be variable). 728 */ 729 if (!fe_be_rate_match) { 730 if (!single_be_rate) { 731 dev_err(sdev->dev, "Unable to select sampling rate for DAI link\n"); 732 return -EINVAL; 733 } 734 735 rate->min = be_rate; 736 rate->max = rate->min; 737 } 738 739 return 0; 740 } 741 742 static int sof_ipc4_pcm_dai_link_fixup_channels(struct snd_sof_dev *sdev, 743 struct snd_pcm_hw_params *params, 744 struct sof_ipc4_copier *ipc4_copier) 745 { 746 struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts; 747 struct snd_interval *channels = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 748 int num_input_formats = ipc4_copier->available_fmt.num_input_formats; 749 unsigned int fe_channels = params_channels(params); 750 bool fe_be_match = false; 751 bool single_be_channels = true; 752 unsigned int be_channels, val; 753 int i; 754 755 if (WARN_ON_ONCE(!num_input_formats)) 756 return -EINVAL; 757 758 /* 759 * Copier does not change channels, so we 760 * need to only consider the input pin information. 761 */ 762 be_channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(pin_fmts[0].audio_fmt.fmt_cfg); 763 for (i = 0; i < num_input_formats; i++) { 764 val = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(pin_fmts[i].audio_fmt.fmt_cfg); 765 766 if (val != be_channels) 767 single_be_channels = false; 768 769 if (val == fe_channels) { 770 fe_be_match = true; 771 break; 772 } 773 } 774 775 /* 776 * If channels is different than FE channels, topology must contain a 777 * module which can change the number of channels. But we do require 778 * topology to define a single channels in the DAI copier config in 779 * this case (FE channels may be variable). 780 */ 781 if (!fe_be_match) { 782 if (!single_be_channels) { 783 dev_err(sdev->dev, "Unable to select channels for DAI link\n"); 784 return -EINVAL; 785 } 786 787 channels->min = be_channels; 788 channels->max = be_channels; 789 } 790 791 return 0; 792 } 793 794 static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd, 795 struct snd_pcm_hw_params *params) 796 { 797 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME); 798 struct snd_sof_dai *dai = snd_sof_find_dai(component, rtd->dai_link->name); 799 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 800 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component); 801 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 802 struct sof_ipc4_audio_format *ipc4_fmt; 803 struct sof_ipc4_copier *ipc4_copier; 804 bool single_bitdepth = false; 805 u32 valid_bits = 0; 806 int dir, ret; 807 808 if (!dai) { 809 dev_err(component->dev, "%s: No DAI found with name %s\n", __func__, 810 rtd->dai_link->name); 811 return -EINVAL; 812 } 813 814 ipc4_copier = dai->private; 815 if (!ipc4_copier) { 816 dev_err(component->dev, "%s: No private data found for DAI %s\n", 817 __func__, rtd->dai_link->name); 818 return -EINVAL; 819 } 820 821 for_each_pcm_streams(dir) { 822 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(cpu_dai, dir); 823 824 if (w) { 825 struct sof_ipc4_available_audio_format *available_fmt = 826 &ipc4_copier->available_fmt; 827 struct snd_sof_widget *swidget = w->dobj.private; 828 struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget; 829 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; 830 831 /* Chain DMA does not use copiers, so no fixup needed */ 832 if (pipeline->use_chain_dma) 833 return 0; 834 835 if (dir == SNDRV_PCM_STREAM_PLAYBACK) { 836 if (sof_ipc4_copier_is_single_bitdepth(sdev, 837 available_fmt->output_pin_fmts, 838 available_fmt->num_output_formats)) { 839 ipc4_fmt = &available_fmt->output_pin_fmts->audio_fmt; 840 single_bitdepth = true; 841 } 842 } else { 843 if (sof_ipc4_copier_is_single_bitdepth(sdev, 844 available_fmt->input_pin_fmts, 845 available_fmt->num_input_formats)) { 846 ipc4_fmt = &available_fmt->input_pin_fmts->audio_fmt; 847 single_bitdepth = true; 848 } 849 } 850 } 851 } 852 853 ret = sof_ipc4_pcm_dai_link_fixup_rate(sdev, params, ipc4_copier); 854 if (ret) 855 return ret; 856 857 ret = sof_ipc4_pcm_dai_link_fixup_channels(sdev, params, ipc4_copier); 858 if (ret) 859 return ret; 860 861 if (single_bitdepth) { 862 snd_mask_none(fmt); 863 valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(ipc4_fmt->fmt_cfg); 864 dev_dbg(component->dev, "Set %s to %d bit format\n", dai->name, valid_bits); 865 } 866 867 /* Set format if it is specified */ 868 switch (valid_bits) { 869 case 16: 870 snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE); 871 break; 872 case 24: 873 snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE); 874 break; 875 case 32: 876 snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S32_LE); 877 break; 878 default: 879 break; 880 } 881 882 if (ipc4_copier->dai_type == SOF_DAI_INTEL_SSP) 883 return ipc4_ssp_dai_config_pcm_params_match(sdev, 884 (char *)rtd->dai_link->name, 885 params); 886 887 return 0; 888 } 889 890 static void sof_ipc4_pcm_free(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm) 891 { 892 struct snd_sof_pcm_stream_pipeline_list *pipeline_list; 893 struct sof_ipc4_pcm_stream_priv *stream_priv; 894 int stream; 895 896 for_each_pcm_streams(stream) { 897 pipeline_list = &spcm->stream[stream].pipeline_list; 898 kfree(pipeline_list->pipelines); 899 pipeline_list->pipelines = NULL; 900 901 stream_priv = spcm->stream[stream].private; 902 kfree(stream_priv->time_info); 903 kfree(spcm->stream[stream].private); 904 spcm->stream[stream].private = NULL; 905 } 906 } 907 908 static int sof_ipc4_pcm_setup(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm) 909 { 910 struct snd_sof_pcm_stream_pipeline_list *pipeline_list; 911 struct sof_ipc4_fw_data *ipc4_data = sdev->private; 912 struct sof_ipc4_pcm_stream_priv *stream_priv; 913 struct sof_ipc4_timestamp_info *time_info; 914 bool support_info = true; 915 u32 abi_version; 916 u32 abi_offset; 917 int stream; 918 919 abi_offset = offsetof(struct sof_ipc4_fw_registers, abi_ver); 920 sof_mailbox_read(sdev, sdev->fw_info_box.offset + abi_offset, &abi_version, 921 sizeof(abi_version)); 922 923 if (abi_version < SOF_IPC4_FW_REGS_ABI_VER) 924 support_info = false; 925 926 /* For delay reporting the get_host_byte_counter callback is needed */ 927 if (!sof_ops(sdev) || !sof_ops(sdev)->get_host_byte_counter) 928 support_info = false; 929 930 for_each_pcm_streams(stream) { 931 pipeline_list = &spcm->stream[stream].pipeline_list; 932 933 /* allocate memory for max number of pipeline IDs */ 934 pipeline_list->pipelines = kcalloc(ipc4_data->max_num_pipelines, 935 sizeof(*pipeline_list->pipelines), 936 GFP_KERNEL); 937 if (!pipeline_list->pipelines) { 938 sof_ipc4_pcm_free(sdev, spcm); 939 return -ENOMEM; 940 } 941 942 stream_priv = kzalloc(sizeof(*stream_priv), GFP_KERNEL); 943 if (!stream_priv) { 944 sof_ipc4_pcm_free(sdev, spcm); 945 return -ENOMEM; 946 } 947 948 spcm->stream[stream].private = stream_priv; 949 950 /* Delay reporting is only supported on playback */ 951 if (!support_info || stream == SNDRV_PCM_STREAM_CAPTURE) 952 continue; 953 954 time_info = kzalloc(sizeof(*time_info), GFP_KERNEL); 955 if (!time_info) { 956 sof_ipc4_pcm_free(sdev, spcm); 957 return -ENOMEM; 958 } 959 960 stream_priv->time_info = time_info; 961 } 962 963 return 0; 964 } 965 966 static void sof_ipc4_build_time_info(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps) 967 { 968 struct sof_ipc4_copier *host_copier = NULL; 969 struct sof_ipc4_copier *dai_copier = NULL; 970 struct sof_ipc4_llp_reading_slot llp_slot; 971 struct sof_ipc4_timestamp_info *time_info; 972 struct snd_soc_dapm_widget *widget; 973 struct snd_sof_dai *dai; 974 int i; 975 976 /* find host & dai to locate info in memory window */ 977 for_each_dapm_widgets(sps->list, i, widget) { 978 struct snd_sof_widget *swidget = widget->dobj.private; 979 980 if (!swidget) 981 continue; 982 983 if (WIDGET_IS_AIF(swidget->widget->id)) { 984 host_copier = swidget->private; 985 } else if (WIDGET_IS_DAI(swidget->widget->id)) { 986 dai = swidget->private; 987 dai_copier = dai->private; 988 } 989 } 990 991 /* both host and dai copier must be valid for time_info */ 992 if (!host_copier || !dai_copier) { 993 dev_err(sdev->dev, "host or dai copier are not found\n"); 994 return; 995 } 996 997 time_info = sof_ipc4_sps_to_time_info(sps); 998 time_info->host_copier = host_copier; 999 time_info->dai_copier = dai_copier; 1000 time_info->llp_offset = offsetof(struct sof_ipc4_fw_registers, 1001 llp_gpdma_reading_slots) + sdev->fw_info_box.offset; 1002 1003 /* find llp slot used by current dai */ 1004 for (i = 0; i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS; i++) { 1005 sof_mailbox_read(sdev, time_info->llp_offset, &llp_slot, sizeof(llp_slot)); 1006 if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id) 1007 break; 1008 1009 time_info->llp_offset += sizeof(llp_slot); 1010 } 1011 1012 if (i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS) 1013 return; 1014 1015 /* if no llp gpdma slot is used, check aggregated sdw slot */ 1016 time_info->llp_offset = offsetof(struct sof_ipc4_fw_registers, 1017 llp_sndw_reading_slots) + sdev->fw_info_box.offset; 1018 for (i = 0; i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS; i++) { 1019 sof_mailbox_read(sdev, time_info->llp_offset, &llp_slot, sizeof(llp_slot)); 1020 if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id) 1021 break; 1022 1023 time_info->llp_offset += sizeof(llp_slot); 1024 } 1025 1026 if (i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS) 1027 return; 1028 1029 /* check EVAD slot */ 1030 time_info->llp_offset = offsetof(struct sof_ipc4_fw_registers, 1031 llp_evad_reading_slot) + sdev->fw_info_box.offset; 1032 sof_mailbox_read(sdev, time_info->llp_offset, &llp_slot, sizeof(llp_slot)); 1033 if (llp_slot.node_id != dai_copier->data.gtw_cfg.node_id) 1034 time_info->llp_offset = 0; 1035 } 1036 1037 static int sof_ipc4_pcm_hw_params(struct snd_soc_component *component, 1038 struct snd_pcm_substream *substream, 1039 struct snd_pcm_hw_params *params, 1040 struct snd_sof_platform_stream_params *platform_params) 1041 { 1042 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component); 1043 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1044 struct sof_ipc4_timestamp_info *time_info; 1045 struct snd_sof_pcm *spcm; 1046 1047 spcm = snd_sof_find_spcm_dai(component, rtd); 1048 if (!spcm) 1049 return -EINVAL; 1050 1051 time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]); 1052 /* delay calculation is not supported by current fw_reg ABI */ 1053 if (!time_info) 1054 return 0; 1055 1056 time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION; 1057 time_info->llp_offset = 0; 1058 1059 sof_ipc4_build_time_info(sdev, &spcm->stream[substream->stream]); 1060 1061 return 0; 1062 } 1063 1064 static u64 sof_ipc4_frames_dai_to_host(struct sof_ipc4_timestamp_info *time_info, u64 value) 1065 { 1066 u64 dai_rate, host_rate; 1067 1068 if (!time_info->dai_copier || !time_info->host_copier) 1069 return value; 1070 1071 /* 1072 * copiers do not change sampling rate, so we can use the 1073 * out_format independently of stream direction 1074 */ 1075 dai_rate = time_info->dai_copier->data.out_format.sampling_frequency; 1076 host_rate = time_info->host_copier->data.out_format.sampling_frequency; 1077 1078 if (!dai_rate || !host_rate || dai_rate == host_rate) 1079 return value; 1080 1081 /* take care not to overflow u64, rates can be up to 768000 */ 1082 if (value > U32_MAX) { 1083 value = div64_u64(value, dai_rate); 1084 value *= host_rate; 1085 } else { 1086 value *= host_rate; 1087 value = div64_u64(value, dai_rate); 1088 } 1089 1090 return value; 1091 } 1092 1093 static int sof_ipc4_get_stream_start_offset(struct snd_sof_dev *sdev, 1094 struct snd_pcm_substream *substream, 1095 struct snd_sof_pcm_stream *sps, 1096 struct sof_ipc4_timestamp_info *time_info) 1097 { 1098 struct sof_ipc4_copier *host_copier = time_info->host_copier; 1099 struct sof_ipc4_copier *dai_copier = time_info->dai_copier; 1100 struct sof_ipc4_pipeline_registers ppl_reg; 1101 u32 dai_sample_size; 1102 u32 ch, node_index; 1103 u32 offset; 1104 1105 if (!host_copier || !dai_copier) 1106 return -EINVAL; 1107 1108 if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_INVALID_NODE_ID) { 1109 return -EINVAL; 1110 } else if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_CHAIN_DMA_NODE_ID) { 1111 /* 1112 * While the firmware does not support time_info reporting for 1113 * streams using ChainDMA, it is granted that ChainDMA can only 1114 * be used on Host+Link pairs where the link position is 1115 * accessible from the host side. 1116 * 1117 * Enable delay calculation in case of ChainDMA via host 1118 * accessible registers. 1119 * 1120 * The ChainDMA prefills the link DMA with a preamble 1121 * of zero samples. Set the stream start offset based 1122 * on size of the preamble (driver provided fifo size 1123 * multiplied by 2.5). We add 1ms of margin as the FW 1124 * will align the buffer size to DMA hardware 1125 * alignment that is not known to host. 1126 */ 1127 int pre_ms = SOF_IPC4_CHAIN_DMA_BUF_SIZE_MS * 5 / 2 + 1; 1128 1129 time_info->stream_start_offset = pre_ms * substream->runtime->rate / MSEC_PER_SEC; 1130 goto out; 1131 } 1132 1133 node_index = SOF_IPC4_NODE_INDEX(host_copier->data.gtw_cfg.node_id); 1134 offset = offsetof(struct sof_ipc4_fw_registers, pipeline_regs) + node_index * sizeof(ppl_reg); 1135 sof_mailbox_read(sdev, sdev->fw_info_box.offset + offset, &ppl_reg, sizeof(ppl_reg)); 1136 if (ppl_reg.stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION) 1137 return -EINVAL; 1138 1139 ch = dai_copier->data.out_format.fmt_cfg; 1140 ch = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(ch); 1141 dai_sample_size = (dai_copier->data.out_format.bit_depth >> 3) * ch; 1142 1143 /* convert offsets to frame count */ 1144 time_info->stream_start_offset = ppl_reg.stream_start_offset; 1145 do_div(time_info->stream_start_offset, dai_sample_size); 1146 time_info->stream_end_offset = ppl_reg.stream_end_offset; 1147 do_div(time_info->stream_end_offset, dai_sample_size); 1148 1149 /* convert to host frame time */ 1150 time_info->stream_start_offset = 1151 sof_ipc4_frames_dai_to_host(time_info, time_info->stream_start_offset); 1152 time_info->stream_end_offset = 1153 sof_ipc4_frames_dai_to_host(time_info, time_info->stream_end_offset); 1154 1155 out: 1156 /* Initialize the delay value to 0 (no delay) */ 1157 time_info->delay = 0; 1158 1159 return 0; 1160 } 1161 1162 static int sof_ipc4_pcm_pointer(struct snd_soc_component *component, 1163 struct snd_pcm_substream *substream, 1164 snd_pcm_uframes_t *pointer) 1165 { 1166 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component); 1167 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1168 struct sof_ipc4_timestamp_info *time_info; 1169 struct sof_ipc4_llp_reading_slot llp; 1170 snd_pcm_uframes_t head_cnt, tail_cnt; 1171 struct snd_sof_pcm_stream *sps; 1172 u64 dai_cnt, host_cnt, host_ptr; 1173 struct snd_sof_pcm *spcm; 1174 int ret; 1175 1176 spcm = snd_sof_find_spcm_dai(component, rtd); 1177 if (!spcm) 1178 return -EOPNOTSUPP; 1179 1180 sps = &spcm->stream[substream->stream]; 1181 time_info = sof_ipc4_sps_to_time_info(sps); 1182 if (!time_info) 1183 return -EOPNOTSUPP; 1184 1185 /* 1186 * stream_start_offset is updated to memory window by FW based on 1187 * pipeline statistics and it may be invalid if host query happens before 1188 * the statistics is complete. And it will not change after the first initiailization. 1189 */ 1190 if (time_info->stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION) { 1191 ret = sof_ipc4_get_stream_start_offset(sdev, substream, sps, time_info); 1192 if (ret < 0) 1193 return -EOPNOTSUPP; 1194 } 1195 1196 /* For delay calculation we need the host counter */ 1197 host_cnt = snd_sof_pcm_get_host_byte_counter(sdev, component, substream); 1198 1199 /* Store the original value to host_ptr */ 1200 host_ptr = host_cnt; 1201 1202 /* convert the host_cnt to frames */ 1203 host_cnt = div64_u64(host_cnt, frames_to_bytes(substream->runtime, 1)); 1204 1205 /* 1206 * If the LLP counter is not reported by firmware in the SRAM window 1207 * then read the dai (link) counter via host accessible means if 1208 * available. 1209 */ 1210 if (!time_info->llp_offset) { 1211 dai_cnt = snd_sof_pcm_get_dai_frame_counter(sdev, component, substream); 1212 if (!dai_cnt) 1213 return -EOPNOTSUPP; 1214 } else { 1215 sof_mailbox_read(sdev, time_info->llp_offset, &llp, sizeof(llp)); 1216 dai_cnt = ((u64)llp.reading.llp_u << 32) | llp.reading.llp_l; 1217 } 1218 1219 dai_cnt = sof_ipc4_frames_dai_to_host(time_info, dai_cnt); 1220 dai_cnt += time_info->stream_end_offset; 1221 1222 /* In two cases dai dma counter is not accurate 1223 * (1) dai pipeline is started before host pipeline 1224 * (2) multiple streams mixed into one. Each stream has the same dai dma 1225 * counter 1226 * 1227 * Firmware calculates correct stream_start_offset for all cases 1228 * including above two. 1229 * Driver subtracts stream_start_offset from dai dma counter to get 1230 * accurate one 1231 */ 1232 1233 /* 1234 * On stream start the dai counter might not yet have reached the 1235 * stream_start_offset value which means that no frames have left the 1236 * DSP yet from the audio stream (on playback, capture streams have 1237 * offset of 0 as we start capturing right away). 1238 * In this case we need to adjust the distance between the counters by 1239 * increasing the host counter by (offset - dai_counter). 1240 * Otherwise the dai_counter needs to be adjusted to reflect the number 1241 * of valid frames passed on the DAI side. 1242 * 1243 * The delay is the difference between the counters on the two 1244 * sides of the DSP. 1245 */ 1246 if (dai_cnt < time_info->stream_start_offset) { 1247 host_cnt += time_info->stream_start_offset - dai_cnt; 1248 dai_cnt = 0; 1249 } else { 1250 dai_cnt -= time_info->stream_start_offset; 1251 } 1252 1253 /* Convert to a common base before comparisons */ 1254 dai_cnt &= DELAY_BOUNDARY; 1255 host_cnt &= DELAY_BOUNDARY; 1256 1257 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1258 head_cnt = host_cnt; 1259 tail_cnt = dai_cnt; 1260 } else { 1261 head_cnt = dai_cnt; 1262 tail_cnt = host_cnt; 1263 } 1264 1265 if (unlikely(head_cnt < tail_cnt)) 1266 time_info->delay = DELAY_BOUNDARY - tail_cnt + head_cnt; 1267 else 1268 time_info->delay = head_cnt - tail_cnt; 1269 1270 if (time_info->delay > DELAY_MAX) { 1271 spcm_dbg_ratelimited(spcm, substream->stream, 1272 "inaccurate delay, host %llu dai_cnt %llu", 1273 host_cnt, dai_cnt); 1274 time_info->delay = 0; 1275 } 1276 1277 /* 1278 * Convert the host byte counter to PCM pointer which wraps in buffer 1279 * and it is in frames 1280 */ 1281 div64_u64_rem(host_ptr, snd_pcm_lib_buffer_bytes(substream), &host_ptr); 1282 *pointer = bytes_to_frames(substream->runtime, host_ptr); 1283 1284 return 0; 1285 } 1286 1287 static snd_pcm_sframes_t sof_ipc4_pcm_delay(struct snd_soc_component *component, 1288 struct snd_pcm_substream *substream) 1289 { 1290 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1291 struct sof_ipc4_timestamp_info *time_info; 1292 struct snd_sof_pcm *spcm; 1293 1294 spcm = snd_sof_find_spcm_dai(component, rtd); 1295 if (!spcm) 1296 return 0; 1297 1298 time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]); 1299 /* 1300 * Report the stored delay value calculated in the pointer callback. 1301 * In the unlikely event that the calculation was skipped/aborted, the 1302 * default 0 delay returned. 1303 */ 1304 if (time_info) 1305 return time_info->delay; 1306 1307 /* No delay information available, report 0 as delay */ 1308 return 0; 1309 1310 } 1311 1312 const struct sof_ipc_pcm_ops ipc4_pcm_ops = { 1313 .hw_params = sof_ipc4_pcm_hw_params, 1314 .trigger = sof_ipc4_pcm_trigger, 1315 .hw_free = sof_ipc4_pcm_hw_free, 1316 .dai_link_fixup = sof_ipc4_pcm_dai_link_fixup, 1317 .pcm_setup = sof_ipc4_pcm_setup, 1318 .pcm_free = sof_ipc4_pcm_free, 1319 .pointer = sof_ipc4_pcm_pointer, 1320 .delay = sof_ipc4_pcm_delay, 1321 .ipc_first_on_start = true, 1322 .platform_stop_during_hw_free = true, 1323 }; 1324