1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021 Intel Corporation. All rights reserved. 7 // 8 // 9 10 #include <sound/sof/stream.h> 11 #include <sound/sof/control.h> 12 #include "sof-priv.h" 13 #include "sof-audio.h" 14 #include "ipc3-ops.h" 15 #include "ops.h" 16 17 typedef void (*ipc3_rx_callback)(struct snd_sof_dev *sdev, void *msg_buf); 18 19 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC) 20 static void ipc3_log_header(struct device *dev, u8 *text, u32 cmd) 21 { 22 u8 *str; 23 u8 *str2 = NULL; 24 u32 glb; 25 u32 type; 26 bool vdbg = false; 27 28 glb = cmd & SOF_GLB_TYPE_MASK; 29 type = cmd & SOF_CMD_TYPE_MASK; 30 31 switch (glb) { 32 case SOF_IPC_GLB_REPLY: 33 str = "GLB_REPLY"; break; 34 case SOF_IPC_GLB_COMPOUND: 35 str = "GLB_COMPOUND"; break; 36 case SOF_IPC_GLB_TPLG_MSG: 37 str = "GLB_TPLG_MSG"; 38 switch (type) { 39 case SOF_IPC_TPLG_COMP_NEW: 40 str2 = "COMP_NEW"; break; 41 case SOF_IPC_TPLG_COMP_FREE: 42 str2 = "COMP_FREE"; break; 43 case SOF_IPC_TPLG_COMP_CONNECT: 44 str2 = "COMP_CONNECT"; break; 45 case SOF_IPC_TPLG_PIPE_NEW: 46 str2 = "PIPE_NEW"; break; 47 case SOF_IPC_TPLG_PIPE_FREE: 48 str2 = "PIPE_FREE"; break; 49 case SOF_IPC_TPLG_PIPE_CONNECT: 50 str2 = "PIPE_CONNECT"; break; 51 case SOF_IPC_TPLG_PIPE_COMPLETE: 52 str2 = "PIPE_COMPLETE"; break; 53 case SOF_IPC_TPLG_BUFFER_NEW: 54 str2 = "BUFFER_NEW"; break; 55 case SOF_IPC_TPLG_BUFFER_FREE: 56 str2 = "BUFFER_FREE"; break; 57 default: 58 str2 = "unknown type"; break; 59 } 60 break; 61 case SOF_IPC_GLB_PM_MSG: 62 str = "GLB_PM_MSG"; 63 switch (type) { 64 case SOF_IPC_PM_CTX_SAVE: 65 str2 = "CTX_SAVE"; break; 66 case SOF_IPC_PM_CTX_RESTORE: 67 str2 = "CTX_RESTORE"; break; 68 case SOF_IPC_PM_CTX_SIZE: 69 str2 = "CTX_SIZE"; break; 70 case SOF_IPC_PM_CLK_SET: 71 str2 = "CLK_SET"; break; 72 case SOF_IPC_PM_CLK_GET: 73 str2 = "CLK_GET"; break; 74 case SOF_IPC_PM_CLK_REQ: 75 str2 = "CLK_REQ"; break; 76 case SOF_IPC_PM_CORE_ENABLE: 77 str2 = "CORE_ENABLE"; break; 78 case SOF_IPC_PM_GATE: 79 str2 = "GATE"; break; 80 default: 81 str2 = "unknown type"; break; 82 } 83 break; 84 case SOF_IPC_GLB_COMP_MSG: 85 str = "GLB_COMP_MSG"; 86 switch (type) { 87 case SOF_IPC_COMP_SET_VALUE: 88 str2 = "SET_VALUE"; break; 89 case SOF_IPC_COMP_GET_VALUE: 90 str2 = "GET_VALUE"; break; 91 case SOF_IPC_COMP_SET_DATA: 92 str2 = "SET_DATA"; break; 93 case SOF_IPC_COMP_GET_DATA: 94 str2 = "GET_DATA"; break; 95 default: 96 str2 = "unknown type"; break; 97 } 98 break; 99 case SOF_IPC_GLB_STREAM_MSG: 100 str = "GLB_STREAM_MSG"; 101 switch (type) { 102 case SOF_IPC_STREAM_PCM_PARAMS: 103 str2 = "PCM_PARAMS"; break; 104 case SOF_IPC_STREAM_PCM_PARAMS_REPLY: 105 str2 = "PCM_REPLY"; break; 106 case SOF_IPC_STREAM_PCM_FREE: 107 str2 = "PCM_FREE"; break; 108 case SOF_IPC_STREAM_TRIG_START: 109 str2 = "TRIG_START"; break; 110 case SOF_IPC_STREAM_TRIG_STOP: 111 str2 = "TRIG_STOP"; break; 112 case SOF_IPC_STREAM_TRIG_PAUSE: 113 str2 = "TRIG_PAUSE"; break; 114 case SOF_IPC_STREAM_TRIG_RELEASE: 115 str2 = "TRIG_RELEASE"; break; 116 case SOF_IPC_STREAM_TRIG_DRAIN: 117 str2 = "TRIG_DRAIN"; break; 118 case SOF_IPC_STREAM_TRIG_XRUN: 119 str2 = "TRIG_XRUN"; break; 120 case SOF_IPC_STREAM_POSITION: 121 vdbg = true; 122 str2 = "POSITION"; break; 123 case SOF_IPC_STREAM_VORBIS_PARAMS: 124 str2 = "VORBIS_PARAMS"; break; 125 case SOF_IPC_STREAM_VORBIS_FREE: 126 str2 = "VORBIS_FREE"; break; 127 default: 128 str2 = "unknown type"; break; 129 } 130 break; 131 case SOF_IPC_FW_READY: 132 str = "FW_READY"; break; 133 case SOF_IPC_GLB_DAI_MSG: 134 str = "GLB_DAI_MSG"; 135 switch (type) { 136 case SOF_IPC_DAI_CONFIG: 137 str2 = "CONFIG"; break; 138 case SOF_IPC_DAI_LOOPBACK: 139 str2 = "LOOPBACK"; break; 140 default: 141 str2 = "unknown type"; break; 142 } 143 break; 144 case SOF_IPC_GLB_TRACE_MSG: 145 str = "GLB_TRACE_MSG"; 146 switch (type) { 147 case SOF_IPC_TRACE_DMA_PARAMS: 148 str2 = "DMA_PARAMS"; break; 149 case SOF_IPC_TRACE_DMA_POSITION: 150 str2 = "DMA_POSITION"; break; 151 case SOF_IPC_TRACE_DMA_PARAMS_EXT: 152 str2 = "DMA_PARAMS_EXT"; break; 153 case SOF_IPC_TRACE_FILTER_UPDATE: 154 str2 = "FILTER_UPDATE"; break; 155 case SOF_IPC_TRACE_DMA_FREE: 156 str2 = "DMA_FREE"; break; 157 default: 158 str2 = "unknown type"; break; 159 } 160 break; 161 case SOF_IPC_GLB_TEST_MSG: 162 str = "GLB_TEST_MSG"; 163 switch (type) { 164 case SOF_IPC_TEST_IPC_FLOOD: 165 str2 = "IPC_FLOOD"; break; 166 default: 167 str2 = "unknown type"; break; 168 } 169 break; 170 case SOF_IPC_GLB_DEBUG: 171 str = "GLB_DEBUG"; 172 switch (type) { 173 case SOF_IPC_DEBUG_MEM_USAGE: 174 str2 = "MEM_USAGE"; break; 175 default: 176 str2 = "unknown type"; break; 177 } 178 break; 179 case SOF_IPC_GLB_PROBE: 180 str = "GLB_PROBE"; 181 switch (type) { 182 case SOF_IPC_PROBE_INIT: 183 str2 = "INIT"; break; 184 case SOF_IPC_PROBE_DEINIT: 185 str2 = "DEINIT"; break; 186 case SOF_IPC_PROBE_DMA_ADD: 187 str2 = "DMA_ADD"; break; 188 case SOF_IPC_PROBE_DMA_INFO: 189 str2 = "DMA_INFO"; break; 190 case SOF_IPC_PROBE_DMA_REMOVE: 191 str2 = "DMA_REMOVE"; break; 192 case SOF_IPC_PROBE_POINT_ADD: 193 str2 = "POINT_ADD"; break; 194 case SOF_IPC_PROBE_POINT_INFO: 195 str2 = "POINT_INFO"; break; 196 case SOF_IPC_PROBE_POINT_REMOVE: 197 str2 = "POINT_REMOVE"; break; 198 default: 199 str2 = "unknown type"; break; 200 } 201 break; 202 default: 203 str = "unknown GLB command"; break; 204 } 205 206 if (str2) { 207 if (vdbg) 208 dev_vdbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2); 209 else 210 dev_dbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2); 211 } else { 212 dev_dbg(dev, "%s: 0x%x: %s\n", text, cmd, str); 213 } 214 } 215 #else 216 static inline void ipc3_log_header(struct device *dev, u8 *text, u32 cmd) 217 { 218 if ((cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_TRACE_MSG) 219 dev_dbg(dev, "%s: 0x%x\n", text, cmd); 220 } 221 #endif 222 223 static int sof_ipc3_get_reply(struct snd_sof_dev *sdev) 224 { 225 struct snd_sof_ipc_msg *msg = sdev->msg; 226 struct sof_ipc_reply *reply; 227 int ret = 0; 228 229 /* get the generic reply */ 230 reply = msg->reply_data; 231 snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset, reply, sizeof(*reply)); 232 233 if (reply->error < 0) 234 return reply->error; 235 236 if (!reply->hdr.size) { 237 /* Reply should always be >= sizeof(struct sof_ipc_reply) */ 238 if (msg->reply_size) 239 dev_err(sdev->dev, 240 "empty reply received, expected %zu bytes\n", 241 msg->reply_size); 242 else 243 dev_err(sdev->dev, "empty reply received\n"); 244 245 return -EINVAL; 246 } 247 248 if (msg->reply_size > 0) { 249 if (reply->hdr.size == msg->reply_size) { 250 ret = 0; 251 } else if (reply->hdr.size < msg->reply_size) { 252 dev_dbg(sdev->dev, 253 "reply size (%u) is less than expected (%zu)\n", 254 reply->hdr.size, msg->reply_size); 255 256 msg->reply_size = reply->hdr.size; 257 ret = 0; 258 } else { 259 dev_err(sdev->dev, 260 "reply size (%u) exceeds the buffer size (%zu)\n", 261 reply->hdr.size, msg->reply_size); 262 ret = -EINVAL; 263 } 264 265 /* 266 * get the full message if reply->hdr.size <= msg->reply_size 267 * and the reply->hdr.size > sizeof(struct sof_ipc_reply) 268 */ 269 if (!ret && msg->reply_size > sizeof(*reply)) 270 snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset, 271 msg->reply_data, msg->reply_size); 272 } 273 274 return ret; 275 } 276 277 /* wait for IPC message reply */ 278 static int ipc3_wait_tx_done(struct snd_sof_ipc *ipc, void *reply_data) 279 { 280 struct snd_sof_ipc_msg *msg = &ipc->msg; 281 struct sof_ipc_cmd_hdr *hdr = msg->msg_data; 282 struct snd_sof_dev *sdev = ipc->sdev; 283 int ret; 284 285 /* wait for DSP IPC completion */ 286 ret = wait_event_timeout(msg->waitq, msg->ipc_complete, 287 msecs_to_jiffies(sdev->ipc_timeout)); 288 289 if (ret == 0) { 290 dev_err(sdev->dev, 291 "ipc tx timed out for %#x (msg/reply size: %d/%zu)\n", 292 hdr->cmd, hdr->size, msg->reply_size); 293 snd_sof_handle_fw_exception(ipc->sdev); 294 ret = -ETIMEDOUT; 295 } else { 296 ret = msg->reply_error; 297 if (ret < 0) { 298 dev_err(sdev->dev, 299 "ipc tx error for %#x (msg/reply size: %d/%zu): %d\n", 300 hdr->cmd, hdr->size, msg->reply_size, ret); 301 } else { 302 ipc3_log_header(sdev->dev, "ipc tx succeeded", hdr->cmd); 303 if (msg->reply_size) 304 /* copy the data returned from DSP */ 305 memcpy(reply_data, msg->reply_data, 306 msg->reply_size); 307 } 308 309 /* re-enable dumps after successful IPC tx */ 310 if (sdev->ipc_dump_printed) { 311 sdev->dbg_dump_printed = false; 312 sdev->ipc_dump_printed = false; 313 } 314 } 315 316 return ret; 317 } 318 319 /* send IPC message from host to DSP */ 320 static int ipc3_tx_msg_unlocked(struct snd_sof_ipc *ipc, 321 void *msg_data, size_t msg_bytes, 322 void *reply_data, size_t reply_bytes) 323 { 324 struct sof_ipc_cmd_hdr *hdr = msg_data; 325 struct snd_sof_dev *sdev = ipc->sdev; 326 int ret; 327 328 ret = sof_ipc_send_msg(sdev, msg_data, msg_bytes, reply_bytes); 329 330 if (ret) { 331 dev_err_ratelimited(sdev->dev, 332 "%s: ipc message send for %#x failed: %d\n", 333 __func__, hdr->cmd, ret); 334 return ret; 335 } 336 337 ipc3_log_header(sdev->dev, "ipc tx", hdr->cmd); 338 339 /* now wait for completion */ 340 return ipc3_wait_tx_done(ipc, reply_data); 341 } 342 343 static int sof_ipc3_tx_msg(struct snd_sof_dev *sdev, void *msg_data, size_t msg_bytes, 344 void *reply_data, size_t reply_bytes, bool no_pm) 345 { 346 struct snd_sof_ipc *ipc = sdev->ipc; 347 int ret; 348 349 if (!msg_data || msg_bytes < sizeof(struct sof_ipc_cmd_hdr)) { 350 dev_err_ratelimited(sdev->dev, "No IPC message to send\n"); 351 return -EINVAL; 352 } 353 354 if (!no_pm) { 355 const struct sof_dsp_power_state target_state = { 356 .state = SOF_DSP_PM_D0, 357 }; 358 359 /* ensure the DSP is in D0 before sending a new IPC */ 360 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 361 if (ret < 0) { 362 dev_err(sdev->dev, "%s: resuming DSP failed: %d\n", 363 __func__, ret); 364 return ret; 365 } 366 } 367 368 /* Serialise IPC TX */ 369 mutex_lock(&ipc->tx_mutex); 370 371 ret = ipc3_tx_msg_unlocked(ipc, msg_data, msg_bytes, reply_data, reply_bytes); 372 373 mutex_unlock(&ipc->tx_mutex); 374 375 return ret; 376 } 377 378 static int sof_ipc3_set_get_data(struct snd_sof_dev *sdev, void *data, size_t data_bytes, 379 bool set) 380 { 381 size_t msg_bytes, hdr_bytes, payload_size, send_bytes; 382 struct sof_ipc_ctrl_data *cdata = data; 383 struct sof_ipc_ctrl_data *cdata_chunk; 384 struct snd_sof_ipc *ipc = sdev->ipc; 385 size_t offset = 0; 386 u8 *src, *dst; 387 u32 num_msg; 388 int ret = 0; 389 int i; 390 391 if (!cdata || data_bytes < sizeof(*cdata)) 392 return -EINVAL; 393 394 if ((cdata->rhdr.hdr.cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_COMP_MSG) { 395 dev_err(sdev->dev, "%s: Not supported message type of %#x\n", 396 __func__, cdata->rhdr.hdr.cmd); 397 return -EINVAL; 398 } 399 400 /* send normal size ipc in one part */ 401 if (cdata->rhdr.hdr.size <= ipc->max_payload_size) 402 return sof_ipc3_tx_msg(sdev, cdata, cdata->rhdr.hdr.size, 403 cdata, cdata->rhdr.hdr.size, false); 404 405 cdata_chunk = kzalloc(ipc->max_payload_size, GFP_KERNEL); 406 if (!cdata_chunk) 407 return -ENOMEM; 408 409 switch (cdata->type) { 410 case SOF_CTRL_TYPE_VALUE_CHAN_GET: 411 case SOF_CTRL_TYPE_VALUE_CHAN_SET: 412 hdr_bytes = sizeof(struct sof_ipc_ctrl_data); 413 if (set) { 414 src = (u8 *)cdata->chanv; 415 dst = (u8 *)cdata_chunk->chanv; 416 } else { 417 src = (u8 *)cdata_chunk->chanv; 418 dst = (u8 *)cdata->chanv; 419 } 420 break; 421 case SOF_CTRL_TYPE_DATA_GET: 422 case SOF_CTRL_TYPE_DATA_SET: 423 hdr_bytes = sizeof(struct sof_ipc_ctrl_data) + sizeof(struct sof_abi_hdr); 424 if (set) { 425 src = (u8 *)cdata->data->data; 426 dst = (u8 *)cdata_chunk->data->data; 427 } else { 428 src = (u8 *)cdata_chunk->data->data; 429 dst = (u8 *)cdata->data->data; 430 } 431 break; 432 default: 433 kfree(cdata_chunk); 434 return -EINVAL; 435 } 436 437 msg_bytes = cdata->rhdr.hdr.size - hdr_bytes; 438 payload_size = ipc->max_payload_size - hdr_bytes; 439 num_msg = DIV_ROUND_UP(msg_bytes, payload_size); 440 441 /* copy the header data */ 442 memcpy(cdata_chunk, cdata, hdr_bytes); 443 444 /* Serialise IPC TX */ 445 mutex_lock(&sdev->ipc->tx_mutex); 446 447 /* copy the payload data in a loop */ 448 for (i = 0; i < num_msg; i++) { 449 send_bytes = min(msg_bytes, payload_size); 450 cdata_chunk->num_elems = send_bytes; 451 cdata_chunk->rhdr.hdr.size = hdr_bytes + send_bytes; 452 cdata_chunk->msg_index = i; 453 msg_bytes -= send_bytes; 454 cdata_chunk->elems_remaining = msg_bytes; 455 456 if (set) 457 memcpy(dst, src + offset, send_bytes); 458 459 ret = ipc3_tx_msg_unlocked(sdev->ipc, 460 cdata_chunk, cdata_chunk->rhdr.hdr.size, 461 cdata_chunk, cdata_chunk->rhdr.hdr.size); 462 if (ret < 0) 463 break; 464 465 if (!set) 466 memcpy(dst + offset, src, send_bytes); 467 468 offset += payload_size; 469 } 470 471 mutex_unlock(&sdev->ipc->tx_mutex); 472 473 kfree(cdata_chunk); 474 475 return ret; 476 } 477 478 /* IPC stream position. */ 479 static void ipc3_period_elapsed(struct snd_sof_dev *sdev, u32 msg_id) 480 { 481 struct snd_soc_component *scomp = sdev->component; 482 struct snd_sof_pcm_stream *stream; 483 struct sof_ipc_stream_posn posn; 484 struct snd_sof_pcm *spcm; 485 int direction, ret; 486 487 spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction); 488 if (!spcm) { 489 dev_err(sdev->dev, "period elapsed for unknown stream, msg_id %d\n", 490 msg_id); 491 return; 492 } 493 494 stream = &spcm->stream[direction]; 495 ret = snd_sof_ipc_msg_data(sdev, stream->substream, &posn, sizeof(posn)); 496 if (ret < 0) { 497 dev_warn(sdev->dev, "failed to read stream position: %d\n", ret); 498 return; 499 } 500 501 dev_vdbg(sdev->dev, "posn : host 0x%llx dai 0x%llx wall 0x%llx\n", 502 posn.host_posn, posn.dai_posn, posn.wallclock); 503 504 memcpy(&stream->posn, &posn, sizeof(posn)); 505 506 if (spcm->pcm.compress) 507 snd_sof_compr_fragment_elapsed(stream->cstream); 508 else if (stream->substream->runtime && 509 !stream->substream->runtime->no_period_wakeup) 510 /* only inform ALSA for period_wakeup mode */ 511 snd_sof_pcm_period_elapsed(stream->substream); 512 } 513 514 /* DSP notifies host of an XRUN within FW */ 515 static void ipc3_xrun(struct snd_sof_dev *sdev, u32 msg_id) 516 { 517 struct snd_soc_component *scomp = sdev->component; 518 struct snd_sof_pcm_stream *stream; 519 struct sof_ipc_stream_posn posn; 520 struct snd_sof_pcm *spcm; 521 int direction, ret; 522 523 spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction); 524 if (!spcm) { 525 dev_err(sdev->dev, "XRUN for unknown stream, msg_id %d\n", 526 msg_id); 527 return; 528 } 529 530 stream = &spcm->stream[direction]; 531 ret = snd_sof_ipc_msg_data(sdev, stream->substream, &posn, sizeof(posn)); 532 if (ret < 0) { 533 dev_warn(sdev->dev, "failed to read overrun position: %d\n", ret); 534 return; 535 } 536 537 dev_dbg(sdev->dev, "posn XRUN: host %llx comp %d size %d\n", 538 posn.host_posn, posn.xrun_comp_id, posn.xrun_size); 539 540 #if defined(CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP) 541 /* stop PCM on XRUN - used for pipeline debug */ 542 memcpy(&stream->posn, &posn, sizeof(posn)); 543 snd_pcm_stop_xrun(stream->substream); 544 #endif 545 } 546 547 /* stream notifications from firmware */ 548 static void ipc3_stream_message(struct snd_sof_dev *sdev, void *msg_buf) 549 { 550 struct sof_ipc_cmd_hdr *hdr = msg_buf; 551 u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK; 552 u32 msg_id = SOF_IPC_MESSAGE_ID(hdr->cmd); 553 554 switch (msg_type) { 555 case SOF_IPC_STREAM_POSITION: 556 ipc3_period_elapsed(sdev, msg_id); 557 break; 558 case SOF_IPC_STREAM_TRIG_XRUN: 559 ipc3_xrun(sdev, msg_id); 560 break; 561 default: 562 dev_err(sdev->dev, "unhandled stream message %#x\n", 563 msg_id); 564 break; 565 } 566 } 567 568 /* component notifications from firmware */ 569 static void ipc3_comp_notification(struct snd_sof_dev *sdev, void *msg_buf) 570 { 571 const struct sof_ipc_tplg_ops *tplg_ops = sdev->ipc->ops->tplg; 572 struct sof_ipc_cmd_hdr *hdr = msg_buf; 573 u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK; 574 575 switch (msg_type) { 576 case SOF_IPC_COMP_GET_VALUE: 577 case SOF_IPC_COMP_GET_DATA: 578 break; 579 default: 580 dev_err(sdev->dev, "unhandled component message %#x\n", msg_type); 581 return; 582 } 583 584 if (tplg_ops->control->update) 585 tplg_ops->control->update(sdev, msg_buf); 586 } 587 588 static void ipc3_trace_message(struct snd_sof_dev *sdev, void *msg_buf) 589 { 590 struct sof_ipc_cmd_hdr *hdr = msg_buf; 591 u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK; 592 593 switch (msg_type) { 594 case SOF_IPC_TRACE_DMA_POSITION: 595 snd_sof_trace_update_pos(sdev, msg_buf); 596 break; 597 default: 598 dev_err(sdev->dev, "unhandled trace message %#x\n", msg_type); 599 break; 600 } 601 } 602 603 /* DSP firmware has sent host a message */ 604 static void sof_ipc3_rx_msg(struct snd_sof_dev *sdev) 605 { 606 ipc3_rx_callback rx_callback = NULL; 607 struct sof_ipc_cmd_hdr hdr; 608 void *msg_buf; 609 u32 cmd; 610 int err; 611 612 /* read back header */ 613 err = snd_sof_ipc_msg_data(sdev, NULL, &hdr, sizeof(hdr)); 614 if (err < 0) { 615 dev_warn(sdev->dev, "failed to read IPC header: %d\n", err); 616 return; 617 } 618 619 if (hdr.size < sizeof(hdr)) { 620 dev_err(sdev->dev, "The received message size is invalid\n"); 621 return; 622 } 623 624 ipc3_log_header(sdev->dev, "ipc rx", hdr.cmd); 625 626 cmd = hdr.cmd & SOF_GLB_TYPE_MASK; 627 628 /* check message type */ 629 switch (cmd) { 630 case SOF_IPC_GLB_REPLY: 631 dev_err(sdev->dev, "ipc reply unknown\n"); 632 break; 633 case SOF_IPC_FW_READY: 634 /* check for FW boot completion */ 635 if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) { 636 err = sof_ops(sdev)->fw_ready(sdev, cmd); 637 if (err < 0) 638 sof_set_fw_state(sdev, SOF_FW_BOOT_READY_FAILED); 639 else 640 sof_set_fw_state(sdev, SOF_FW_BOOT_READY_OK); 641 642 /* wake up firmware loader */ 643 wake_up(&sdev->boot_wait); 644 } 645 break; 646 case SOF_IPC_GLB_COMPOUND: 647 case SOF_IPC_GLB_TPLG_MSG: 648 case SOF_IPC_GLB_PM_MSG: 649 break; 650 case SOF_IPC_GLB_COMP_MSG: 651 rx_callback = ipc3_comp_notification; 652 break; 653 case SOF_IPC_GLB_STREAM_MSG: 654 rx_callback = ipc3_stream_message; 655 break; 656 case SOF_IPC_GLB_TRACE_MSG: 657 rx_callback = ipc3_trace_message; 658 break; 659 default: 660 dev_err(sdev->dev, "%s: Unknown DSP message: 0x%x\n", __func__, cmd); 661 break; 662 } 663 664 /* read the full message */ 665 msg_buf = kmalloc(hdr.size, GFP_KERNEL); 666 if (!msg_buf) 667 return; 668 669 err = snd_sof_ipc_msg_data(sdev, NULL, msg_buf, hdr.size); 670 if (err < 0) { 671 dev_err(sdev->dev, "%s: Failed to read message: %d\n", __func__, err); 672 } else { 673 /* Call local handler for the message */ 674 if (rx_callback) 675 rx_callback(sdev, msg_buf); 676 677 /* Notify registered clients */ 678 sof_client_ipc_rx_dispatcher(sdev, msg_buf); 679 } 680 681 kfree(msg_buf); 682 683 ipc3_log_header(sdev->dev, "ipc rx done", hdr.cmd); 684 } 685 686 static int sof_ipc3_ctx_ipc(struct snd_sof_dev *sdev, int cmd) 687 { 688 struct sof_ipc_pm_ctx pm_ctx = { 689 .hdr.size = sizeof(pm_ctx), 690 .hdr.cmd = SOF_IPC_GLB_PM_MSG | cmd, 691 }; 692 struct sof_ipc_reply reply; 693 694 /* send ctx save ipc to dsp */ 695 return sof_ipc3_tx_msg(sdev, &pm_ctx, sizeof(pm_ctx), 696 &reply, sizeof(reply), false); 697 } 698 699 static int sof_ipc3_ctx_save(struct snd_sof_dev *sdev) 700 { 701 return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_SAVE); 702 } 703 704 static int sof_ipc3_ctx_restore(struct snd_sof_dev *sdev) 705 { 706 return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_RESTORE); 707 } 708 709 static const struct sof_ipc_pm_ops ipc3_pm_ops = { 710 .ctx_save = sof_ipc3_ctx_save, 711 .ctx_restore = sof_ipc3_ctx_restore, 712 }; 713 714 const struct sof_ipc_ops ipc3_ops = { 715 .tplg = &ipc3_tplg_ops, 716 .pm = &ipc3_pm_ops, 717 .pcm = &ipc3_pcm_ops, 718 719 .tx_msg = sof_ipc3_tx_msg, 720 .rx_msg = sof_ipc3_rx_msg, 721 .set_get_data = sof_ipc3_set_get_data, 722 .get_reply = sof_ipc3_get_reply, 723 }; 724