1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018-2022 Intel Corporation. All rights reserved. 7 // 8 9 /* 10 * Hardware interface for audio DSP on Skylake and Kabylake. 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/firmware.h> 17 #include <linux/fs.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/slab.h> 21 #include <linux/pci.h> 22 #include <sound/hdaudio_ext.h> 23 #include <sound/pcm_params.h> 24 #include <sound/sof.h> 25 #include <sound/sof/ext_manifest4.h> 26 27 #include "../sof-priv.h" 28 #include "../ipc4-priv.h" 29 #include "../ops.h" 30 #include "hda.h" 31 #include "../sof-audio.h" 32 33 #define SRAM_MEMORY_WINDOW_BASE 0x8000 34 35 static const __maybe_unused struct snd_sof_debugfs_map skl_dsp_debugfs[] = { 36 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000}, 37 {"pp", HDA_DSP_PP_BAR, 0, 0x1000}, 38 {"dsp", HDA_DSP_BAR, 0, 0x10000}, 39 }; 40 41 static int skl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id) 42 { 43 return SRAM_MEMORY_WINDOW_BASE + (0x2000 * id); 44 } 45 46 static int skl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev) 47 { 48 return SRAM_MEMORY_WINDOW_BASE + 0x1000; 49 } 50 51 /* skylake ops */ 52 struct snd_sof_dsp_ops sof_skl_ops; 53 EXPORT_SYMBOL_NS(sof_skl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 54 55 int sof_skl_ops_init(struct snd_sof_dev *sdev) 56 { 57 struct sof_ipc4_fw_data *ipc4_data; 58 59 /* common defaults */ 60 memcpy(&sof_skl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 61 62 /* probe/remove/shutdown */ 63 sof_skl_ops.shutdown = hda_dsp_shutdown; 64 65 sdev->private = kzalloc(sizeof(*ipc4_data), GFP_KERNEL); 66 if (!sdev->private) 67 return -ENOMEM; 68 69 ipc4_data = sdev->private; 70 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET_CAVS_1_5; 71 72 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_5; 73 74 sof_skl_ops.get_window_offset = skl_dsp_ipc_get_window_offset; 75 sof_skl_ops.get_mailbox_offset = skl_dsp_ipc_get_mailbox_offset; 76 77 /* doorbell */ 78 sof_skl_ops.irq_thread = hda_dsp_ipc4_irq_thread; 79 80 /* ipc */ 81 sof_skl_ops.send_msg = hda_dsp_ipc4_send_msg; 82 83 /* set DAI driver ops */ 84 hda_set_dai_drv_ops(sdev, &sof_skl_ops); 85 86 /* debug */ 87 sof_skl_ops.debug_map = skl_dsp_debugfs; 88 sof_skl_ops.debug_map_count = ARRAY_SIZE(skl_dsp_debugfs); 89 sof_skl_ops.ipc_dump = hda_ipc4_dump; 90 91 /* firmware run */ 92 sof_skl_ops.run = hda_dsp_cl_boot_firmware_skl; 93 94 /* pre/post fw run */ 95 sof_skl_ops.post_fw_run = hda_dsp_post_fw_run; 96 97 return 0; 98 }; 99 EXPORT_SYMBOL_NS(sof_skl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 100 101 const struct sof_intel_dsp_desc skl_chip_info = { 102 .cores_num = 2, 103 .init_core_mask = 1, 104 .host_managed_cores_mask = GENMASK(1, 0), 105 .ipc_req = HDA_DSP_REG_HIPCI, 106 .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY, 107 .ipc_ack = HDA_DSP_REG_HIPCIE, 108 .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE, 109 .ipc_ctl = HDA_DSP_REG_HIPCCTL, 110 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS_SKL, 111 .rom_init_timeout = 300, 112 .check_ipc_irq = hda_dsp_check_ipc_irq, 113 .power_down_dsp = hda_power_down_dsp, 114 .disable_interrupts = hda_dsp_disable_interrupts, 115 .hw_ip_version = SOF_INTEL_CAVS_1_5, 116 }; 117 EXPORT_SYMBOL_NS(skl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 118