1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2017 Intel Corporation 7 * 8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 */ 10 11 #ifndef __SOF_INTEL_SHIM_H 12 #define __SOF_INTEL_SHIM_H 13 14 enum sof_intel_hw_ip_version { 15 SOF_INTEL_TANGIER, 16 SOF_INTEL_BAYTRAIL, 17 SOF_INTEL_BROADWELL, 18 SOF_INTEL_CAVS_1_5, /* SkyLake, KabyLake, AmberLake */ 19 SOF_INTEL_CAVS_1_5_PLUS,/* ApolloLake, GeminiLake */ 20 SOF_INTEL_CAVS_1_8, /* CannonLake, CometLake, CoffeeLake */ 21 SOF_INTEL_CAVS_2_0, /* IceLake, JasperLake */ 22 SOF_INTEL_CAVS_2_5, /* TigerLake, AlderLake */ 23 SOF_INTEL_ACE_1_0, /* MeteorLake */ 24 SOF_INTEL_ACE_2_0, /* LunarLake */ 25 SOF_INTEL_ACE_3_0, /* PantherLake */ 26 }; 27 28 /* 29 * SHIM registers for BYT, BSW, CHT, BDW 30 */ 31 32 #define SHIM_CSR (SHIM_OFFSET + 0x00) 33 #define SHIM_PISR (SHIM_OFFSET + 0x08) 34 #define SHIM_PIMR (SHIM_OFFSET + 0x10) 35 #define SHIM_ISRX (SHIM_OFFSET + 0x18) 36 #define SHIM_ISRD (SHIM_OFFSET + 0x20) 37 #define SHIM_IMRX (SHIM_OFFSET + 0x28) 38 #define SHIM_IMRD (SHIM_OFFSET + 0x30) 39 #define SHIM_IPCX (SHIM_OFFSET + 0x38) 40 #define SHIM_IPCD (SHIM_OFFSET + 0x40) 41 #define SHIM_ISRSC (SHIM_OFFSET + 0x48) 42 #define SHIM_ISRLPESC (SHIM_OFFSET + 0x50) 43 #define SHIM_IMRSC (SHIM_OFFSET + 0x58) 44 #define SHIM_IMRLPESC (SHIM_OFFSET + 0x60) 45 #define SHIM_IPCSC (SHIM_OFFSET + 0x68) 46 #define SHIM_IPCLPESC (SHIM_OFFSET + 0x70) 47 #define SHIM_CLKCTL (SHIM_OFFSET + 0x78) 48 #define SHIM_CSR2 (SHIM_OFFSET + 0x80) 49 #define SHIM_LTRC (SHIM_OFFSET + 0xE0) 50 #define SHIM_HMDC (SHIM_OFFSET + 0xE8) 51 52 #define SHIM_PWMCTRL 0x1000 53 54 /* 55 * SST SHIM register bits for BYT, BSW, CHT, BDW 56 * Register bit naming and functionaility can differ between devices. 57 */ 58 59 /* CSR / CS */ 60 #define SHIM_CSR_RST BIT(1) 61 #define SHIM_CSR_SBCS0 BIT(2) 62 #define SHIM_CSR_SBCS1 BIT(3) 63 #define SHIM_CSR_DCS(x) ((x) << 4) 64 #define SHIM_CSR_DCS_MASK (0x7 << 4) 65 #define SHIM_CSR_STALL BIT(10) 66 #define SHIM_CSR_S0IOCS BIT(21) 67 #define SHIM_CSR_S1IOCS BIT(23) 68 #define SHIM_CSR_LPCS BIT(31) 69 #define SHIM_CSR_24MHZ_LPCS \ 70 (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS) 71 #define SHIM_CSR_24MHZ_NO_LPCS (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1) 72 #define SHIM_BYT_CSR_RST BIT(0) 73 #define SHIM_BYT_CSR_VECTOR_SEL BIT(1) 74 #define SHIM_BYT_CSR_STALL BIT(2) 75 #define SHIM_BYT_CSR_PWAITMODE BIT(3) 76 77 /* ISRX / ISC */ 78 #define SHIM_ISRX_BUSY BIT(1) 79 #define SHIM_ISRX_DONE BIT(0) 80 #define SHIM_BYT_ISRX_REQUEST BIT(1) 81 82 /* ISRD / ISD */ 83 #define SHIM_ISRD_BUSY BIT(1) 84 #define SHIM_ISRD_DONE BIT(0) 85 86 /* IMRX / IMC */ 87 #define SHIM_IMRX_BUSY BIT(1) 88 #define SHIM_IMRX_DONE BIT(0) 89 #define SHIM_BYT_IMRX_REQUEST BIT(1) 90 91 /* IMRD / IMD */ 92 #define SHIM_IMRD_DONE BIT(0) 93 #define SHIM_IMRD_BUSY BIT(1) 94 #define SHIM_IMRD_SSP0 BIT(16) 95 #define SHIM_IMRD_DMAC0 BIT(21) 96 #define SHIM_IMRD_DMAC1 BIT(22) 97 #define SHIM_IMRD_DMAC (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1) 98 99 /* IPCX / IPCC */ 100 #define SHIM_IPCX_DONE BIT(30) 101 #define SHIM_IPCX_BUSY BIT(31) 102 #define SHIM_BYT_IPCX_DONE BIT_ULL(62) 103 #define SHIM_BYT_IPCX_BUSY BIT_ULL(63) 104 105 /* IPCD */ 106 #define SHIM_IPCD_DONE BIT(30) 107 #define SHIM_IPCD_BUSY BIT(31) 108 #define SHIM_BYT_IPCD_DONE BIT_ULL(62) 109 #define SHIM_BYT_IPCD_BUSY BIT_ULL(63) 110 111 /* CLKCTL */ 112 #define SHIM_CLKCTL_SMOS(x) ((x) << 24) 113 #define SHIM_CLKCTL_MASK (3 << 24) 114 #define SHIM_CLKCTL_DCPLCG BIT(18) 115 #define SHIM_CLKCTL_SCOE1 BIT(17) 116 #define SHIM_CLKCTL_SCOE0 BIT(16) 117 118 /* CSR2 / CS2 */ 119 #define SHIM_CSR2_SDFD_SSP0 BIT(1) 120 #define SHIM_CSR2_SDFD_SSP1 BIT(2) 121 122 /* LTRC */ 123 #define SHIM_LTRC_VAL(x) ((x) << 0) 124 125 /* HMDC */ 126 #define SHIM_HMDC_HDDA0(x) ((x) << 0) 127 #define SHIM_HMDC_HDDA1(x) ((x) << 7) 128 #define SHIM_HMDC_HDDA_E0_CH0 1 129 #define SHIM_HMDC_HDDA_E0_CH1 2 130 #define SHIM_HMDC_HDDA_E0_CH2 4 131 #define SHIM_HMDC_HDDA_E0_CH3 8 132 #define SHIM_HMDC_HDDA_E1_CH0 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0) 133 #define SHIM_HMDC_HDDA_E1_CH1 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1) 134 #define SHIM_HMDC_HDDA_E1_CH2 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2) 135 #define SHIM_HMDC_HDDA_E1_CH3 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3) 136 #define SHIM_HMDC_HDDA_E0_ALLCH \ 137 (SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \ 138 SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3) 139 #define SHIM_HMDC_HDDA_E1_ALLCH \ 140 (SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \ 141 SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3) 142 143 /* Audio DSP PCI registers */ 144 #define PCI_VDRTCTL0 0xa0 145 #define PCI_VDRTCTL1 0xa4 146 #define PCI_VDRTCTL2 0xa8 147 #define PCI_VDRTCTL3 0xaC 148 149 /* VDRTCTL0 */ 150 #define PCI_VDRTCL0_D3PGD BIT(0) 151 #define PCI_VDRTCL0_D3SRAMPGD BIT(1) 152 #define PCI_VDRTCL0_DSRAMPGE_SHIFT 12 153 #define PCI_VDRTCL0_DSRAMPGE_MASK GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\ 154 PCI_VDRTCL0_DSRAMPGE_SHIFT) 155 #define PCI_VDRTCL0_ISRAMPGE_SHIFT 2 156 #define PCI_VDRTCL0_ISRAMPGE_MASK GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\ 157 PCI_VDRTCL0_ISRAMPGE_SHIFT) 158 159 /* VDRTCTL2 */ 160 #define PCI_VDRTCL2_DCLCGE BIT(1) 161 #define PCI_VDRTCL2_DTCGE BIT(10) 162 #define PCI_VDRTCL2_APLLSE_MASK BIT(31) 163 164 /* PMCS */ 165 #define PCI_PMCS 0x84 166 #define PCI_PMCS_PS_MASK 0x3 167 168 /* Intel quirks */ 169 #define SOF_INTEL_PROCEN_FMT_QUIRK BIT(0) 170 171 /* DSP hardware descriptor */ 172 struct sof_intel_dsp_desc { 173 int cores_num; 174 int host_managed_cores_mask; 175 int init_core_mask; /* cores available after fw boot */ 176 int ipc_req; 177 int ipc_req_mask; 178 int ipc_ack; 179 int ipc_ack_mask; 180 int ipc_ctl; 181 int rom_status_reg; 182 int rom_init_timeout; 183 int ssp_count; /* ssp count of the platform */ 184 int ssp_base_offset; /* base address of the SSPs */ 185 u32 sdw_shim_base; 186 u32 sdw_alh_base; 187 u32 d0i3_offset; 188 u32 quirks; 189 enum sof_intel_hw_ip_version hw_ip_version; 190 int (*read_sdw_lcount)(struct snd_sof_dev *sdev); 191 void (*enable_sdw_irq)(struct snd_sof_dev *sdev, bool enable); 192 bool (*check_sdw_irq)(struct snd_sof_dev *sdev); 193 bool (*check_sdw_wakeen_irq)(struct snd_sof_dev *sdev); 194 void (*sdw_process_wakeen)(struct snd_sof_dev *sdev); 195 bool (*check_ipc_irq)(struct snd_sof_dev *sdev); 196 int (*power_down_dsp)(struct snd_sof_dev *sdev); 197 int (*disable_interrupts)(struct snd_sof_dev *sdev); 198 int (*cl_init)(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); 199 }; 200 201 extern const struct snd_sof_dsp_ops sof_tng_ops; 202 203 extern const struct sof_intel_dsp_desc tng_chip_info; 204 205 struct sof_intel_stream { 206 size_t posn_offset; 207 }; 208 209 static inline const struct sof_intel_dsp_desc *get_chip_info(struct snd_sof_pdata *pdata) 210 { 211 const struct sof_dev_desc *desc = pdata->desc; 212 213 return desc->chip_info; 214 } 215 216 #endif 217