xref: /linux/sound/soc/sof/intel/shim.h (revision 24bce201d79807b668bf9d9e0aca801c5c0d5f78) 
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * Copyright(c) 2017 Intel Corporation. All rights reserved.
7  *
8  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9  */
10 
11 #ifndef __SOF_INTEL_SHIM_H
12 #define __SOF_INTEL_SHIM_H
13 
14 enum sof_intel_hw_ip_version {
15 	SOF_INTEL_TANGIER,
16 	SOF_INTEL_BAYTRAIL,
17 	SOF_INTEL_BROADWELL,
18 	SOF_INTEL_CAVS_1_5,	/* SkyLake, KabyLake, AmberLake */
19 	SOF_INTEL_CAVS_1_5_PLUS,/* ApolloLake, GeminiLake */
20 	SOF_INTEL_CAVS_1_8,	/* CannonLake, CometLake, CoffeeLake */
21 	SOF_INTEL_CAVS_2_0,	/* IceLake, JasperLake */
22 	SOF_INTEL_CAVS_2_5,	/* TigerLake, AlderLake */
23 };
24 
25 /*
26  * SHIM registers for BYT, BSW, CHT, BDW
27  */
28 
29 #define SHIM_CSR		(SHIM_OFFSET + 0x00)
30 #define SHIM_PISR		(SHIM_OFFSET + 0x08)
31 #define SHIM_PIMR		(SHIM_OFFSET + 0x10)
32 #define SHIM_ISRX		(SHIM_OFFSET + 0x18)
33 #define SHIM_ISRD		(SHIM_OFFSET + 0x20)
34 #define SHIM_IMRX		(SHIM_OFFSET + 0x28)
35 #define SHIM_IMRD		(SHIM_OFFSET + 0x30)
36 #define SHIM_IPCX		(SHIM_OFFSET + 0x38)
37 #define SHIM_IPCD		(SHIM_OFFSET + 0x40)
38 #define SHIM_ISRSC		(SHIM_OFFSET + 0x48)
39 #define SHIM_ISRLPESC		(SHIM_OFFSET + 0x50)
40 #define SHIM_IMRSC		(SHIM_OFFSET + 0x58)
41 #define SHIM_IMRLPESC		(SHIM_OFFSET + 0x60)
42 #define SHIM_IPCSC		(SHIM_OFFSET + 0x68)
43 #define SHIM_IPCLPESC		(SHIM_OFFSET + 0x70)
44 #define SHIM_CLKCTL		(SHIM_OFFSET + 0x78)
45 #define SHIM_CSR2		(SHIM_OFFSET + 0x80)
46 #define SHIM_LTRC		(SHIM_OFFSET + 0xE0)
47 #define SHIM_HMDC		(SHIM_OFFSET + 0xE8)
48 
49 #define SHIM_PWMCTRL		0x1000
50 
51 /*
52  * SST SHIM register bits for BYT, BSW, CHT, BDW
53  * Register bit naming and functionaility can differ between devices.
54  */
55 
56 /* CSR / CS */
57 #define SHIM_CSR_RST		BIT(1)
58 #define SHIM_CSR_SBCS0		BIT(2)
59 #define SHIM_CSR_SBCS1		BIT(3)
60 #define SHIM_CSR_DCS(x)		((x) << 4)
61 #define SHIM_CSR_DCS_MASK	(0x7 << 4)
62 #define SHIM_CSR_STALL		BIT(10)
63 #define SHIM_CSR_S0IOCS		BIT(21)
64 #define SHIM_CSR_S1IOCS		BIT(23)
65 #define SHIM_CSR_LPCS		BIT(31)
66 #define SHIM_CSR_24MHZ_LPCS \
67 	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
68 #define SHIM_CSR_24MHZ_NO_LPCS	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
69 #define SHIM_BYT_CSR_RST	BIT(0)
70 #define SHIM_BYT_CSR_VECTOR_SEL	BIT(1)
71 #define SHIM_BYT_CSR_STALL	BIT(2)
72 #define SHIM_BYT_CSR_PWAITMODE	BIT(3)
73 
74 /*  ISRX / ISC */
75 #define SHIM_ISRX_BUSY		BIT(1)
76 #define SHIM_ISRX_DONE		BIT(0)
77 #define SHIM_BYT_ISRX_REQUEST	BIT(1)
78 
79 /*  ISRD / ISD */
80 #define SHIM_ISRD_BUSY		BIT(1)
81 #define SHIM_ISRD_DONE		BIT(0)
82 
83 /* IMRX / IMC */
84 #define SHIM_IMRX_BUSY		BIT(1)
85 #define SHIM_IMRX_DONE		BIT(0)
86 #define SHIM_BYT_IMRX_REQUEST	BIT(1)
87 
88 /* IMRD / IMD */
89 #define SHIM_IMRD_DONE		BIT(0)
90 #define SHIM_IMRD_BUSY		BIT(1)
91 #define SHIM_IMRD_SSP0		BIT(16)
92 #define SHIM_IMRD_DMAC0		BIT(21)
93 #define SHIM_IMRD_DMAC1		BIT(22)
94 #define SHIM_IMRD_DMAC		(SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
95 
96 /*  IPCX / IPCC */
97 #define	SHIM_IPCX_DONE		BIT(30)
98 #define	SHIM_IPCX_BUSY		BIT(31)
99 #define SHIM_BYT_IPCX_DONE	BIT_ULL(62)
100 #define SHIM_BYT_IPCX_BUSY	BIT_ULL(63)
101 
102 /*  IPCD */
103 #define	SHIM_IPCD_DONE		BIT(30)
104 #define	SHIM_IPCD_BUSY		BIT(31)
105 #define SHIM_BYT_IPCD_DONE	BIT_ULL(62)
106 #define SHIM_BYT_IPCD_BUSY	BIT_ULL(63)
107 
108 /* CLKCTL */
109 #define SHIM_CLKCTL_SMOS(x)	((x) << 24)
110 #define SHIM_CLKCTL_MASK	(3 << 24)
111 #define SHIM_CLKCTL_DCPLCG	BIT(18)
112 #define SHIM_CLKCTL_SCOE1	BIT(17)
113 #define SHIM_CLKCTL_SCOE0	BIT(16)
114 
115 /* CSR2 / CS2 */
116 #define SHIM_CSR2_SDFD_SSP0	BIT(1)
117 #define SHIM_CSR2_SDFD_SSP1	BIT(2)
118 
119 /* LTRC */
120 #define SHIM_LTRC_VAL(x)	((x) << 0)
121 
122 /* HMDC */
123 #define SHIM_HMDC_HDDA0(x)	((x) << 0)
124 #define SHIM_HMDC_HDDA1(x)	((x) << 7)
125 #define SHIM_HMDC_HDDA_E0_CH0	1
126 #define SHIM_HMDC_HDDA_E0_CH1	2
127 #define SHIM_HMDC_HDDA_E0_CH2	4
128 #define SHIM_HMDC_HDDA_E0_CH3	8
129 #define SHIM_HMDC_HDDA_E1_CH0	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0)
130 #define SHIM_HMDC_HDDA_E1_CH1	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1)
131 #define SHIM_HMDC_HDDA_E1_CH2	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2)
132 #define SHIM_HMDC_HDDA_E1_CH3	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3)
133 #define SHIM_HMDC_HDDA_E0_ALLCH	\
134 	(SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \
135 	 SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3)
136 #define SHIM_HMDC_HDDA_E1_ALLCH	\
137 	(SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \
138 	 SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3)
139 
140 /* Audio DSP PCI registers */
141 #define PCI_VDRTCTL0		0xa0
142 #define PCI_VDRTCTL1		0xa4
143 #define PCI_VDRTCTL2		0xa8
144 #define PCI_VDRTCTL3		0xaC
145 
146 /* VDRTCTL0 */
147 #define PCI_VDRTCL0_D3PGD		BIT(0)
148 #define PCI_VDRTCL0_D3SRAMPGD		BIT(1)
149 #define PCI_VDRTCL0_DSRAMPGE_SHIFT	12
150 #define PCI_VDRTCL0_DSRAMPGE_MASK	GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
151 						PCI_VDRTCL0_DSRAMPGE_SHIFT)
152 #define PCI_VDRTCL0_ISRAMPGE_SHIFT	2
153 #define PCI_VDRTCL0_ISRAMPGE_MASK	GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
154 						PCI_VDRTCL0_ISRAMPGE_SHIFT)
155 
156 /* VDRTCTL2 */
157 #define PCI_VDRTCL2_DCLCGE		BIT(1)
158 #define PCI_VDRTCL2_DTCGE		BIT(10)
159 #define PCI_VDRTCL2_APLLSE_MASK		BIT(31)
160 
161 /* PMCS */
162 #define PCI_PMCS		0x84
163 #define PCI_PMCS_PS_MASK	0x3
164 
165 /* Intel quirks */
166 #define SOF_INTEL_PROCEN_FMT_QUIRK BIT(0)
167 
168 /* DSP hardware descriptor */
169 struct sof_intel_dsp_desc {
170 	int cores_num;
171 	int host_managed_cores_mask;
172 	int init_core_mask; /* cores available after fw boot */
173 	int ipc_req;
174 	int ipc_req_mask;
175 	int ipc_ack;
176 	int ipc_ack_mask;
177 	int ipc_ctl;
178 	int rom_status_reg;
179 	int rom_init_timeout;
180 	int ssp_count;			/* ssp count of the platform */
181 	int ssp_base_offset;		/* base address of the SSPs */
182 	u32 sdw_shim_base;
183 	u32 sdw_alh_base;
184 	u32 quirks;
185 	enum sof_intel_hw_ip_version hw_ip_version;
186 	bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
187 	bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
188 };
189 
190 extern struct snd_sof_dsp_ops sof_tng_ops;
191 
192 extern const struct sof_intel_dsp_desc tng_chip_info;
193 
194 struct sof_intel_stream {
195 	size_t posn_offset;
196 };
197 
198 static inline const struct sof_intel_dsp_desc *get_chip_info(struct snd_sof_pdata *pdata)
199 {
200 	const struct sof_dev_desc *desc = pdata->desc;
201 
202 	return desc->chip_info;
203 }
204 
205 #endif
206