18aeb7d2cSPeter Ujfalusi /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 28aeb7d2cSPeter Ujfalusi /* 38aeb7d2cSPeter Ujfalusi * This file is provided under a dual BSD/GPLv2 license. When using or 48aeb7d2cSPeter Ujfalusi * redistributing this file, you may do so under either license. 58aeb7d2cSPeter Ujfalusi * 68aeb7d2cSPeter Ujfalusi * Copyright(c) 2025 Intel Corporation 78aeb7d2cSPeter Ujfalusi */ 88aeb7d2cSPeter Ujfalusi 98aeb7d2cSPeter Ujfalusi #ifndef __SOF_INTEL_PTL_H 108aeb7d2cSPeter Ujfalusi #define __SOF_INTEL_PTL_H 118aeb7d2cSPeter Ujfalusi 12*4a43c324SPeter Ujfalusi #define PTL_MICPVCP_DDZE_FORCED BIT(16) 13*4a43c324SPeter Ujfalusi #define PTL_MICPVCP_DDZE_ENABLED BIT(17) 14*4a43c324SPeter Ujfalusi #define PTL_MICPVCP_DDZLS_SDW GENMASK(26, 20) 15*4a43c324SPeter Ujfalusi #define PTL_MICPVCP_GET_SDW_MASK(x) (((x) & PTL_MICPVCP_DDZLS_SDW) >> 20) 16*4a43c324SPeter Ujfalusi 178aeb7d2cSPeter Ujfalusi int sof_ptl_set_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *dsp_ops); 188aeb7d2cSPeter Ujfalusi 198aeb7d2cSPeter Ujfalusi #endif /* __SOF_INTEL_PTL_H */ 20