1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2025 Intel Corporation 4 5 /* 6 * Hardware interface for audio DSP on PantherLake. 7 */ 8 9 #include <sound/hda_register.h> 10 #include <sound/hda-mlink.h> 11 #include <sound/sof/ipc4/header.h> 12 #include "../ipc4-priv.h" 13 #include "../ops.h" 14 #include "hda.h" 15 #include "hda-ipc.h" 16 #include "../sof-audio.h" 17 #include "mtl.h" 18 #include "lnl.h" 19 #include "ptl.h" 20 21 static bool sof_ptl_check_mic_privacy_irq(struct snd_sof_dev *sdev, bool alt, 22 int elid) 23 { 24 if (!alt || elid != AZX_REG_ML_LEPTR_ID_SDW) 25 return false; 26 27 return hdac_bus_eml_is_mic_privacy_changed(sof_to_bus(sdev), alt, elid); 28 } 29 30 static void sof_ptl_process_mic_privacy(struct snd_sof_dev *sdev, bool alt, 31 int elid) 32 { 33 bool state; 34 35 if (!alt || elid != AZX_REG_ML_LEPTR_ID_SDW) 36 return; 37 38 state = hdac_bus_eml_get_mic_privacy_state(sof_to_bus(sdev), alt, elid); 39 40 sof_ipc4_mic_privacy_state_change(sdev, state); 41 } 42 43 static void sof_ptl_set_mic_privacy(struct snd_sof_dev *sdev, 44 struct sof_ipc4_intel_mic_privacy_cap *caps) 45 { 46 u32 micpvcp; 47 48 if (!caps || !caps->capabilities_length) 49 return; 50 51 micpvcp = caps->capabilities[0]; 52 53 /* No need to set the mic privacy if it is not enabled or forced */ 54 if (!(micpvcp & PTL_MICPVCP_DDZE_ENABLED) || 55 micpvcp & PTL_MICPVCP_DDZE_FORCED) 56 return; 57 58 hdac_bus_eml_set_mic_privacy_mask(sof_to_bus(sdev), true, 59 AZX_REG_ML_LEPTR_ID_SDW, 60 PTL_MICPVCP_GET_SDW_MASK(micpvcp)); 61 } 62 63 int sof_ptl_set_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *dsp_ops) 64 { 65 struct sof_ipc4_fw_data *ipc4_data; 66 int ret; 67 68 ret = sof_lnl_set_ops(sdev, dsp_ops); 69 if (ret) 70 return ret; 71 72 ipc4_data = sdev->private; 73 ipc4_data->intel_configure_mic_privacy = sof_ptl_set_mic_privacy; 74 75 return 0; 76 }; 77 EXPORT_SYMBOL_NS(sof_ptl_set_ops, "SND_SOC_SOF_INTEL_PTL"); 78 79 const struct sof_intel_dsp_desc ptl_chip_info = { 80 .cores_num = 5, 81 .init_core_mask = BIT(0), 82 .host_managed_cores_mask = BIT(0), 83 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 84 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 85 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 86 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 87 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 88 .rom_status_reg = LNL_DSP_REG_HFDSC, 89 .rom_init_timeout = 300, 90 .ssp_count = MTL_SSP_COUNT, 91 .d0i3_offset = MTL_HDA_VS_D0I3C, 92 .read_sdw_lcount = hda_sdw_check_lcount_ext, 93 .check_sdw_irq = lnl_dsp_check_sdw_irq, 94 .check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq, 95 .check_ipc_irq = mtl_dsp_check_ipc_irq, 96 .check_mic_privacy_irq = sof_ptl_check_mic_privacy_irq, 97 .process_mic_privacy = sof_ptl_process_mic_privacy, 98 .cl_init = mtl_dsp_cl_init, 99 .power_down_dsp = mtl_power_down_dsp, 100 .disable_interrupts = lnl_dsp_disable_interrupts, 101 .hw_ip_version = SOF_INTEL_ACE_3_0, 102 }; 103 104 MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_MTL"); 105 MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_LNL"); 106 MODULE_IMPORT_NS("SND_SOC_SOF_HDA_MLINK"); 107