1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2022 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Meteorlake. 10 */ 11 12 #include <linux/debugfs.h> 13 #include <linux/firmware.h> 14 #include <sound/sof/ipc4/header.h> 15 #include <trace/events/sof_intel.h> 16 #include "../ipc4-priv.h" 17 #include "../ops.h" 18 #include "hda.h" 19 #include "hda-ipc.h" 20 #include "../sof-audio.h" 21 #include "mtl.h" 22 #include "telemetry.h" 23 24 static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = { 25 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 26 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 27 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 28 {"fw_regs", HDA_DSP_BAR, MTL_SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY}, 29 }; 30 31 static void mtl_ipc_host_done(struct snd_sof_dev *sdev) 32 { 33 /* 34 * clear busy interrupt to tell dsp controller this interrupt has been accepted, 35 * not trigger it again 36 */ 37 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR, 38 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY); 39 /* 40 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp 41 */ 42 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA, 43 MTL_DSP_REG_HFIPCXTDA_BUSY, 0); 44 } 45 46 static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev) 47 { 48 /* 49 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it, 50 * don't send more reply to host 51 */ 52 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA, 53 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE); 54 55 /* unmask Done interrupt */ 56 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 57 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE); 58 } 59 60 /* Check if an IPC IRQ occurred */ 61 bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev) 62 { 63 u32 irq_status; 64 u32 hfintipptr; 65 66 if (sdev->dspless_mode_selected) 67 return false; 68 69 /* read Interrupt IP Pointer */ 70 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 71 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 72 73 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status); 74 75 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC)) 76 return true; 77 78 return false; 79 } 80 81 /* Check if an SDW IRQ occurred */ 82 static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 83 { 84 u32 irq_status; 85 u32 hfintipptr; 86 87 /* read Interrupt IP Pointer */ 88 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 89 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 90 91 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW)) 92 return true; 93 94 return false; 95 } 96 97 int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 98 { 99 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 100 struct sof_ipc4_msg *msg_data = msg->msg_data; 101 102 if (hda_ipc4_tx_is_busy(sdev)) { 103 hdev->delayed_ipc_tx_msg = msg; 104 return 0; 105 } 106 107 hdev->delayed_ipc_tx_msg = NULL; 108 109 /* send the message via mailbox */ 110 if (msg_data->data_size) 111 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr, 112 msg_data->data_size); 113 114 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY, 115 msg_data->extension); 116 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR, 117 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY); 118 119 hda_dsp_ipc4_schedule_d0i3_work(hdev, msg); 120 121 return 0; 122 } 123 124 void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev) 125 { 126 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 127 const struct sof_intel_dsp_desc *chip = hda->desc; 128 129 if (sdev->dspless_mode_selected) 130 return; 131 132 /* enable IPC DONE and BUSY interrupts */ 133 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 134 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 135 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE); 136 } 137 138 void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev) 139 { 140 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 141 const struct sof_intel_dsp_desc *chip = hda->desc; 142 143 if (sdev->dspless_mode_selected) 144 return; 145 146 /* disable IPC DONE and BUSY interrupts */ 147 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 148 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0); 149 } 150 151 static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 152 { 153 u32 hipcie; 154 u32 mask; 155 u32 val; 156 int ret; 157 158 if (sdev->dspless_mode_selected) 159 return; 160 161 /* Enable/Disable SoundWire interrupt */ 162 mask = MTL_DSP_REG_HfSNDWIE_IE_MASK; 163 if (enable) 164 val = mask; 165 else 166 val = 0; 167 168 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, mask, val); 169 170 /* check if operation was successful */ 171 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie, 172 (hipcie & mask) == val, 173 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 174 if (ret < 0) 175 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt %s\n", 176 enable ? "enable" : "disable"); 177 } 178 179 int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable) 180 { 181 u32 hfintipptr; 182 u32 irqinten; 183 u32 hipcie; 184 u32 mask; 185 u32 val; 186 int ret; 187 188 if (sdev->dspless_mode_selected) 189 return 0; 190 191 /* read Interrupt IP Pointer */ 192 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 193 194 /* Enable/Disable Host IPC and SOUNDWIRE */ 195 mask = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK; 196 if (enable) 197 val = mask; 198 else 199 val = 0; 200 201 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, mask, val); 202 203 /* check if operation was successful */ 204 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten, 205 (irqinten & mask) == val, 206 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 207 if (ret < 0) { 208 dev_err(sdev->dev, "failed to %s Host IPC and/or SOUNDWIRE\n", 209 enable ? "enable" : "disable"); 210 return ret; 211 } 212 213 /* Enable/Disable Host IPC interrupt*/ 214 mask = MTL_DSP_REG_HfHIPCIE_IE_MASK; 215 if (enable) 216 val = mask; 217 else 218 val = 0; 219 220 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, mask, val); 221 222 /* check if operation was successful */ 223 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie, 224 (hipcie & mask) == val, 225 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 226 if (ret < 0) { 227 dev_err(sdev->dev, "failed to set Host IPC interrupt %s\n", 228 enable ? "enable" : "disable"); 229 return ret; 230 } 231 232 return ret; 233 } 234 235 /* pre fw run operations */ 236 int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) 237 { 238 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 239 u32 dsphfpwrsts; 240 u32 dsphfdsscs; 241 u32 cpa; 242 u32 pgs; 243 int ret; 244 245 /* Set the DSP subsystem power on */ 246 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 247 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK); 248 249 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 250 usleep_range(1000, 1010); 251 252 /* poll with timeout to check if operation successful */ 253 cpa = MTL_HFDSSCS_CPA_MASK; 254 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 255 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 256 HDA_DSP_RESET_TIMEOUT_US); 257 if (ret < 0) { 258 dev_err(sdev->dev, "failed to enable DSP subsystem\n"); 259 return ret; 260 } 261 262 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */ 263 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, 264 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG); 265 266 usleep_range(1000, 1010); 267 268 /* poll with timeout to check if operation successful */ 269 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK; 270 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts, 271 (dsphfpwrsts & pgs) == pgs, 272 HDA_DSP_REG_POLL_INTERVAL_US, 273 HDA_DSP_RESET_TIMEOUT_US); 274 if (ret < 0) 275 dev_err(sdev->dev, "failed to power up gated DSP domain\n"); 276 277 /* if SoundWire is used, make sure it is not power-gated */ 278 if (hdev->info.handle && hdev->info.link_mask > 0) 279 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, 280 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1)); 281 282 return ret; 283 } 284 285 int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev) 286 { 287 int ret; 288 289 if (sdev->first_boot) { 290 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 291 292 ret = hda_sdw_startup(sdev); 293 if (ret < 0) { 294 dev_err(sdev->dev, "could not startup SoundWire links\n"); 295 return ret; 296 } 297 298 /* Check if IMR boot is usable */ 299 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) { 300 hdev->imrboot_supported = true; 301 debugfs_create_bool("skip_imr_boot", 302 0644, sdev->debugfs_root, 303 &hdev->skip_imr_boot); 304 } 305 } 306 307 hda_sdw_int_enable(sdev, true); 308 return 0; 309 } 310 311 void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 312 { 313 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 314 u32 fwsts; 315 u32 fwlec; 316 317 hda_dsp_get_state(sdev, level); 318 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS); 319 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR); 320 321 if (fwsts != 0xffffffff) 322 dev_err(sdev->dev, "Firmware state: %#x, status/error code: %#x\n", 323 fwsts, fwlec); 324 325 sof_ipc4_intel_dump_telemetry_state(sdev, flags); 326 } 327 328 static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev) 329 { 330 int val; 331 332 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE); 333 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK) 334 return true; 335 336 return false; 337 } 338 339 static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core) 340 { 341 unsigned int cpa; 342 u32 dspcxctl; 343 int ret; 344 345 /* Only the primary core can be powered up by the host */ 346 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev)) 347 return 0; 348 349 /* Program the owner of the IP & shim registers (10: Host CPU) */ 350 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 351 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL, 352 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT); 353 354 /* enable SPA bit */ 355 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 356 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 357 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK); 358 359 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 360 usleep_range(1000, 1010); 361 362 /* poll with timeout to check if operation successful */ 363 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK; 364 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 365 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 366 HDA_DSP_RESET_TIMEOUT_US); 367 if (ret < 0) { 368 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n", 369 __func__); 370 return ret; 371 } 372 373 /* set primary core mask and refcount to 1 */ 374 sdev->enabled_cores_mask = BIT(SOF_DSP_PRIMARY_CORE); 375 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 1; 376 377 return 0; 378 } 379 380 static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core) 381 { 382 u32 dspcxctl; 383 int ret; 384 385 /* Only the primary core can be powered down by the host */ 386 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev)) 387 return 0; 388 389 /* disable SPA bit */ 390 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 391 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0); 392 393 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */ 394 usleep_range(1000, 1010); 395 396 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 397 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK), 398 HDA_DSP_REG_POLL_INTERVAL_US, 399 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 400 if (ret < 0) { 401 dev_err(sdev->dev, "failed to power down primary core\n"); 402 return ret; 403 } 404 405 sdev->enabled_cores_mask = 0; 406 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 0; 407 408 return 0; 409 } 410 411 int mtl_power_down_dsp(struct snd_sof_dev *sdev) 412 { 413 u32 dsphfdsscs, cpa; 414 int ret; 415 416 /* first power down core */ 417 ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 418 if (ret) { 419 dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret); 420 return ret; 421 } 422 423 /* Set the DSP subsystem power down */ 424 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 425 MTL_HFDSSCS_SPA_MASK, 0); 426 427 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */ 428 usleep_range(1000, 1010); 429 430 /* poll with timeout to check if operation successful */ 431 cpa = MTL_HFDSSCS_CPA_MASK; 432 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS); 433 return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 434 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US, 435 HDA_DSP_RESET_TIMEOUT_US); 436 } 437 438 int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) 439 { 440 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 441 const struct sof_intel_dsp_desc *chip = hda->desc; 442 unsigned int status, target_status; 443 u32 ipc_hdr, flags; 444 char *dump_msg; 445 int ret; 446 447 /* step 1: purge FW request */ 448 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL; 449 if (!imr_boot) 450 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9); 451 452 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr); 453 454 /* step 2: power up primary core */ 455 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE); 456 if (ret < 0) { 457 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 458 dev_err(sdev->dev, "dsp core 0/1 power up failed\n"); 459 goto err; 460 } 461 462 dev_dbg(sdev->dev, "Primary core power up successful\n"); 463 464 /* step 3: wait for IPC DONE bit from ROM */ 465 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status, 466 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask), 467 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_INIT_TIMEOUT_US); 468 if (ret < 0) { 469 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 470 dev_err(sdev->dev, "timeout waiting for purge IPC done\n"); 471 goto err; 472 } 473 474 /* set DONE bit to clear the reply IPC message */ 475 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask, 476 chip->ipc_ack_mask); 477 478 /* step 4: enable interrupts */ 479 ret = mtl_enable_interrupts(sdev, true); 480 if (ret < 0) { 481 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 482 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__); 483 goto err; 484 } 485 486 mtl_enable_ipc_interrupts(sdev); 487 488 if (chip->rom_status_reg == MTL_DSP_ROM_STS) { 489 /* 490 * Workaround: when the ROM status register is pointing to 491 * the SRAM window (MTL_DSP_ROM_STS) the platform cannot catch 492 * ROM_INIT_DONE because of a very short timing window. 493 * Follow the recommendations and skip target state waiting. 494 */ 495 return 0; 496 } 497 498 /* 499 * step 7: 500 * - Cold/Full boot: wait for ROM init to proceed to download the firmware 501 * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR) 502 */ 503 if (imr_boot) 504 target_status = FSR_STATE_FW_ENTERED; 505 else 506 target_status = FSR_STATE_INIT_DONE; 507 508 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 509 chip->rom_status_reg, status, 510 (FSR_TO_STATE_CODE(status) == target_status), 511 HDA_DSP_REG_POLL_INTERVAL_US, 512 chip->rom_init_timeout * 513 USEC_PER_MSEC); 514 515 if (!ret) 516 return 0; 517 518 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 519 dev_err(sdev->dev, 520 "%s: timeout with rom_status_reg (%#x) read\n", 521 __func__, chip->rom_status_reg); 522 523 err: 524 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL; 525 526 /* after max boot attempts make sure that the dump is printed */ 527 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 528 flags &= ~SOF_DBG_DUMP_OPTIONAL; 529 530 dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d", 531 hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS); 532 snd_sof_dsp_dbg_dump(sdev, dump_msg, flags); 533 mtl_enable_interrupts(sdev, false); 534 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 535 536 kfree(dump_msg); 537 return ret; 538 } 539 540 irqreturn_t mtl_ipc_irq_thread(int irq, void *context) 541 { 542 struct sof_ipc4_msg notification_data = {{ 0 }}; 543 struct snd_sof_dev *sdev = context; 544 bool ack_received = false; 545 bool ipc_irq = false; 546 u32 hipcida; 547 u32 hipctdr; 548 549 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 550 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 551 552 /* reply message from DSP */ 553 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) { 554 /* DSP received the message */ 555 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 556 MTL_DSP_REG_HFIPCXCTL_DONE, 0); 557 558 mtl_ipc_dsp_done(sdev); 559 560 ipc_irq = true; 561 ack_received = true; 562 } 563 564 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) { 565 /* Message from DSP (reply or notification) */ 566 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 567 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK; 568 569 /* 570 * ACE fw sends a new fw ipc message to host to 571 * notify the status of the last host ipc message 572 */ 573 if (primary & SOF_IPC4_MSG_DIR_MASK) { 574 /* Reply received */ 575 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { 576 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data; 577 578 data->primary = primary; 579 data->extension = extension; 580 581 spin_lock_irq(&sdev->ipc_lock); 582 583 snd_sof_ipc_get_reply(sdev); 584 mtl_ipc_host_done(sdev); 585 snd_sof_ipc_reply(sdev, data->primary); 586 587 spin_unlock_irq(&sdev->ipc_lock); 588 } else { 589 dev_dbg_ratelimited(sdev->dev, 590 "IPC reply before FW_READY: %#x|%#x\n", 591 primary, extension); 592 } 593 } else { 594 /* Notification received */ 595 notification_data.primary = primary; 596 notification_data.extension = extension; 597 598 sdev->ipc->msg.rx_data = ¬ification_data; 599 snd_sof_ipc_msgs_rx(sdev); 600 sdev->ipc->msg.rx_data = NULL; 601 602 mtl_ipc_host_done(sdev); 603 } 604 605 ipc_irq = true; 606 } 607 608 if (!ipc_irq) { 609 /* This interrupt is not shared so no need to return IRQ_NONE. */ 610 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); 611 } 612 613 if (ack_received) { 614 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 615 616 if (hdev->delayed_ipc_tx_msg) 617 mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg); 618 } 619 620 return IRQ_HANDLED; 621 } 622 623 int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev) 624 { 625 return MTL_DSP_MBOX_UPLINK_OFFSET; 626 } 627 628 int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id) 629 { 630 return MTL_SRAM_WINDOW_OFFSET(id); 631 } 632 633 void mtl_ipc_dump(struct snd_sof_dev *sdev) 634 { 635 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl; 636 637 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR); 638 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY); 639 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 640 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 641 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 642 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA); 643 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL); 644 645 dev_err(sdev->dev, 646 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n", 647 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl); 648 } 649 650 static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev) 651 { 652 mtl_enable_sdw_irq(sdev, false); 653 mtl_disable_ipc_interrupts(sdev); 654 return mtl_enable_interrupts(sdev, false); 655 } 656 657 int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core) 658 { 659 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 660 661 if (core == SOF_DSP_PRIMARY_CORE) 662 return mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE); 663 664 if (pm_ops->set_core_state) 665 return pm_ops->set_core_state(sdev, core, true); 666 667 return 0; 668 } 669 670 int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core) 671 { 672 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 673 int ret; 674 675 if (pm_ops->set_core_state) { 676 ret = pm_ops->set_core_state(sdev, core, false); 677 if (ret < 0) 678 return ret; 679 } 680 681 if (core == SOF_DSP_PRIMARY_CORE) 682 return mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 683 684 return 0; 685 } 686 687 /* Meteorlake ops */ 688 struct snd_sof_dsp_ops sof_mtl_ops; 689 EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 690 691 int sof_mtl_ops_init(struct snd_sof_dev *sdev) 692 { 693 struct sof_ipc4_fw_data *ipc4_data; 694 695 /* common defaults */ 696 memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 697 698 /* shutdown */ 699 sof_mtl_ops.shutdown = hda_dsp_shutdown; 700 701 /* doorbell */ 702 sof_mtl_ops.irq_thread = mtl_ipc_irq_thread; 703 704 /* ipc */ 705 sof_mtl_ops.send_msg = mtl_ipc_send_msg; 706 sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 707 sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 708 709 /* debug */ 710 sof_mtl_ops.debug_map = mtl_dsp_debugfs; 711 sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs); 712 sof_mtl_ops.dbg_dump = mtl_dsp_dump; 713 sof_mtl_ops.ipc_dump = mtl_ipc_dump; 714 715 /* pre/post fw run */ 716 sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 717 sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run; 718 719 /* parse platform specific extended manifest */ 720 sof_mtl_ops.parse_platform_ext_manifest = NULL; 721 722 /* dsp core get/put */ 723 sof_mtl_ops.core_get = mtl_dsp_core_get; 724 sof_mtl_ops.core_put = mtl_dsp_core_put; 725 726 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 727 if (!sdev->private) 728 return -ENOMEM; 729 730 ipc4_data = sdev->private; 731 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 732 733 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 734 735 ipc4_data->fw_context_save = true; 736 737 /* External library loading support */ 738 ipc4_data->load_library = hda_dsp_ipc4_load_library; 739 740 /* set DAI ops */ 741 hda_set_dai_drv_ops(sdev, &sof_mtl_ops); 742 743 sof_mtl_ops.set_power_state = hda_dsp_set_power_state_ipc4; 744 745 return 0; 746 }; 747 EXPORT_SYMBOL_NS(sof_mtl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 748 749 const struct sof_intel_dsp_desc mtl_chip_info = { 750 .cores_num = 3, 751 .init_core_mask = BIT(0), 752 .host_managed_cores_mask = BIT(0), 753 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 754 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 755 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 756 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 757 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 758 .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, 759 .rom_init_timeout = 300, 760 .ssp_count = MTL_SSP_COUNT, 761 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 762 .sdw_shim_base = SDW_SHIM_BASE_ACE, 763 .sdw_alh_base = SDW_ALH_BASE_ACE, 764 .d0i3_offset = MTL_HDA_VS_D0I3C, 765 .read_sdw_lcount = hda_sdw_check_lcount_common, 766 .enable_sdw_irq = mtl_enable_sdw_irq, 767 .check_sdw_irq = mtl_dsp_check_sdw_irq, 768 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, 769 .check_ipc_irq = mtl_dsp_check_ipc_irq, 770 .cl_init = mtl_dsp_cl_init, 771 .power_down_dsp = mtl_power_down_dsp, 772 .disable_interrupts = mtl_dsp_disable_interrupts, 773 .hw_ip_version = SOF_INTEL_ACE_1_0, 774 }; 775 EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 776 777 const struct sof_intel_dsp_desc arl_s_chip_info = { 778 .cores_num = 2, 779 .init_core_mask = BIT(0), 780 .host_managed_cores_mask = BIT(0), 781 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 782 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 783 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 784 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 785 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 786 .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, 787 .rom_init_timeout = 300, 788 .ssp_count = MTL_SSP_COUNT, 789 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 790 .sdw_shim_base = SDW_SHIM_BASE_ACE, 791 .sdw_alh_base = SDW_ALH_BASE_ACE, 792 .d0i3_offset = MTL_HDA_VS_D0I3C, 793 .read_sdw_lcount = hda_sdw_check_lcount_common, 794 .enable_sdw_irq = mtl_enable_sdw_irq, 795 .check_sdw_irq = mtl_dsp_check_sdw_irq, 796 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, 797 .check_ipc_irq = mtl_dsp_check_ipc_irq, 798 .cl_init = mtl_dsp_cl_init, 799 .power_down_dsp = mtl_power_down_dsp, 800 .disable_interrupts = mtl_dsp_disable_interrupts, 801 .hw_ip_version = SOF_INTEL_ACE_1_0, 802 }; 803 EXPORT_SYMBOL_NS(arl_s_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 804