1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2022 Intel Corporation 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Meteorlake. 10 */ 11 12 #include <linux/debugfs.h> 13 #include <linux/firmware.h> 14 #include <linux/string_choices.h> 15 #include <sound/sof/ipc4/header.h> 16 #include <trace/events/sof_intel.h> 17 #include "../ipc4-priv.h" 18 #include "../ops.h" 19 #include "hda.h" 20 #include "hda-ipc.h" 21 #include "../sof-audio.h" 22 #include "mtl.h" 23 #include "telemetry.h" 24 25 static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = { 26 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 27 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 28 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 29 {"fw_regs", HDA_DSP_BAR, MTL_SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY}, 30 }; 31 32 static void mtl_ipc_host_done(struct snd_sof_dev *sdev) 33 { 34 /* 35 * clear busy interrupt to tell dsp controller this interrupt has been accepted, 36 * not trigger it again 37 */ 38 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR, 39 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY); 40 /* 41 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp 42 */ 43 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA, 44 MTL_DSP_REG_HFIPCXTDA_BUSY, 0); 45 } 46 47 static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev) 48 { 49 /* 50 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it, 51 * don't send more reply to host 52 */ 53 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA, 54 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE); 55 56 /* unmask Done interrupt */ 57 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 58 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE); 59 } 60 61 /* Check if an IPC IRQ occurred */ 62 bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev) 63 { 64 u32 irq_status; 65 u32 hfintipptr; 66 67 if (sdev->dspless_mode_selected) 68 return false; 69 70 /* read Interrupt IP Pointer */ 71 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 72 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 73 74 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status); 75 76 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC)) 77 return true; 78 79 return false; 80 } 81 EXPORT_SYMBOL_NS(mtl_dsp_check_ipc_irq, "SND_SOC_SOF_INTEL_MTL"); 82 83 /* Check if an SDW IRQ occurred */ 84 static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 85 { 86 u32 irq_status; 87 u32 hfintipptr; 88 89 /* read Interrupt IP Pointer */ 90 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 91 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 92 93 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW)) 94 return true; 95 96 return false; 97 } 98 99 int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 100 { 101 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 102 struct sof_ipc4_msg *msg_data = msg->msg_data; 103 104 if (hda_ipc4_tx_is_busy(sdev)) { 105 hdev->delayed_ipc_tx_msg = msg; 106 return 0; 107 } 108 109 hdev->delayed_ipc_tx_msg = NULL; 110 111 /* send the message via mailbox */ 112 if (msg_data->data_size) 113 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr, 114 msg_data->data_size); 115 116 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY, 117 msg_data->extension); 118 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR, 119 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY); 120 121 hda_dsp_ipc4_schedule_d0i3_work(hdev, msg); 122 123 return 0; 124 } 125 EXPORT_SYMBOL_NS(mtl_ipc_send_msg, "SND_SOC_SOF_INTEL_MTL"); 126 127 void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev) 128 { 129 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 130 const struct sof_intel_dsp_desc *chip = hda->desc; 131 132 if (sdev->dspless_mode_selected) 133 return; 134 135 /* enable IPC DONE and BUSY interrupts */ 136 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 137 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 138 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE); 139 } 140 141 void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev) 142 { 143 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 144 const struct sof_intel_dsp_desc *chip = hda->desc; 145 146 if (sdev->dspless_mode_selected) 147 return; 148 149 /* disable IPC DONE and BUSY interrupts */ 150 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 151 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0); 152 } 153 EXPORT_SYMBOL_NS(mtl_disable_ipc_interrupts, "SND_SOC_SOF_INTEL_MTL"); 154 155 static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 156 { 157 u32 hipcie; 158 u32 mask; 159 u32 val; 160 int ret; 161 162 if (sdev->dspless_mode_selected) 163 return; 164 165 /* Enable/Disable SoundWire interrupt */ 166 mask = MTL_DSP_REG_HfSNDWIE_IE_MASK; 167 if (enable) 168 val = mask; 169 else 170 val = 0; 171 172 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, mask, val); 173 174 /* check if operation was successful */ 175 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie, 176 (hipcie & mask) == val, 177 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 178 if (ret < 0) 179 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt %s\n", 180 str_enable_disable(enable)); 181 } 182 183 int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable) 184 { 185 u32 hfintipptr; 186 u32 irqinten; 187 u32 hipcie; 188 u32 mask; 189 u32 val; 190 int ret; 191 192 if (sdev->dspless_mode_selected) 193 return 0; 194 195 /* read Interrupt IP Pointer */ 196 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 197 198 /* Enable/Disable Host IPC and SOUNDWIRE */ 199 mask = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK; 200 if (enable) 201 val = mask; 202 else 203 val = 0; 204 205 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, mask, val); 206 207 /* check if operation was successful */ 208 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten, 209 (irqinten & mask) == val, 210 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 211 if (ret < 0) { 212 dev_err(sdev->dev, "failed to %s Host IPC and/or SOUNDWIRE\n", 213 str_enable_disable(enable)); 214 return ret; 215 } 216 217 /* Enable/Disable Host IPC interrupt*/ 218 mask = MTL_DSP_REG_HfHIPCIE_IE_MASK; 219 if (enable) 220 val = mask; 221 else 222 val = 0; 223 224 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, mask, val); 225 226 /* check if operation was successful */ 227 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie, 228 (hipcie & mask) == val, 229 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 230 if (ret < 0) { 231 dev_err(sdev->dev, "failed to set Host IPC interrupt %s\n", 232 str_enable_disable(enable)); 233 return ret; 234 } 235 236 return ret; 237 } 238 EXPORT_SYMBOL_NS(mtl_enable_interrupts, "SND_SOC_SOF_INTEL_MTL"); 239 240 /* pre fw run operations */ 241 int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) 242 { 243 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 244 u32 dsphfpwrsts; 245 u32 dsphfdsscs; 246 u32 cpa; 247 u32 pgs; 248 int ret; 249 u32 dsppwrctl; 250 u32 dsppwrsts; 251 const struct sof_intel_dsp_desc *chip; 252 253 chip = get_chip_info(sdev->pdata); 254 if (chip->hw_ip_version > SOF_INTEL_ACE_2_0) { 255 dsppwrctl = PTL_HFPWRCTL2; 256 dsppwrsts = PTL_HFPWRSTS2; 257 } else { 258 dsppwrctl = MTL_HFPWRCTL; 259 dsppwrsts = MTL_HFPWRSTS; 260 } 261 262 /* Set the DSP subsystem power on */ 263 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 264 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK); 265 266 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 267 usleep_range(1000, 1010); 268 269 /* poll with timeout to check if operation successful */ 270 cpa = MTL_HFDSSCS_CPA_MASK; 271 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 272 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 273 HDA_DSP_RESET_TIMEOUT_US); 274 if (ret < 0) { 275 dev_err(sdev->dev, "failed to enable DSP subsystem\n"); 276 return ret; 277 } 278 279 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */ 280 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, dsppwrctl, 281 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG); 282 283 usleep_range(1000, 1010); 284 285 /* poll with timeout to check if operation successful */ 286 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK; 287 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, dsppwrsts, dsphfpwrsts, 288 (dsphfpwrsts & pgs) == pgs, 289 HDA_DSP_REG_POLL_INTERVAL_US, 290 HDA_DSP_RESET_TIMEOUT_US); 291 if (ret < 0) 292 dev_err(sdev->dev, "failed to power up gated DSP domain\n"); 293 294 /* if SoundWire is used, make sure it is not power-gated */ 295 if (hdev->info.handle && hdev->info.link_mask > 0) 296 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, 297 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1)); 298 299 return ret; 300 } 301 EXPORT_SYMBOL_NS(mtl_dsp_pre_fw_run, "SND_SOC_SOF_INTEL_MTL"); 302 303 int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev) 304 { 305 int ret; 306 307 if (sdev->first_boot) { 308 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 309 310 ret = hda_sdw_startup(sdev); 311 if (ret < 0) { 312 dev_err(sdev->dev, "could not startup SoundWire links\n"); 313 return ret; 314 } 315 316 /* Check if IMR boot is usable */ 317 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) { 318 hdev->imrboot_supported = true; 319 debugfs_create_bool("skip_imr_boot", 320 0644, sdev->debugfs_root, 321 &hdev->skip_imr_boot); 322 } 323 } 324 325 hda_sdw_int_enable(sdev, true); 326 return 0; 327 } 328 EXPORT_SYMBOL_NS(mtl_dsp_post_fw_run, "SND_SOC_SOF_INTEL_MTL"); 329 330 void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 331 { 332 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 333 u32 fwsts; 334 u32 fwlec; 335 336 hda_dsp_get_state(sdev, level); 337 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS); 338 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR); 339 340 if (fwsts != 0xffffffff) 341 dev_err(sdev->dev, "Firmware state: %#x, status/error code: %#x\n", 342 fwsts, fwlec); 343 344 sof_ipc4_intel_dump_telemetry_state(sdev, flags); 345 } 346 EXPORT_SYMBOL_NS(mtl_dsp_dump, "SND_SOC_SOF_INTEL_MTL"); 347 348 static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev) 349 { 350 int val; 351 352 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE); 353 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK) 354 return true; 355 356 return false; 357 } 358 359 static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core) 360 { 361 unsigned int cpa; 362 u32 dspcxctl; 363 int ret; 364 365 /* Only the primary core can be powered up by the host */ 366 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev)) 367 return 0; 368 369 /* Program the owner of the IP & shim registers (10: Host CPU) */ 370 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 371 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL, 372 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT); 373 374 /* enable SPA bit */ 375 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 376 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 377 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK); 378 379 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 380 usleep_range(1000, 1010); 381 382 /* poll with timeout to check if operation successful */ 383 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK; 384 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 385 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 386 HDA_DSP_RESET_TIMEOUT_US); 387 if (ret < 0) { 388 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n", 389 __func__); 390 return ret; 391 } 392 393 /* set primary core mask and refcount to 1 */ 394 sdev->enabled_cores_mask = BIT(SOF_DSP_PRIMARY_CORE); 395 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 1; 396 397 return 0; 398 } 399 400 static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core) 401 { 402 u32 dspcxctl; 403 int ret; 404 405 /* Only the primary core can be powered down by the host */ 406 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev)) 407 return 0; 408 409 /* disable SPA bit */ 410 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 411 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0); 412 413 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */ 414 usleep_range(1000, 1010); 415 416 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 417 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK), 418 HDA_DSP_REG_POLL_INTERVAL_US, 419 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 420 if (ret < 0) { 421 dev_err(sdev->dev, "failed to power down primary core\n"); 422 return ret; 423 } 424 425 sdev->enabled_cores_mask = 0; 426 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 0; 427 428 return 0; 429 } 430 431 int mtl_power_down_dsp(struct snd_sof_dev *sdev) 432 { 433 u32 dsphfdsscs, cpa; 434 int ret; 435 436 /* first power down core */ 437 ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 438 if (ret) { 439 dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret); 440 return ret; 441 } 442 443 /* Set the DSP subsystem power down */ 444 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 445 MTL_HFDSSCS_SPA_MASK, 0); 446 447 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */ 448 usleep_range(1000, 1010); 449 450 /* poll with timeout to check if operation successful */ 451 cpa = MTL_HFDSSCS_CPA_MASK; 452 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS); 453 return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 454 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US, 455 HDA_DSP_RESET_TIMEOUT_US); 456 } 457 EXPORT_SYMBOL_NS(mtl_power_down_dsp, "SND_SOC_SOF_INTEL_MTL"); 458 459 int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) 460 { 461 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 462 const struct sof_intel_dsp_desc *chip = hda->desc; 463 unsigned int status, target_status; 464 u32 ipc_hdr, flags; 465 char *dump_msg; 466 int ret; 467 468 /* step 1: purge FW request */ 469 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL; 470 if (!imr_boot) 471 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9); 472 473 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr); 474 475 /* step 2: power up primary core */ 476 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE); 477 if (ret < 0) { 478 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 479 dev_err(sdev->dev, "dsp core 0/1 power up failed\n"); 480 goto err; 481 } 482 483 dev_dbg(sdev->dev, "Primary core power up successful\n"); 484 485 /* step 3: wait for IPC DONE bit from ROM */ 486 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status, 487 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask), 488 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_INIT_TIMEOUT_US); 489 if (ret < 0) { 490 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 491 dev_err(sdev->dev, "timeout waiting for purge IPC done\n"); 492 goto err; 493 } 494 495 /* set DONE bit to clear the reply IPC message */ 496 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask, 497 chip->ipc_ack_mask); 498 499 /* step 4: enable interrupts */ 500 ret = mtl_enable_interrupts(sdev, true); 501 if (ret < 0) { 502 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 503 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__); 504 goto err; 505 } 506 507 mtl_enable_ipc_interrupts(sdev); 508 509 if (chip->rom_status_reg == MTL_DSP_ROM_STS) { 510 /* 511 * Workaround: when the ROM status register is pointing to 512 * the SRAM window (MTL_DSP_ROM_STS) the platform cannot catch 513 * ROM_INIT_DONE because of a very short timing window. 514 * Follow the recommendations and skip target state waiting. 515 */ 516 return 0; 517 } 518 519 /* 520 * step 7: 521 * - Cold/Full boot: wait for ROM init to proceed to download the firmware 522 * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR) 523 */ 524 if (imr_boot) 525 target_status = FSR_STATE_FW_ENTERED; 526 else 527 target_status = FSR_STATE_INIT_DONE; 528 529 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 530 chip->rom_status_reg, status, 531 (FSR_TO_STATE_CODE(status) == target_status), 532 HDA_DSP_REG_POLL_INTERVAL_US, 533 chip->rom_init_timeout * 534 USEC_PER_MSEC); 535 536 if (!ret) 537 return 0; 538 539 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 540 dev_err(sdev->dev, 541 "%s: timeout with rom_status_reg (%#x) read\n", 542 __func__, chip->rom_status_reg); 543 544 err: 545 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL; 546 547 /* after max boot attempts make sure that the dump is printed */ 548 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 549 flags &= ~SOF_DBG_DUMP_OPTIONAL; 550 551 dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d", 552 hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS); 553 snd_sof_dsp_dbg_dump(sdev, dump_msg, flags); 554 mtl_enable_interrupts(sdev, false); 555 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 556 557 kfree(dump_msg); 558 return ret; 559 } 560 EXPORT_SYMBOL_NS(mtl_dsp_cl_init, "SND_SOC_SOF_INTEL_MTL"); 561 562 irqreturn_t mtl_ipc_irq_thread(int irq, void *context) 563 { 564 struct sof_ipc4_msg notification_data = {{ 0 }}; 565 struct snd_sof_dev *sdev = context; 566 bool ack_received = false; 567 bool ipc_irq = false; 568 u32 hipcida; 569 u32 hipctdr; 570 571 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 572 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 573 574 /* reply message from DSP */ 575 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) { 576 /* DSP received the message */ 577 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 578 MTL_DSP_REG_HFIPCXCTL_DONE, 0); 579 580 mtl_ipc_dsp_done(sdev); 581 582 ipc_irq = true; 583 ack_received = true; 584 } 585 586 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) { 587 /* Message from DSP (reply or notification) */ 588 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 589 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK; 590 591 /* 592 * ACE fw sends a new fw ipc message to host to 593 * notify the status of the last host ipc message 594 */ 595 if (primary & SOF_IPC4_MSG_DIR_MASK) { 596 /* Reply received */ 597 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { 598 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data; 599 600 data->primary = primary; 601 data->extension = extension; 602 603 spin_lock_irq(&sdev->ipc_lock); 604 605 snd_sof_ipc_get_reply(sdev); 606 mtl_ipc_host_done(sdev); 607 snd_sof_ipc_reply(sdev, data->primary); 608 609 spin_unlock_irq(&sdev->ipc_lock); 610 } else { 611 dev_dbg_ratelimited(sdev->dev, 612 "IPC reply before FW_READY: %#x|%#x\n", 613 primary, extension); 614 } 615 } else { 616 /* Notification received */ 617 notification_data.primary = primary; 618 notification_data.extension = extension; 619 620 sdev->ipc->msg.rx_data = ¬ification_data; 621 snd_sof_ipc_msgs_rx(sdev); 622 sdev->ipc->msg.rx_data = NULL; 623 624 mtl_ipc_host_done(sdev); 625 } 626 627 ipc_irq = true; 628 } 629 630 if (!ipc_irq) { 631 /* This interrupt is not shared so no need to return IRQ_NONE. */ 632 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); 633 } 634 635 if (ack_received) { 636 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 637 638 if (hdev->delayed_ipc_tx_msg) 639 mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg); 640 } 641 642 return IRQ_HANDLED; 643 } 644 EXPORT_SYMBOL_NS(mtl_ipc_irq_thread, "SND_SOC_SOF_INTEL_MTL"); 645 646 int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev) 647 { 648 return MTL_DSP_MBOX_UPLINK_OFFSET; 649 } 650 EXPORT_SYMBOL_NS(mtl_dsp_ipc_get_mailbox_offset, "SND_SOC_SOF_INTEL_MTL"); 651 652 int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id) 653 { 654 return MTL_SRAM_WINDOW_OFFSET(id); 655 } 656 EXPORT_SYMBOL_NS(mtl_dsp_ipc_get_window_offset, "SND_SOC_SOF_INTEL_MTL"); 657 658 void mtl_ipc_dump(struct snd_sof_dev *sdev) 659 { 660 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl; 661 662 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR); 663 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY); 664 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 665 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 666 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 667 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA); 668 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL); 669 670 dev_err(sdev->dev, 671 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n", 672 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl); 673 } 674 EXPORT_SYMBOL_NS(mtl_ipc_dump, "SND_SOC_SOF_INTEL_MTL"); 675 676 static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev) 677 { 678 mtl_enable_sdw_irq(sdev, false); 679 mtl_disable_ipc_interrupts(sdev); 680 return mtl_enable_interrupts(sdev, false); 681 } 682 683 int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core) 684 { 685 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 686 687 if (core == SOF_DSP_PRIMARY_CORE) 688 return mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE); 689 690 if (pm_ops->set_core_state) 691 return pm_ops->set_core_state(sdev, core, true); 692 693 return 0; 694 } 695 EXPORT_SYMBOL_NS(mtl_dsp_core_get, "SND_SOC_SOF_INTEL_MTL"); 696 697 int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core) 698 { 699 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 700 int ret; 701 702 if (pm_ops->set_core_state) { 703 ret = pm_ops->set_core_state(sdev, core, false); 704 if (ret < 0) 705 return ret; 706 } 707 708 if (core == SOF_DSP_PRIMARY_CORE) 709 return mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 710 711 return 0; 712 } 713 EXPORT_SYMBOL_NS(mtl_dsp_core_put, "SND_SOC_SOF_INTEL_MTL"); 714 715 /* Meteorlake ops */ 716 struct snd_sof_dsp_ops sof_mtl_ops; 717 718 int sof_mtl_ops_init(struct snd_sof_dev *sdev) 719 { 720 struct sof_ipc4_fw_data *ipc4_data; 721 722 /* common defaults */ 723 memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 724 725 /* shutdown */ 726 sof_mtl_ops.shutdown = hda_dsp_shutdown; 727 728 /* doorbell */ 729 sof_mtl_ops.irq_thread = mtl_ipc_irq_thread; 730 731 /* ipc */ 732 sof_mtl_ops.send_msg = mtl_ipc_send_msg; 733 sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 734 sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 735 736 /* debug */ 737 sof_mtl_ops.debug_map = mtl_dsp_debugfs; 738 sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs); 739 sof_mtl_ops.dbg_dump = mtl_dsp_dump; 740 sof_mtl_ops.ipc_dump = mtl_ipc_dump; 741 742 /* pre/post fw run */ 743 sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 744 sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run; 745 746 /* parse platform specific extended manifest */ 747 sof_mtl_ops.parse_platform_ext_manifest = NULL; 748 749 /* dsp core get/put */ 750 sof_mtl_ops.core_get = mtl_dsp_core_get; 751 sof_mtl_ops.core_put = mtl_dsp_core_put; 752 753 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 754 if (!sdev->private) 755 return -ENOMEM; 756 757 ipc4_data = sdev->private; 758 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 759 760 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 761 762 ipc4_data->fw_context_save = true; 763 764 /* External library loading support */ 765 ipc4_data->load_library = hda_dsp_ipc4_load_library; 766 767 /* set DAI ops */ 768 hda_set_dai_drv_ops(sdev, &sof_mtl_ops); 769 770 sof_mtl_ops.set_power_state = hda_dsp_set_power_state_ipc4; 771 772 return 0; 773 }; 774 775 const struct sof_intel_dsp_desc mtl_chip_info = { 776 .cores_num = 3, 777 .init_core_mask = BIT(0), 778 .host_managed_cores_mask = BIT(0), 779 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 780 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 781 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 782 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 783 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 784 .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, 785 .rom_init_timeout = 300, 786 .ssp_count = MTL_SSP_COUNT, 787 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 788 .sdw_shim_base = SDW_SHIM_BASE_ACE, 789 .sdw_alh_base = SDW_ALH_BASE_ACE, 790 .d0i3_offset = MTL_HDA_VS_D0I3C, 791 .read_sdw_lcount = hda_sdw_check_lcount_common, 792 .enable_sdw_irq = mtl_enable_sdw_irq, 793 .check_sdw_irq = mtl_dsp_check_sdw_irq, 794 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, 795 .sdw_process_wakeen = hda_sdw_process_wakeen_common, 796 .check_ipc_irq = mtl_dsp_check_ipc_irq, 797 .cl_init = mtl_dsp_cl_init, 798 .power_down_dsp = mtl_power_down_dsp, 799 .disable_interrupts = mtl_dsp_disable_interrupts, 800 .hw_ip_version = SOF_INTEL_ACE_1_0, 801 }; 802 803 const struct sof_intel_dsp_desc arl_s_chip_info = { 804 .cores_num = 2, 805 .init_core_mask = BIT(0), 806 .host_managed_cores_mask = BIT(0), 807 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 808 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 809 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 810 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 811 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 812 .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, 813 .rom_init_timeout = 300, 814 .ssp_count = MTL_SSP_COUNT, 815 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 816 .sdw_shim_base = SDW_SHIM_BASE_ACE, 817 .sdw_alh_base = SDW_ALH_BASE_ACE, 818 .d0i3_offset = MTL_HDA_VS_D0I3C, 819 .read_sdw_lcount = hda_sdw_check_lcount_common, 820 .enable_sdw_irq = mtl_enable_sdw_irq, 821 .check_sdw_irq = mtl_dsp_check_sdw_irq, 822 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, 823 .sdw_process_wakeen = hda_sdw_process_wakeen_common, 824 .check_ipc_irq = mtl_dsp_check_ipc_irq, 825 .cl_init = mtl_dsp_cl_init, 826 .power_down_dsp = mtl_power_down_dsp, 827 .disable_interrupts = mtl_dsp_disable_interrupts, 828 .hw_ip_version = SOF_INTEL_ACE_1_0, 829 }; 830