1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2022 Intel Corporation. All rights reserved. 4 // 5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on Meteorlake. 10 */ 11 12 #include <linux/firmware.h> 13 #include <sound/sof/ipc4/header.h> 14 #include "../ipc4-priv.h" 15 #include "../ops.h" 16 #include "hda.h" 17 #include "hda-ipc.h" 18 #include "../sof-audio.h" 19 #include "mtl.h" 20 21 static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = { 22 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 23 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 24 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 25 }; 26 27 static void mtl_ipc_host_done(struct snd_sof_dev *sdev) 28 { 29 /* 30 * clear busy interrupt to tell dsp controller this interrupt has been accepted, 31 * not trigger it again 32 */ 33 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR, 34 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY); 35 /* 36 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp 37 */ 38 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA, 39 MTL_DSP_REG_HFIPCXTDA_BUSY, 0); 40 } 41 42 static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev) 43 { 44 /* 45 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it, 46 * don't send more reply to host 47 */ 48 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA, 49 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE); 50 51 /* unmask Done interrupt */ 52 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 53 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE); 54 } 55 56 /* Check if an IPC IRQ occurred */ 57 static bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev) 58 { 59 u32 irq_status; 60 u32 hfintipptr; 61 62 /* read Interrupt IP Pointer */ 63 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 64 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 65 66 dev_vdbg(sdev->dev, "irq handler: irq_status:0x%x\n", irq_status); 67 68 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC)) 69 return true; 70 71 return false; 72 } 73 74 /* Check if an SDW IRQ occurred */ 75 static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 76 { 77 u32 irq_status; 78 u32 hfintipptr; 79 80 /* read Interrupt IP Pointer */ 81 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 82 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 83 84 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW)) 85 return true; 86 87 return false; 88 } 89 90 static int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 91 { 92 struct sof_ipc4_msg *msg_data = msg->msg_data; 93 94 /* send the message via mailbox */ 95 if (msg_data->data_size) 96 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr, 97 msg_data->data_size); 98 99 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY, 100 msg_data->extension); 101 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR, 102 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY); 103 104 return 0; 105 } 106 107 static void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev) 108 { 109 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 110 const struct sof_intel_dsp_desc *chip = hda->desc; 111 112 /* enable IPC DONE and BUSY interrupts */ 113 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 114 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 115 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE); 116 } 117 118 static void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev) 119 { 120 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 121 const struct sof_intel_dsp_desc *chip = hda->desc; 122 123 /* disable IPC DONE and BUSY interrupts */ 124 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 125 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0); 126 } 127 128 static int mtl_enable_interrupts(struct snd_sof_dev *sdev) 129 { 130 u32 hfintipptr; 131 u32 irqinten; 132 u32 host_ipc; 133 u32 hipcie; 134 int ret; 135 136 /* read Interrupt IP Pointer */ 137 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 138 139 /* Enable Host IPC and SOUNDWIRE */ 140 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, 141 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK, 142 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK); 143 144 /* check if operation was successful */ 145 host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK; 146 irqinten = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr); 147 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten, 148 (irqinten & host_ipc) == host_ipc, 149 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 150 if (ret < 0) { 151 dev_err(sdev->dev, "failed to enable Host IPC and/or SOUNDWIRE\n"); 152 return ret; 153 } 154 155 /* Set Host IPC interrupt enable */ 156 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, 157 MTL_DSP_REG_HfHIPCIE_IE_MASK, MTL_DSP_REG_HfHIPCIE_IE_MASK); 158 159 /* check if operation was successful */ 160 host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK; 161 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE); 162 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie, 163 (hipcie & host_ipc) == host_ipc, 164 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 165 if (ret < 0) { 166 dev_err(sdev->dev, "failed to set Host IPC interrupt enable\n"); 167 return ret; 168 } 169 170 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, 171 MTL_DSP_REG_HfSNDWIE_IE_MASK, MTL_DSP_REG_HfSNDWIE_IE_MASK); 172 host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK; 173 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE); 174 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie, 175 (hipcie & host_ipc) == host_ipc, 176 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 177 if (ret < 0) 178 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt enable\n"); 179 180 return ret; 181 } 182 183 static int mtl_disable_interrupts(struct snd_sof_dev *sdev) 184 { 185 u32 hfintipptr; 186 u32 irqinten; 187 u32 host_ipc; 188 u32 hipcie; 189 int ret1; 190 int ret; 191 192 /* read Interrupt IP Pointer */ 193 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 194 195 /* Disable Host IPC and SOUNDWIRE */ 196 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, 197 MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK, 0); 198 199 /* check if operation was successful */ 200 host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK; 201 irqinten = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr); 202 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten, 203 (irqinten & host_ipc) == 0, 204 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); 205 /* Continue to disable other interrupts when error happens */ 206 if (ret < 0) 207 dev_err(sdev->dev, "failed to disable Host IPC and SoundWire\n"); 208 209 /* Set Host IPC interrupt disable */ 210 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, 211 MTL_DSP_REG_HfHIPCIE_IE_MASK, 0); 212 213 /* check if operation was successful */ 214 host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK; 215 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE); 216 ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie, 217 (hipcie & host_ipc) == 0, 218 HDA_DSP_REG_POLL_INTERVAL_US, 219 HDA_DSP_RESET_TIMEOUT_US); 220 if (ret1 < 0) { 221 dev_err(sdev->dev, "failed to set Host IPC interrupt disable\n"); 222 if (!ret) 223 ret = ret1; 224 } 225 226 /* Set SoundWire IPC interrupt disable */ 227 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, 228 MTL_DSP_REG_HfSNDWIE_IE_MASK, 0); 229 host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK; 230 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE); 231 ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie, 232 (hipcie & host_ipc) == 0, 233 HDA_DSP_REG_POLL_INTERVAL_US, 234 HDA_DSP_RESET_TIMEOUT_US); 235 if (ret1 < 0) { 236 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt disable\n"); 237 if (!ret) 238 ret = ret1; 239 } 240 241 return ret; 242 } 243 244 /* pre fw run operations */ 245 static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) 246 { 247 u32 dsphfpwrsts; 248 u32 dsphfdsscs; 249 u32 cpa; 250 u32 pgs; 251 int ret; 252 253 /* Set the DSP subsystem power on */ 254 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 255 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK); 256 257 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 258 usleep_range(1000, 1010); 259 260 /* poll with timeout to check if operation successful */ 261 cpa = MTL_HFDSSCS_CPA_MASK; 262 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS); 263 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 264 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 265 HDA_DSP_RESET_TIMEOUT_US); 266 if (ret < 0) { 267 dev_err(sdev->dev, "failed to enable DSP subsystem\n"); 268 return ret; 269 } 270 271 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */ 272 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, 273 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG); 274 275 usleep_range(1000, 1010); 276 277 /* poll with timeout to check if operation successful */ 278 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK; 279 dsphfpwrsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFPWRSTS); 280 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts, 281 (dsphfpwrsts & pgs) == pgs, 282 HDA_DSP_REG_POLL_INTERVAL_US, 283 HDA_DSP_RESET_TIMEOUT_US); 284 if (ret < 0) 285 dev_err(sdev->dev, "failed to power up gated DSP domain\n"); 286 287 /* make sure SoundWire is not power-gated */ 288 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_HFPWRCTL, 289 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1)); 290 return ret; 291 } 292 293 static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev) 294 { 295 int ret; 296 297 if (sdev->first_boot) { 298 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 299 300 ret = hda_sdw_startup(sdev); 301 if (ret < 0) { 302 dev_err(sdev->dev, "could not startup SoundWire links\n"); 303 return ret; 304 } 305 306 /* Check if IMR boot is usable */ 307 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) 308 hdev->imrboot_supported = true; 309 } 310 311 hda_sdw_int_enable(sdev, true); 312 return 0; 313 } 314 315 static void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 316 { 317 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 318 u32 romdbgsts; 319 u32 romdbgerr; 320 u32 fwsts; 321 u32 fwlec; 322 323 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS); 324 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR); 325 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY); 326 romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR); 327 328 dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec); 329 dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts, 330 romdbgerr); 331 romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3); 332 dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n", 333 romdbgsts & BIT(24) ? "" : " not"); 334 } 335 336 static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev) 337 { 338 int val; 339 340 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE); 341 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK) 342 return true; 343 344 return false; 345 } 346 347 static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core) 348 { 349 unsigned int cpa; 350 u32 dspcxctl; 351 int ret; 352 353 /* Only the primary core can be powered up by the host */ 354 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev)) 355 return 0; 356 357 /* Program the owner of the IP & shim registers (10: Host CPU) */ 358 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 359 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL, 360 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT); 361 362 /* enable SPA bit */ 363 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 364 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 365 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK); 366 367 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 368 usleep_range(1000, 1010); 369 370 /* poll with timeout to check if operation successful */ 371 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK; 372 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 373 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US, 374 HDA_DSP_RESET_TIMEOUT_US); 375 if (ret < 0) { 376 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n", 377 __func__); 378 return ret; 379 } 380 381 /* did core power up ? */ 382 dspcxctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE); 383 if ((dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK) 384 != MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK) { 385 dev_err(sdev->dev, "power up core failed core %d adspcs %#x\n", 386 core, dspcxctl); 387 ret = -EIO; 388 } 389 390 return ret; 391 } 392 393 static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core) 394 { 395 u32 dspcxctl; 396 int ret; 397 398 /* Only the primary core can be powered down by the host */ 399 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev)) 400 return 0; 401 402 /* disable SPA bit */ 403 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, 404 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0); 405 406 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 407 usleep_range(1000, 1010); 408 409 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl, 410 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK), 411 HDA_DSP_REG_POLL_INTERVAL_US, 412 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 413 if (ret < 0) 414 dev_err(sdev->dev, "failed to power down primary core\n"); 415 416 return ret; 417 } 418 419 static int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) 420 { 421 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 422 const struct sof_intel_dsp_desc *chip = hda->desc; 423 unsigned int status; 424 u32 ipc_hdr; 425 int ret; 426 427 /* step 1: purge FW request */ 428 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL; 429 if (!imr_boot) 430 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9); 431 432 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr); 433 434 /* step 2: power up primary core */ 435 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE); 436 if (ret < 0) { 437 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 438 dev_err(sdev->dev, "dsp core 0/1 power up failed\n"); 439 goto err; 440 } 441 442 dev_dbg(sdev->dev, "Primary core power up successful\n"); 443 444 /* step 3: wait for IPC DONE bit from ROM */ 445 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status, 446 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask), 447 HDA_DSP_REG_POLL_INTERVAL_US, MTL_DSP_PURGE_TIMEOUT_US); 448 if (ret < 0) { 449 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 450 dev_err(sdev->dev, "timeout waiting for purge IPC done\n"); 451 goto err; 452 } 453 454 /* set DONE bit to clear the reply IPC message */ 455 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask, 456 chip->ipc_ack_mask); 457 458 /* step 4: enable interrupts */ 459 ret = mtl_enable_interrupts(sdev); 460 if (ret < 0) { 461 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 462 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__); 463 goto err; 464 } 465 466 mtl_enable_ipc_interrupts(sdev); 467 468 /* 469 * ACE workaround: don't wait for ROM INIT. 470 * The platform cannot catch ROM_INIT_DONE because of a very short 471 * timing window. Follow the recommendations and skip this part. 472 */ 473 474 return 0; 475 476 err: 477 snd_sof_dsp_dbg_dump(sdev, "MTL DSP init fail", 0); 478 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); 479 return ret; 480 } 481 482 static irqreturn_t mtl_ipc_irq_thread(int irq, void *context) 483 { 484 struct sof_ipc4_msg notification_data = {{ 0 }}; 485 struct snd_sof_dev *sdev = context; 486 bool ipc_irq = false; 487 u32 hipcida; 488 u32 hipctdr; 489 490 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 491 492 /* reply message from DSP */ 493 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) { 494 /* DSP received the message */ 495 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL, 496 MTL_DSP_REG_HFIPCXCTL_DONE, 0); 497 498 mtl_ipc_dsp_done(sdev); 499 500 ipc_irq = true; 501 } 502 503 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 504 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) { 505 /* Message from DSP (reply or notification) */ 506 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY); 507 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK; 508 509 /* 510 * ACE fw sends a new fw ipc message to host to 511 * notify the status of the last host ipc message 512 */ 513 if (primary & SOF_IPC4_MSG_DIR_MASK) { 514 /* Reply received */ 515 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data; 516 517 data->primary = primary; 518 data->extension = extension; 519 520 spin_lock_irq(&sdev->ipc_lock); 521 522 snd_sof_ipc_get_reply(sdev); 523 snd_sof_ipc_reply(sdev, data->primary); 524 525 spin_unlock_irq(&sdev->ipc_lock); 526 } else { 527 /* Notification received */ 528 notification_data.primary = primary; 529 notification_data.extension = extension; 530 531 sdev->ipc->msg.rx_data = ¬ification_data; 532 snd_sof_ipc_msgs_rx(sdev); 533 sdev->ipc->msg.rx_data = NULL; 534 } 535 536 mtl_ipc_host_done(sdev); 537 538 ipc_irq = true; 539 } 540 541 if (!ipc_irq) { 542 /* This interrupt is not shared so no need to return IRQ_NONE. */ 543 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n"); 544 } 545 546 return IRQ_HANDLED; 547 } 548 549 static int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev) 550 { 551 return MTL_DSP_MBOX_UPLINK_OFFSET; 552 } 553 554 static int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id) 555 { 556 return MTL_SRAM_WINDOW_OFFSET(id); 557 } 558 559 static int mtl_suspend(struct snd_sof_dev *sdev, bool runtime_suspend) 560 { 561 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 562 const struct sof_intel_dsp_desc *chip = hda->desc; 563 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 564 struct hdac_bus *bus = sof_to_bus(sdev); 565 #endif 566 u32 dsphfdsscs; 567 u32 cpa; 568 int ret; 569 int i; 570 571 mtl_disable_ipc_interrupts(sdev); 572 ret = mtl_disable_interrupts(sdev); 573 if (ret) 574 return ret; 575 576 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 577 hda_codec_jack_wake_enable(sdev, runtime_suspend); 578 /* power down all hda link */ 579 snd_hdac_ext_bus_link_power_down_all(bus); 580 #endif 581 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, 582 MTL_HFPWRCTL_WPDSPHPXPG, 0); 583 584 /* Set the DSP subsystem power down */ 585 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, 586 MTL_HFDSSCS_SPA_MASK, 0); 587 588 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */ 589 usleep_range(1000, 1010); 590 591 /* poll with timeout to check if operation successful */ 592 cpa = MTL_HFDSSCS_CPA_MASK; 593 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS); 594 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs, 595 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US, 596 HDA_DSP_RESET_TIMEOUT_US); 597 if (ret < 0) 598 dev_err(sdev->dev, "failed to disable DSP subsystem\n"); 599 600 /* reset ref counts for all cores */ 601 for (i = 0; i < chip->cores_num; i++) 602 sdev->dsp_core_ref_count[i] = 0; 603 604 /* TODO: need to reset controller? */ 605 606 /* display codec can be powered off after link reset */ 607 hda_codec_i915_display_power(sdev, false); 608 609 return 0; 610 } 611 612 static int mtl_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 613 { 614 const struct sof_dsp_power_state target_dsp_state = { 615 .state = target_state, 616 .substate = target_state == SOF_DSP_PM_D0 ? 617 SOF_HDA_DSP_PM_D0I3 : 0, 618 }; 619 int ret; 620 621 ret = mtl_suspend(sdev, false); 622 if (ret < 0) 623 return ret; 624 625 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 626 } 627 628 static int mtl_dsp_runtime_suspend(struct snd_sof_dev *sdev) 629 { 630 const struct sof_dsp_power_state target_state = { 631 .state = SOF_DSP_PM_D3, 632 }; 633 int ret; 634 635 ret = mtl_suspend(sdev, true); 636 if (ret < 0) 637 return ret; 638 639 return snd_sof_dsp_set_power_state(sdev, &target_state); 640 } 641 642 static int mtl_resume(struct snd_sof_dev *sdev, bool runtime_resume) 643 { 644 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 645 struct hdac_bus *bus = sof_to_bus(sdev); 646 struct hdac_ext_link *hlink = NULL; 647 #endif 648 649 /* display codec must be powered before link reset */ 650 hda_codec_i915_display_power(sdev, true); 651 652 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 653 /* check jack status */ 654 if (runtime_resume) { 655 hda_codec_jack_wake_enable(sdev, false); 656 if (sdev->system_suspend_target == SOF_SUSPEND_NONE) 657 hda_codec_jack_check(sdev); 658 } 659 660 /* turn off the links that were off before suspend */ 661 list_for_each_entry(hlink, &bus->hlink_list, list) { 662 if (!hlink->ref_count) 663 snd_hdac_ext_bus_link_power_down(hlink); 664 } 665 666 /* check dma status and clean up CORB/RIRB buffers */ 667 if (!bus->cmd_dma_state) 668 snd_hdac_bus_stop_cmd_io(bus); 669 #endif 670 671 return 0; 672 } 673 674 static int mtl_dsp_resume(struct snd_sof_dev *sdev) 675 { 676 const struct sof_dsp_power_state target_state = { 677 .state = SOF_DSP_PM_D0, 678 .substate = SOF_HDA_DSP_PM_D0I0, 679 }; 680 int ret; 681 682 ret = mtl_resume(sdev, false); 683 if (ret < 0) 684 return ret; 685 686 return snd_sof_dsp_set_power_state(sdev, &target_state); 687 } 688 689 static int mtl_dsp_runtime_resume(struct snd_sof_dev *sdev) 690 { 691 const struct sof_dsp_power_state target_state = { 692 .state = SOF_DSP_PM_D0, 693 }; 694 int ret; 695 696 ret = mtl_resume(sdev, true); 697 if (ret < 0) 698 return ret; 699 700 return snd_sof_dsp_set_power_state(sdev, &target_state); 701 } 702 703 static void mtl_ipc_dump(struct snd_sof_dev *sdev) 704 { 705 u32 hipcctl; 706 u32 hipcida; 707 u32 hipctdr; 708 709 /* read IPC status */ 710 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA); 711 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL); 712 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR); 713 714 /* dump the IPC regs */ 715 /* TODO: parse the raw msg */ 716 dev_err(sdev->dev, 717 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 718 hipcida, hipctdr, hipcctl); 719 } 720 721 /* Meteorlake ops */ 722 struct snd_sof_dsp_ops sof_mtl_ops; 723 EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 724 725 int sof_mtl_ops_init(struct snd_sof_dev *sdev) 726 { 727 struct sof_ipc4_fw_data *ipc4_data; 728 729 /* common defaults */ 730 memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 731 732 /* shutdown */ 733 sof_mtl_ops.shutdown = hda_dsp_shutdown; 734 735 /* doorbell */ 736 sof_mtl_ops.irq_thread = mtl_ipc_irq_thread; 737 738 /* ipc */ 739 sof_mtl_ops.send_msg = mtl_ipc_send_msg; 740 sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 741 sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 742 743 /* debug */ 744 sof_mtl_ops.debug_map = mtl_dsp_debugfs; 745 sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs); 746 sof_mtl_ops.dbg_dump = mtl_dsp_dump; 747 sof_mtl_ops.ipc_dump = mtl_ipc_dump; 748 749 /* pre/post fw run */ 750 sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 751 sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run; 752 753 /* parse platform specific extended manifest */ 754 sof_mtl_ops.parse_platform_ext_manifest = NULL; 755 756 /* dsp core get/put */ 757 /* TODO: add core_get and core_put */ 758 759 /* PM */ 760 sof_mtl_ops.suspend = mtl_dsp_suspend; 761 sof_mtl_ops.resume = mtl_dsp_resume; 762 sof_mtl_ops.runtime_suspend = mtl_dsp_runtime_suspend; 763 sof_mtl_ops.runtime_resume = mtl_dsp_runtime_resume; 764 765 sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 766 if (!sdev->private) 767 return -ENOMEM; 768 769 ipc4_data = sdev->private; 770 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 771 772 /* set DAI ops */ 773 hda_set_dai_drv_ops(sdev, &sof_mtl_ops); 774 775 return 0; 776 }; 777 EXPORT_SYMBOL_NS(sof_mtl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 778 779 const struct sof_intel_dsp_desc mtl_chip_info = { 780 .cores_num = 3, 781 .init_core_mask = BIT(0), 782 .host_managed_cores_mask = BIT(0), 783 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 784 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 785 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 786 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 787 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 788 .rom_status_reg = MTL_DSP_ROM_STS, 789 .rom_init_timeout = 300, 790 .ssp_count = ICL_SSP_COUNT, 791 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 792 .sdw_shim_base = SDW_SHIM_BASE_ACE, 793 .sdw_alh_base = SDW_ALH_BASE_ACE, 794 .check_sdw_irq = mtl_dsp_check_sdw_irq, 795 .check_ipc_irq = mtl_dsp_check_ipc_irq, 796 .cl_init = mtl_dsp_cl_init, 797 .hw_ip_version = SOF_INTEL_ACE_1_0, 798 }; 799 EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 800