1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2023 Intel Corporation. All rights reserved. 4 5 /* 6 * Hardware interface for audio DSP on LunarLake. 7 */ 8 9 #include <linux/debugfs.h> 10 #include <linux/firmware.h> 11 #include <sound/hda_register.h> 12 #include <sound/sof/ipc4/header.h> 13 #include <trace/events/sof_intel.h> 14 #include "../ipc4-priv.h" 15 #include "../ops.h" 16 #include "hda.h" 17 #include "hda-ipc.h" 18 #include "../sof-audio.h" 19 #include "mtl.h" 20 #include "lnl.h" 21 #include <sound/hda-mlink.h> 22 23 /* LunarLake ops */ 24 struct snd_sof_dsp_ops sof_lnl_ops; 25 EXPORT_SYMBOL_NS(sof_lnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 26 27 static const struct snd_sof_debugfs_map lnl_dsp_debugfs[] = { 28 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 29 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 30 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 31 {"fw_regs", HDA_DSP_BAR, MTL_SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY}, 32 }; 33 34 /* this helps allows the DSP to setup DMIC/SSP */ 35 static int hdac_bus_offload_dmic_ssp(struct hdac_bus *bus) 36 { 37 int ret; 38 39 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_SSP, true); 40 if (ret < 0) 41 return ret; 42 43 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_DMIC, true); 44 if (ret < 0) 45 return ret; 46 47 return 0; 48 } 49 50 static int lnl_hda_dsp_probe(struct snd_sof_dev *sdev) 51 { 52 int ret; 53 54 ret = hda_dsp_probe(sdev); 55 if (ret < 0) 56 return ret; 57 58 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev)); 59 } 60 61 static int lnl_hda_dsp_resume(struct snd_sof_dev *sdev) 62 { 63 int ret; 64 65 ret = hda_dsp_resume(sdev); 66 if (ret < 0) 67 return ret; 68 69 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev)); 70 } 71 72 static int lnl_hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 73 { 74 int ret; 75 76 ret = hda_dsp_runtime_resume(sdev); 77 if (ret < 0) 78 return ret; 79 80 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev)); 81 } 82 83 static int lnl_dsp_post_fw_run(struct snd_sof_dev *sdev) 84 { 85 if (sdev->first_boot) { 86 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 87 88 /* Check if IMR boot is usable */ 89 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) { 90 hda->imrboot_supported = true; 91 debugfs_create_bool("skip_imr_boot", 92 0644, sdev->debugfs_root, 93 &hda->skip_imr_boot); 94 } 95 } 96 97 return 0; 98 } 99 100 int sof_lnl_ops_init(struct snd_sof_dev *sdev) 101 { 102 struct sof_ipc4_fw_data *ipc4_data; 103 104 /* common defaults */ 105 memcpy(&sof_lnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 106 107 /* probe */ 108 if (!sdev->dspless_mode_selected) 109 sof_lnl_ops.probe = lnl_hda_dsp_probe; 110 111 /* shutdown */ 112 sof_lnl_ops.shutdown = hda_dsp_shutdown; 113 114 /* doorbell */ 115 sof_lnl_ops.irq_thread = mtl_ipc_irq_thread; 116 117 /* ipc */ 118 sof_lnl_ops.send_msg = mtl_ipc_send_msg; 119 sof_lnl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 120 sof_lnl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 121 122 /* debug */ 123 sof_lnl_ops.debug_map = lnl_dsp_debugfs; 124 sof_lnl_ops.debug_map_count = ARRAY_SIZE(lnl_dsp_debugfs); 125 sof_lnl_ops.dbg_dump = mtl_dsp_dump; 126 sof_lnl_ops.ipc_dump = mtl_ipc_dump; 127 128 /* pre/post fw run */ 129 sof_lnl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 130 sof_lnl_ops.post_fw_run = lnl_dsp_post_fw_run; 131 132 /* parse platform specific extended manifest */ 133 sof_lnl_ops.parse_platform_ext_manifest = NULL; 134 135 /* dsp core get/put */ 136 /* TODO: add core_get and core_put */ 137 138 /* PM */ 139 if (!sdev->dspless_mode_selected) { 140 sof_lnl_ops.resume = lnl_hda_dsp_resume; 141 sof_lnl_ops.runtime_resume = lnl_hda_dsp_runtime_resume; 142 } 143 144 /* dsp core get/put */ 145 sof_lnl_ops.core_get = mtl_dsp_core_get; 146 sof_lnl_ops.core_put = mtl_dsp_core_put; 147 148 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 149 if (!sdev->private) 150 return -ENOMEM; 151 152 ipc4_data = sdev->private; 153 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 154 155 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 156 157 ipc4_data->fw_context_save = true; 158 159 /* External library loading support */ 160 ipc4_data->load_library = hda_dsp_ipc4_load_library; 161 162 /* set DAI ops */ 163 hda_set_dai_drv_ops(sdev, &sof_lnl_ops); 164 165 sof_lnl_ops.set_power_state = hda_dsp_set_power_state_ipc4; 166 167 return 0; 168 }; 169 EXPORT_SYMBOL_NS(sof_lnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 170 171 /* Check if an SDW IRQ occurred */ 172 static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 173 { 174 struct hdac_bus *bus = sof_to_bus(sdev); 175 176 return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 177 } 178 179 static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 180 { 181 struct hdac_bus *bus = sof_to_bus(sdev); 182 183 hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable); 184 } 185 186 static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev) 187 { 188 lnl_enable_sdw_irq(sdev, false); 189 mtl_disable_ipc_interrupts(sdev); 190 return mtl_enable_interrupts(sdev, false); 191 } 192 193 static bool lnl_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 194 { 195 struct hdac_bus *bus = sof_to_bus(sdev); 196 u16 wake_sts; 197 198 /* 199 * we need to use the global HDaudio WAKEEN/STS to be able to 200 * detect wakes in low-power modes. The link-specific information 201 * is handled in the process_wakeen() helper, this helper only 202 * detects a SoundWire wake without identifying the link. 203 */ 204 wake_sts = snd_hdac_chip_readw(bus, STATESTS); 205 206 /* filter out the range of SDIs that can be set for SoundWire */ 207 return wake_sts & GENMASK(SDW_MAX_DEVICES, SDW_INTEL_DEV_NUM_IDA_MIN); 208 } 209 210 const struct sof_intel_dsp_desc lnl_chip_info = { 211 .cores_num = 5, 212 .init_core_mask = BIT(0), 213 .host_managed_cores_mask = BIT(0), 214 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 215 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 216 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 217 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 218 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 219 .rom_status_reg = LNL_DSP_REG_HFDSC, 220 .rom_init_timeout = 300, 221 .ssp_count = MTL_SSP_COUNT, 222 .d0i3_offset = MTL_HDA_VS_D0I3C, 223 .read_sdw_lcount = hda_sdw_check_lcount_ext, 224 .enable_sdw_irq = lnl_enable_sdw_irq, 225 .check_sdw_irq = lnl_dsp_check_sdw_irq, 226 .check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq, 227 .check_ipc_irq = mtl_dsp_check_ipc_irq, 228 .cl_init = mtl_dsp_cl_init, 229 .power_down_dsp = mtl_power_down_dsp, 230 .disable_interrupts = lnl_dsp_disable_interrupts, 231 .hw_ip_version = SOF_INTEL_ACE_2_0, 232 }; 233 EXPORT_SYMBOL_NS(lnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 234