1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2023 Intel Corporation 4 5 /* 6 * Hardware interface for audio DSP on LunarLake. 7 */ 8 9 #include <linux/debugfs.h> 10 #include <linux/firmware.h> 11 #include <sound/hda_register.h> 12 #include <sound/sof/ipc4/header.h> 13 #include <trace/events/sof_intel.h> 14 #include "../ipc4-priv.h" 15 #include "../ops.h" 16 #include "hda.h" 17 #include "hda-ipc.h" 18 #include "../sof-audio.h" 19 #include "mtl.h" 20 #include "lnl.h" 21 #include <sound/hda-mlink.h> 22 23 /* LunarLake ops */ 24 struct snd_sof_dsp_ops sof_lnl_ops; 25 26 static const struct snd_sof_debugfs_map lnl_dsp_debugfs[] = { 27 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 28 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 29 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 30 {"fw_regs", HDA_DSP_BAR, MTL_SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY}, 31 }; 32 33 /* this helps allows the DSP to setup DMIC/SSP */ 34 static int hdac_bus_offload_dmic_ssp(struct hdac_bus *bus, bool enable) 35 { 36 int ret; 37 38 ret = hdac_bus_eml_enable_offload(bus, true, 39 AZX_REG_ML_LEPTR_ID_INTEL_SSP, enable); 40 if (ret < 0) 41 return ret; 42 43 ret = hdac_bus_eml_enable_offload(bus, true, 44 AZX_REG_ML_LEPTR_ID_INTEL_DMIC, enable); 45 if (ret < 0) 46 return ret; 47 48 return 0; 49 } 50 51 static int lnl_hda_dsp_probe(struct snd_sof_dev *sdev) 52 { 53 int ret; 54 55 ret = hda_dsp_probe(sdev); 56 if (ret < 0) 57 return ret; 58 59 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), true); 60 } 61 62 static void lnl_hda_dsp_remove(struct snd_sof_dev *sdev) 63 { 64 int ret; 65 66 ret = hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), false); 67 if (ret < 0) 68 dev_warn(sdev->dev, 69 "Failed to disable offload for DMIC/SSP: %d\n", ret); 70 71 hda_dsp_remove(sdev); 72 } 73 74 static int lnl_hda_dsp_resume(struct snd_sof_dev *sdev) 75 { 76 int ret; 77 78 ret = hda_dsp_resume(sdev); 79 if (ret < 0) 80 return ret; 81 82 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), true); 83 } 84 85 static int lnl_hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 86 { 87 int ret; 88 89 ret = hda_dsp_runtime_resume(sdev); 90 if (ret < 0) 91 return ret; 92 93 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), true); 94 } 95 96 static int lnl_dsp_post_fw_run(struct snd_sof_dev *sdev) 97 { 98 if (sdev->first_boot) { 99 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 100 101 /* Check if IMR boot is usable */ 102 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) { 103 hda->imrboot_supported = true; 104 debugfs_create_bool("skip_imr_boot", 105 0644, sdev->debugfs_root, 106 &hda->skip_imr_boot); 107 } 108 } 109 110 return 0; 111 } 112 113 int sof_lnl_ops_init(struct snd_sof_dev *sdev) 114 { 115 struct sof_ipc4_fw_data *ipc4_data; 116 117 /* common defaults */ 118 memcpy(&sof_lnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 119 120 /* probe/remove */ 121 if (!sdev->dspless_mode_selected) { 122 sof_lnl_ops.probe = lnl_hda_dsp_probe; 123 sof_lnl_ops.remove = lnl_hda_dsp_remove; 124 } 125 126 /* shutdown */ 127 sof_lnl_ops.shutdown = hda_dsp_shutdown; 128 129 /* doorbell */ 130 sof_lnl_ops.irq_thread = mtl_ipc_irq_thread; 131 132 /* ipc */ 133 sof_lnl_ops.send_msg = mtl_ipc_send_msg; 134 sof_lnl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 135 sof_lnl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 136 137 /* debug */ 138 sof_lnl_ops.debug_map = lnl_dsp_debugfs; 139 sof_lnl_ops.debug_map_count = ARRAY_SIZE(lnl_dsp_debugfs); 140 sof_lnl_ops.dbg_dump = mtl_dsp_dump; 141 sof_lnl_ops.ipc_dump = mtl_ipc_dump; 142 143 /* pre/post fw run */ 144 sof_lnl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 145 sof_lnl_ops.post_fw_run = lnl_dsp_post_fw_run; 146 147 /* parse platform specific extended manifest */ 148 sof_lnl_ops.parse_platform_ext_manifest = NULL; 149 150 /* dsp core get/put */ 151 /* TODO: add core_get and core_put */ 152 153 /* PM */ 154 if (!sdev->dspless_mode_selected) { 155 sof_lnl_ops.resume = lnl_hda_dsp_resume; 156 sof_lnl_ops.runtime_resume = lnl_hda_dsp_runtime_resume; 157 } 158 159 /* dsp core get/put */ 160 sof_lnl_ops.core_get = mtl_dsp_core_get; 161 sof_lnl_ops.core_put = mtl_dsp_core_put; 162 163 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 164 if (!sdev->private) 165 return -ENOMEM; 166 167 ipc4_data = sdev->private; 168 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 169 170 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 171 172 ipc4_data->fw_context_save = true; 173 174 /* External library loading support */ 175 ipc4_data->load_library = hda_dsp_ipc4_load_library; 176 177 /* set DAI ops */ 178 hda_set_dai_drv_ops(sdev, &sof_lnl_ops); 179 180 sof_lnl_ops.set_power_state = hda_dsp_set_power_state_ipc4; 181 182 return 0; 183 }; 184 185 /* Check if an SDW IRQ occurred */ 186 static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 187 { 188 struct hdac_bus *bus = sof_to_bus(sdev); 189 190 return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 191 } 192 193 static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 194 { 195 struct hdac_bus *bus = sof_to_bus(sdev); 196 197 hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable); 198 } 199 200 static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev) 201 { 202 lnl_enable_sdw_irq(sdev, false); 203 mtl_disable_ipc_interrupts(sdev); 204 return mtl_enable_interrupts(sdev, false); 205 } 206 207 static bool lnl_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 208 { 209 struct hdac_bus *bus = sof_to_bus(sdev); 210 u16 wake_sts; 211 212 /* 213 * we need to use the global HDaudio WAKEEN/STS to be able to 214 * detect wakes in low-power modes. The link-specific information 215 * is handled in the process_wakeen() helper, this helper only 216 * detects a SoundWire wake without identifying the link. 217 */ 218 wake_sts = snd_hdac_chip_readw(bus, STATESTS); 219 220 /* filter out the range of SDIs that can be set for SoundWire */ 221 return wake_sts & GENMASK(SDW_MAX_DEVICES, SDW_INTEL_DEV_NUM_IDA_MIN); 222 } 223 224 const struct sof_intel_dsp_desc lnl_chip_info = { 225 .cores_num = 5, 226 .init_core_mask = BIT(0), 227 .host_managed_cores_mask = BIT(0), 228 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 229 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 230 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 231 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 232 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 233 .rom_status_reg = LNL_DSP_REG_HFDSC, 234 .rom_init_timeout = 300, 235 .ssp_count = MTL_SSP_COUNT, 236 .d0i3_offset = MTL_HDA_VS_D0I3C, 237 .read_sdw_lcount = hda_sdw_check_lcount_ext, 238 .enable_sdw_irq = lnl_enable_sdw_irq, 239 .check_sdw_irq = lnl_dsp_check_sdw_irq, 240 .check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq, 241 .sdw_process_wakeen = hda_sdw_process_wakeen_common, 242 .check_ipc_irq = mtl_dsp_check_ipc_irq, 243 .cl_init = mtl_dsp_cl_init, 244 .power_down_dsp = mtl_power_down_dsp, 245 .disable_interrupts = lnl_dsp_disable_interrupts, 246 .hw_ip_version = SOF_INTEL_ACE_2_0, 247 }; 248