1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2023 Intel Corporation. All rights reserved. 4 5 /* 6 * Hardware interface for audio DSP on LunarLake. 7 */ 8 9 #include <linux/firmware.h> 10 #include <sound/hda_register.h> 11 #include <sound/sof/ipc4/header.h> 12 #include <trace/events/sof_intel.h> 13 #include "../ipc4-priv.h" 14 #include "../ops.h" 15 #include "hda.h" 16 #include "hda-ipc.h" 17 #include "../sof-audio.h" 18 #include "mtl.h" 19 #include <sound/hda-mlink.h> 20 21 /* LunarLake ops */ 22 struct snd_sof_dsp_ops sof_lnl_ops; 23 EXPORT_SYMBOL_NS(sof_lnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 24 25 static const struct snd_sof_debugfs_map lnl_dsp_debugfs[] = { 26 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 27 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 28 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 29 }; 30 31 /* this helps allows the DSP to setup DMIC/SSP */ 32 static int hdac_bus_offload_dmic_ssp(struct hdac_bus *bus) 33 { 34 int ret; 35 36 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_SSP, true); 37 if (ret < 0) 38 return ret; 39 40 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_DMIC, true); 41 if (ret < 0) 42 return ret; 43 44 return 0; 45 } 46 47 static int lnl_hda_dsp_probe(struct snd_sof_dev *sdev) 48 { 49 int ret; 50 51 ret = hda_dsp_probe(sdev); 52 if (ret < 0) 53 return ret; 54 55 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev)); 56 } 57 58 static int lnl_hda_dsp_resume(struct snd_sof_dev *sdev) 59 { 60 int ret; 61 62 ret = hda_dsp_resume(sdev); 63 if (ret < 0) 64 return ret; 65 66 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev)); 67 } 68 69 static int lnl_hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 70 { 71 int ret; 72 73 ret = hda_dsp_runtime_resume(sdev); 74 if (ret < 0) 75 return ret; 76 77 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev)); 78 } 79 80 int sof_lnl_ops_init(struct snd_sof_dev *sdev) 81 { 82 struct sof_ipc4_fw_data *ipc4_data; 83 84 /* common defaults */ 85 memcpy(&sof_lnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 86 87 /* probe */ 88 sof_lnl_ops.probe = lnl_hda_dsp_probe; 89 90 /* shutdown */ 91 sof_lnl_ops.shutdown = hda_dsp_shutdown; 92 93 /* doorbell */ 94 sof_lnl_ops.irq_thread = mtl_ipc_irq_thread; 95 96 /* ipc */ 97 sof_lnl_ops.send_msg = mtl_ipc_send_msg; 98 sof_lnl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 99 sof_lnl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 100 101 /* debug */ 102 sof_lnl_ops.debug_map = lnl_dsp_debugfs; 103 sof_lnl_ops.debug_map_count = ARRAY_SIZE(lnl_dsp_debugfs); 104 sof_lnl_ops.dbg_dump = mtl_dsp_dump; 105 sof_lnl_ops.ipc_dump = mtl_ipc_dump; 106 107 /* pre/post fw run */ 108 sof_lnl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 109 sof_lnl_ops.post_fw_run = mtl_dsp_post_fw_run; 110 111 /* parse platform specific extended manifest */ 112 sof_lnl_ops.parse_platform_ext_manifest = NULL; 113 114 /* dsp core get/put */ 115 /* TODO: add core_get and core_put */ 116 117 /* PM */ 118 sof_lnl_ops.resume = lnl_hda_dsp_resume; 119 sof_lnl_ops.runtime_resume = lnl_hda_dsp_runtime_resume; 120 121 sof_lnl_ops.get_stream_position = mtl_dsp_get_stream_hda_link_position; 122 123 /* dsp core get/put */ 124 sof_lnl_ops.core_get = mtl_dsp_core_get; 125 sof_lnl_ops.core_put = mtl_dsp_core_put; 126 127 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 128 if (!sdev->private) 129 return -ENOMEM; 130 131 ipc4_data = sdev->private; 132 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 133 134 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 135 136 ipc4_data->fw_context_save = true; 137 138 /* External library loading support */ 139 ipc4_data->load_library = hda_dsp_ipc4_load_library; 140 141 /* set DAI ops */ 142 hda_set_dai_drv_ops(sdev, &sof_lnl_ops); 143 144 sof_lnl_ops.set_power_state = hda_dsp_set_power_state_ipc4; 145 146 return 0; 147 }; 148 EXPORT_SYMBOL_NS(sof_lnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 149 150 /* Check if an SDW IRQ occurred */ 151 static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 152 { 153 struct hdac_bus *bus = sof_to_bus(sdev); 154 155 return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 156 } 157 158 static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 159 { 160 struct hdac_bus *bus = sof_to_bus(sdev); 161 162 hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable); 163 } 164 165 static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev) 166 { 167 lnl_enable_sdw_irq(sdev, false); 168 mtl_disable_ipc_interrupts(sdev); 169 return mtl_enable_interrupts(sdev, false); 170 } 171 172 const struct sof_intel_dsp_desc lnl_chip_info = { 173 .cores_num = 5, 174 .init_core_mask = BIT(0), 175 .host_managed_cores_mask = BIT(0), 176 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 177 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 178 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 179 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 180 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 181 .rom_status_reg = MTL_DSP_ROM_STS, 182 .rom_init_timeout = 300, 183 .ssp_count = MTL_SSP_COUNT, 184 .d0i3_offset = MTL_HDA_VS_D0I3C, 185 .read_sdw_lcount = hda_sdw_check_lcount_ext, 186 .enable_sdw_irq = lnl_enable_sdw_irq, 187 .check_sdw_irq = lnl_dsp_check_sdw_irq, 188 .check_ipc_irq = mtl_dsp_check_ipc_irq, 189 .cl_init = mtl_dsp_cl_init, 190 .power_down_dsp = mtl_power_down_dsp, 191 .disable_interrupts = lnl_dsp_disable_interrupts, 192 .hw_ip_version = SOF_INTEL_ACE_2_0, 193 }; 194 EXPORT_SYMBOL_NS(lnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 195