1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2023 Intel Corporation. All rights reserved. 4 5 /* 6 * Hardware interface for audio DSP on LunarLake. 7 */ 8 9 #include <linux/firmware.h> 10 #include <sound/hda_register.h> 11 #include <sound/sof/ipc4/header.h> 12 #include <trace/events/sof_intel.h> 13 #include "../ipc4-priv.h" 14 #include "../ops.h" 15 #include "hda.h" 16 #include "hda-ipc.h" 17 #include "../sof-audio.h" 18 #include "mtl.h" 19 #include <sound/hda-mlink.h> 20 21 /* LunarLake ops */ 22 struct snd_sof_dsp_ops sof_lnl_ops; 23 EXPORT_SYMBOL_NS(sof_lnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 24 25 static const struct snd_sof_debugfs_map lnl_dsp_debugfs[] = { 26 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 27 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 28 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 29 }; 30 31 /* this helps allows the DSP to setup DMIC/SSP */ 32 static int hdac_bus_offload_dmic_ssp(struct hdac_bus *bus) 33 { 34 int ret; 35 36 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_SSP, true); 37 if (ret < 0) 38 return ret; 39 40 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_DMIC, true); 41 if (ret < 0) 42 return ret; 43 44 return 0; 45 } 46 47 static int lnl_hda_dsp_probe(struct snd_sof_dev *sdev) 48 { 49 int ret; 50 51 ret = hda_dsp_probe(sdev); 52 if (ret < 0) 53 return ret; 54 55 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev)); 56 } 57 58 static int lnl_hda_dsp_resume(struct snd_sof_dev *sdev) 59 { 60 int ret; 61 62 ret = hda_dsp_resume(sdev); 63 if (ret < 0) 64 return ret; 65 66 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev)); 67 } 68 69 static int lnl_hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 70 { 71 int ret; 72 73 ret = hda_dsp_runtime_resume(sdev); 74 if (ret < 0) 75 return ret; 76 77 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev)); 78 } 79 80 static int lnl_dsp_post_fw_run(struct snd_sof_dev *sdev) 81 { 82 if (sdev->first_boot) { 83 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 84 85 /* Check if IMR boot is usable */ 86 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) 87 hda->imrboot_supported = true; 88 } 89 90 return 0; 91 } 92 93 int sof_lnl_ops_init(struct snd_sof_dev *sdev) 94 { 95 struct sof_ipc4_fw_data *ipc4_data; 96 97 /* common defaults */ 98 memcpy(&sof_lnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 99 100 /* probe */ 101 if (!sdev->dspless_mode_selected) 102 sof_lnl_ops.probe = lnl_hda_dsp_probe; 103 104 /* shutdown */ 105 sof_lnl_ops.shutdown = hda_dsp_shutdown; 106 107 /* doorbell */ 108 sof_lnl_ops.irq_thread = mtl_ipc_irq_thread; 109 110 /* ipc */ 111 sof_lnl_ops.send_msg = mtl_ipc_send_msg; 112 sof_lnl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset; 113 sof_lnl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset; 114 115 /* debug */ 116 sof_lnl_ops.debug_map = lnl_dsp_debugfs; 117 sof_lnl_ops.debug_map_count = ARRAY_SIZE(lnl_dsp_debugfs); 118 sof_lnl_ops.dbg_dump = mtl_dsp_dump; 119 sof_lnl_ops.ipc_dump = mtl_ipc_dump; 120 121 /* pre/post fw run */ 122 sof_lnl_ops.pre_fw_run = mtl_dsp_pre_fw_run; 123 sof_lnl_ops.post_fw_run = lnl_dsp_post_fw_run; 124 125 /* parse platform specific extended manifest */ 126 sof_lnl_ops.parse_platform_ext_manifest = NULL; 127 128 /* dsp core get/put */ 129 /* TODO: add core_get and core_put */ 130 131 /* PM */ 132 if (!sdev->dspless_mode_selected) { 133 sof_lnl_ops.resume = lnl_hda_dsp_resume; 134 sof_lnl_ops.runtime_resume = lnl_hda_dsp_runtime_resume; 135 } 136 137 sof_lnl_ops.get_stream_position = mtl_dsp_get_stream_hda_link_position; 138 139 /* dsp core get/put */ 140 sof_lnl_ops.core_get = mtl_dsp_core_get; 141 sof_lnl_ops.core_put = mtl_dsp_core_put; 142 143 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL); 144 if (!sdev->private) 145 return -ENOMEM; 146 147 ipc4_data = sdev->private; 148 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 149 150 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 151 152 ipc4_data->fw_context_save = true; 153 154 /* External library loading support */ 155 ipc4_data->load_library = hda_dsp_ipc4_load_library; 156 157 /* set DAI ops */ 158 hda_set_dai_drv_ops(sdev, &sof_lnl_ops); 159 160 sof_lnl_ops.set_power_state = hda_dsp_set_power_state_ipc4; 161 162 return 0; 163 }; 164 EXPORT_SYMBOL_NS(sof_lnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 165 166 /* Check if an SDW IRQ occurred */ 167 static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 168 { 169 struct hdac_bus *bus = sof_to_bus(sdev); 170 171 return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 172 } 173 174 static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 175 { 176 struct hdac_bus *bus = sof_to_bus(sdev); 177 178 hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable); 179 } 180 181 static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev) 182 { 183 lnl_enable_sdw_irq(sdev, false); 184 mtl_disable_ipc_interrupts(sdev); 185 return mtl_enable_interrupts(sdev, false); 186 } 187 188 const struct sof_intel_dsp_desc lnl_chip_info = { 189 .cores_num = 5, 190 .init_core_mask = BIT(0), 191 .host_managed_cores_mask = BIT(0), 192 .ipc_req = MTL_DSP_REG_HFIPCXIDR, 193 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, 194 .ipc_ack = MTL_DSP_REG_HFIPCXIDA, 195 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, 196 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, 197 .rom_status_reg = MTL_DSP_ROM_STS, 198 .rom_init_timeout = 300, 199 .ssp_count = MTL_SSP_COUNT, 200 .d0i3_offset = MTL_HDA_VS_D0I3C, 201 .read_sdw_lcount = hda_sdw_check_lcount_ext, 202 .enable_sdw_irq = lnl_enable_sdw_irq, 203 .check_sdw_irq = lnl_dsp_check_sdw_irq, 204 .check_ipc_irq = mtl_dsp_check_ipc_irq, 205 .cl_init = mtl_dsp_cl_init, 206 .power_down_dsp = mtl_power_down_dsp, 207 .disable_interrupts = lnl_dsp_disable_interrupts, 208 .hw_ip_version = SOF_INTEL_ACE_2_0, 209 }; 210 EXPORT_SYMBOL_NS(lnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 211