1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright(c) 2020 Intel Corporation 4 // 5 // Author: Fred Oh <fred.oh@linux.intel.com> 6 // 7 8 /* 9 * Hardware interface for audio DSP on IceLake. 10 */ 11 12 #include <linux/array_size.h> 13 #include <linux/bits.h> 14 #include <linux/dev_printk.h> 15 #include <linux/errno.h> 16 #include <linux/slab.h> 17 #include <linux/string.h> 18 #include <linux/types.h> 19 20 #include "../ipc4-priv.h" 21 #include "../ops.h" 22 #include "hda.h" 23 #include "hda-ipc.h" 24 #include "../sof-audio.h" 25 26 #define ICL_DSP_HPRO_CORE_ID 3 27 28 static const struct snd_sof_debugfs_map icl_dsp_debugfs[] = { 29 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 30 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 31 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 32 }; 33 34 static int icl_dsp_core_stall(struct snd_sof_dev *sdev, unsigned int core_mask) 35 { 36 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 37 const struct sof_intel_dsp_desc *chip = hda->desc; 38 39 /* make sure core_mask in host managed cores */ 40 core_mask &= chip->host_managed_cores_mask; 41 if (!core_mask) { 42 dev_err(sdev->dev, "error: core_mask is not in host managed cores\n"); 43 return -EINVAL; 44 } 45 46 /* stall core */ 47 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, 48 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 49 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 50 51 return 0; 52 } 53 54 /* 55 * post fw run operation for ICL. 56 * Core 3 will be powered up and in stall when HPRO is enabled 57 */ 58 static int icl_dsp_post_fw_run(struct snd_sof_dev *sdev) 59 { 60 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 61 int ret; 62 63 if (sdev->first_boot) { 64 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 65 66 ret = hda_sdw_startup(sdev); 67 if (ret < 0) { 68 dev_err(sdev->dev, "error: could not startup SoundWire links\n"); 69 return ret; 70 } 71 72 /* Check if IMR boot is usable */ 73 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) && 74 sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT) 75 hdev->imrboot_supported = true; 76 } 77 78 hda_sdw_int_enable(sdev, true); 79 80 /* 81 * The recommended HW programming sequence for ICL is to 82 * power up core 3 and keep it in stall if HPRO is enabled. 83 */ 84 if (!hda->clk_config_lpro) { 85 ret = hda_dsp_enable_core(sdev, BIT(ICL_DSP_HPRO_CORE_ID)); 86 if (ret < 0) { 87 dev_err(sdev->dev, "error: dsp core power up failed on core %d\n", 88 ICL_DSP_HPRO_CORE_ID); 89 return ret; 90 } 91 92 sdev->enabled_cores_mask |= BIT(ICL_DSP_HPRO_CORE_ID); 93 sdev->dsp_core_ref_count[ICL_DSP_HPRO_CORE_ID]++; 94 95 snd_sof_dsp_stall(sdev, BIT(ICL_DSP_HPRO_CORE_ID)); 96 } 97 98 /* re-enable clock gating and power gating */ 99 return hda_dsp_ctrl_clock_power_gating(sdev, true); 100 } 101 102 /* Icelake ops */ 103 struct snd_sof_dsp_ops sof_icl_ops; 104 105 int sof_icl_ops_init(struct snd_sof_dev *sdev) 106 { 107 /* common defaults */ 108 memcpy(&sof_icl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 109 110 /* probe/remove/shutdown */ 111 sof_icl_ops.shutdown = hda_dsp_shutdown; 112 113 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_3) { 114 /* doorbell */ 115 sof_icl_ops.irq_thread = cnl_ipc_irq_thread; 116 117 /* ipc */ 118 sof_icl_ops.send_msg = cnl_ipc_send_msg; 119 120 /* debug */ 121 sof_icl_ops.ipc_dump = cnl_ipc_dump; 122 123 sof_icl_ops.set_power_state = hda_dsp_set_power_state_ipc3; 124 } 125 126 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) { 127 struct sof_ipc4_fw_data *ipc4_data; 128 129 sdev->private = kzalloc_obj(*ipc4_data); 130 if (!sdev->private) 131 return -ENOMEM; 132 133 ipc4_data = sdev->private; 134 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 135 136 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 137 138 /* External library loading support */ 139 ipc4_data->load_library = hda_dsp_ipc4_load_library; 140 141 /* doorbell */ 142 sof_icl_ops.irq_thread = cnl_ipc4_irq_thread; 143 144 /* ipc */ 145 sof_icl_ops.send_msg = cnl_ipc4_send_msg; 146 147 /* debug */ 148 sof_icl_ops.ipc_dump = cnl_ipc4_dump; 149 150 sof_icl_ops.set_power_state = hda_dsp_set_power_state_ipc4; 151 } 152 153 /* debug */ 154 sof_icl_ops.debug_map = icl_dsp_debugfs; 155 sof_icl_ops.debug_map_count = ARRAY_SIZE(icl_dsp_debugfs); 156 157 /* pre/post fw run */ 158 sof_icl_ops.post_fw_run = icl_dsp_post_fw_run; 159 160 /* firmware run */ 161 sof_icl_ops.run = hda_dsp_cl_boot_firmware_iccmax; 162 sof_icl_ops.stall = icl_dsp_core_stall; 163 164 /* dsp core get/put */ 165 sof_icl_ops.core_get = hda_dsp_core_get; 166 167 /* set DAI driver ops */ 168 hda_set_dai_drv_ops(sdev, &sof_icl_ops); 169 170 return 0; 171 }; 172 173 const struct sof_intel_dsp_desc icl_chip_info = { 174 /* Icelake */ 175 .cores_num = 4, 176 .init_core_mask = 1, 177 .host_managed_cores_mask = GENMASK(3, 0), 178 .ipc_req = CNL_DSP_REG_HIPCIDR, 179 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 180 .ipc_ack = CNL_DSP_REG_HIPCIDA, 181 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 182 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 183 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 184 .rom_init_timeout = 300, 185 .ssp_count = ICL_SSP_COUNT, 186 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 187 .sdw_shim_base = SDW_SHIM_BASE, 188 .sdw_alh_base = SDW_ALH_BASE, 189 .d0i3_offset = SOF_HDA_VS_D0I3C, 190 .read_sdw_lcount = hda_sdw_check_lcount_common, 191 .enable_sdw_irq = hda_common_enable_sdw_irq, 192 .check_sdw_irq = hda_common_check_sdw_irq, 193 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, 194 .sdw_process_wakeen = hda_sdw_process_wakeen_common, 195 .check_ipc_irq = hda_dsp_check_ipc_irq, 196 .cl_init = cl_dsp_init, 197 .power_down_dsp = hda_power_down_dsp, 198 .disable_interrupts = hda_dsp_disable_interrupts, 199 .hw_ip_version = SOF_INTEL_CAVS_2_0, 200 .platform = "icl", 201 }; 202