1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2017 Intel Corporation. All rights reserved. 7 * 8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 */ 10 11 #ifndef __SOF_INTEL_HDA_H 12 #define __SOF_INTEL_HDA_H 13 14 #include <linux/soundwire/sdw.h> 15 #include <linux/soundwire/sdw_intel.h> 16 #include <sound/compress_driver.h> 17 #include <sound/hda_codec.h> 18 #include <sound/hdaudio_ext.h> 19 #include "../sof-client-probes.h" 20 #include "shim.h" 21 22 /* PCI registers */ 23 #define PCI_TCSEL 0x44 24 #define PCI_PGCTL PCI_TCSEL 25 #define PCI_CGCTL 0x48 26 27 /* PCI_PGCTL bits */ 28 #define PCI_PGCTL_ADSPPGD BIT(2) 29 #define PCI_PGCTL_LSRMD_MASK BIT(4) 30 31 /* PCI_CGCTL bits */ 32 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 33 #define PCI_CGCTL_ADSPDCGE BIT(1) 34 35 /* Legacy HDA registers and bits used - widths are variable */ 36 #define SOF_HDA_GCAP 0x0 37 #define SOF_HDA_GCTL 0x8 38 /* accept unsol. response enable */ 39 #define SOF_HDA_GCTL_UNSOL BIT(8) 40 #define SOF_HDA_LLCH 0x14 41 #define SOF_HDA_INTCTL 0x20 42 #define SOF_HDA_INTSTS 0x24 43 #define SOF_HDA_WAKESTS 0x0E 44 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 45 #define SOF_HDA_RIRBSTS 0x5d 46 47 /* SOF_HDA_GCTL register bist */ 48 #define SOF_HDA_GCTL_RESET BIT(0) 49 50 /* SOF_HDA_INCTL regs */ 51 #define SOF_HDA_INT_GLOBAL_EN BIT(31) 52 #define SOF_HDA_INT_CTRL_EN BIT(30) 53 #define SOF_HDA_INT_ALL_STREAM 0xff 54 55 /* SOF_HDA_INTSTS regs */ 56 #define SOF_HDA_INTSTS_GIS BIT(31) 57 58 #define SOF_HDA_MAX_CAPS 10 59 #define SOF_HDA_CAP_ID_OFF 16 60 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 61 SOF_HDA_CAP_ID_OFF) 62 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 63 64 #define SOF_HDA_GTS_CAP_ID 0x1 65 #define SOF_HDA_ML_CAP_ID 0x2 66 67 #define SOF_HDA_PP_CAP_ID 0x3 68 #define SOF_HDA_REG_PP_PPCH 0x10 69 #define SOF_HDA_REG_PP_PPCTL 0x04 70 #define SOF_HDA_REG_PP_PPSTS 0x08 71 #define SOF_HDA_PPCTL_PIE BIT(31) 72 #define SOF_HDA_PPCTL_GPROCEN BIT(30) 73 74 /*Vendor Specific Registers*/ 75 #define SOF_HDA_VS_D0I3C 0x104A 76 77 /* D0I3C Register fields */ 78 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 79 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 80 81 /* DPIB entry size: 8 Bytes = 2 DWords */ 82 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 83 84 #define SOF_HDA_SPIB_CAP_ID 0x4 85 #define SOF_HDA_DRSM_CAP_ID 0x5 86 87 #define SOF_HDA_SPIB_BASE 0x08 88 #define SOF_HDA_SPIB_INTERVAL 0x08 89 #define SOF_HDA_SPIB_SPIB 0x00 90 #define SOF_HDA_SPIB_MAXFIFO 0x04 91 92 #define SOF_HDA_PPHC_BASE 0x10 93 #define SOF_HDA_PPHC_INTERVAL 0x10 94 95 #define SOF_HDA_PPLC_BASE 0x10 96 #define SOF_HDA_PPLC_MULTI 0x10 97 #define SOF_HDA_PPLC_INTERVAL 0x10 98 99 #define SOF_HDA_DRSM_BASE 0x08 100 #define SOF_HDA_DRSM_INTERVAL 0x08 101 102 /* Descriptor error interrupt */ 103 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 104 105 /* FIFO error interrupt */ 106 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 107 108 /* Buffer completion interrupt */ 109 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 110 111 #define SOF_HDA_CL_DMA_SD_INT_MASK \ 112 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 113 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 114 SOF_HDA_CL_DMA_SD_INT_COMPLETE) 115 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 116 117 /* Intel HD Audio Code Loader DMA Registers */ 118 #define SOF_HDA_ADSP_LOADER_BASE 0x80 119 #define SOF_HDA_ADSP_DPLBASE 0x70 120 #define SOF_HDA_ADSP_DPUBASE 0x74 121 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 122 123 /* Stream Registers */ 124 #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 125 #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 126 #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 127 #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 128 #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 129 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 130 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 131 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 132 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 133 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 134 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 135 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 136 137 /* CL: Software Position Based FIFO Capability Registers */ 138 #define SOF_DSP_REG_CL_SPBFIFO \ 139 (SOF_HDA_ADSP_LOADER_BASE + 0x20) 140 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 141 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 142 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 143 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 144 145 /* Stream Number */ 146 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 147 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 148 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 149 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 150 151 #define HDA_DSP_HDA_BAR 0 152 #define HDA_DSP_PP_BAR 1 153 #define HDA_DSP_SPIB_BAR 2 154 #define HDA_DSP_DRSM_BAR 3 155 #define HDA_DSP_BAR 4 156 157 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 158 159 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 160 161 #define HDA_DSP_PANIC_OFFSET(x) \ 162 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 163 164 /* SRAM window 0 FW "registers" */ 165 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 166 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 167 /* FW and ROM share offset 4 */ 168 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 169 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 170 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 171 172 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 173 174 #define HDA_DSP_STREAM_RESET_TIMEOUT 300 175 /* 176 * Timeout in us, for setting the stream RUN bit, during 177 * start/stop the stream. The timeout expires if new RUN bit 178 * value cannot be read back within the specified time. 179 */ 180 #define HDA_DSP_STREAM_RUN_TIMEOUT 300 181 182 #define HDA_DSP_SPIB_ENABLE 1 183 #define HDA_DSP_SPIB_DISABLE 0 184 185 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 186 187 #define HDA_DSP_STACK_DUMP_SIZE 32 188 189 /* ROM status/error values */ 190 #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0) 191 #define HDA_DSP_ROM_INIT 0x1 192 #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3 193 #define HDA_DSP_ROM_FW_FW_LOADED 0x4 194 #define HDA_DSP_ROM_FW_ENTERED 0x5 195 #define HDA_DSP_ROM_RFW_START 0xf 196 #define HDA_DSP_ROM_CSE_ERROR 40 197 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 198 #define HDA_DSP_ROM_IMR_TO_SMALL 42 199 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 200 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 201 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 202 #define HDA_DSP_ROM_L2_CACHE_ERROR 46 203 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 204 #define HDA_DSP_ROM_API_PTR_INVALID 50 205 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 206 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 207 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 208 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 209 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 210 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 211 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 212 #define HDA_DSP_IPC_PURGE_FW 0x01004000 213 214 /* various timeout values */ 215 #define HDA_DSP_PU_TIMEOUT 50 216 #define HDA_DSP_PD_TIMEOUT 50 217 #define HDA_DSP_RESET_TIMEOUT_US 50000 218 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 219 #define HDA_DSP_INIT_TIMEOUT_US 500000 220 #define HDA_DSP_CTRL_RESET_TIMEOUT 100 221 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 222 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 223 #define HDA_DSP_REG_POLL_RETRY_COUNT 50 224 225 #define HDA_DSP_ADSPIC_IPC 1 226 #define HDA_DSP_ADSPIS_IPC 1 227 228 /* Intel HD Audio General DSP Registers */ 229 #define HDA_DSP_GEN_BASE 0x0 230 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 231 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 232 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 233 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 234 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 235 236 #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) 237 238 /* Intel HD Audio Inter-Processor Communication Registers */ 239 #define HDA_DSP_IPC_BASE 0x40 240 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 241 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 242 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 243 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 244 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 245 246 /* Intel Vendor Specific Registers */ 247 #define HDA_VS_INTEL_EM2 0x1030 248 #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 249 #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F 250 251 /* HIPCI */ 252 #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 253 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 254 255 /* HIPCIE */ 256 #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 257 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 258 259 /* HIPCCTL */ 260 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 261 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 262 263 /* HIPCT */ 264 #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 265 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 266 267 /* HIPCTE */ 268 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 269 270 #define HDA_DSP_ADSPIC_CL_DMA 0x2 271 #define HDA_DSP_ADSPIS_CL_DMA 0x2 272 273 /* Delay before scheduling D0i3 entry */ 274 #define BXT_D0I3_DELAY 5000 275 276 #define FW_CL_STREAM_NUMBER 0x1 277 #define HDA_FW_BOOT_ATTEMPTS 3 278 279 /* ADSPCS - Audio DSP Control & Status */ 280 281 /* 282 * Core Reset - asserted high 283 * CRST Mask for a given core mask pattern, cm 284 */ 285 #define HDA_DSP_ADSPCS_CRST_SHIFT 0 286 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 287 288 /* 289 * Core run/stall - when set to '1' core is stalled 290 * CSTALL Mask for a given core mask pattern, cm 291 */ 292 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 293 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 294 295 /* 296 * Set Power Active - when set to '1' turn cores on 297 * SPA Mask for a given core mask pattern, cm 298 */ 299 #define HDA_DSP_ADSPCS_SPA_SHIFT 16 300 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 301 302 /* 303 * Current Power Active - power status of cores, set by hardware 304 * CPA Mask for a given core mask pattern, cm 305 */ 306 #define HDA_DSP_ADSPCS_CPA_SHIFT 24 307 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 308 309 /* 310 * Mask for a given number of cores 311 * nc = number of supported cores 312 */ 313 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 314 315 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 316 #define CNL_DSP_IPC_BASE 0xc0 317 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 318 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 319 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 320 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 321 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 322 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 323 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 324 325 /* HIPCI */ 326 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 327 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 328 329 /* HIPCIE */ 330 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 331 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 332 333 /* HIPCCTL */ 334 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 335 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 336 337 /* HIPCT */ 338 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 339 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 340 341 /* HIPCTDA */ 342 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 343 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 344 345 /* HIPCTDD */ 346 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 347 348 /* BDL */ 349 #define HDA_DSP_BDL_SIZE 4096 350 #define HDA_DSP_MAX_BDL_ENTRIES \ 351 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 352 353 /* Number of DAIs */ 354 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 355 #define SOF_SKL_NUM_DAIS 15 356 #else 357 #define SOF_SKL_NUM_DAIS 8 358 #endif 359 360 /* Intel HD Audio SRAM Window 0*/ 361 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 362 363 /* Firmware status window */ 364 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 365 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 366 367 /* Host Device Memory Space */ 368 #define APL_SSP_BASE_OFFSET 0x2000 369 #define CNL_SSP_BASE_OFFSET 0x10000 370 371 /* Host Device Memory Size of a Single SSP */ 372 #define SSP_DEV_MEM_SIZE 0x1000 373 374 /* SSP Count of the Platform */ 375 #define APL_SSP_COUNT 6 376 #define CNL_SSP_COUNT 3 377 #define ICL_SSP_COUNT 6 378 379 /* SSP Registers */ 380 #define SSP_SSC1_OFFSET 0x4 381 #define SSP_SET_SCLK_CONSUMER BIT(25) 382 #define SSP_SET_SFRM_CONSUMER BIT(24) 383 #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) 384 385 #define HDA_IDISP_ADDR 2 386 #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) 387 388 struct sof_intel_dsp_bdl { 389 __le32 addr_l; 390 __le32 addr_h; 391 __le32 size; 392 __le32 ioc; 393 } __attribute((packed)); 394 395 #define SOF_HDA_PLAYBACK_STREAMS 16 396 #define SOF_HDA_CAPTURE_STREAMS 16 397 #define SOF_HDA_PLAYBACK 0 398 #define SOF_HDA_CAPTURE 1 399 400 /* stream flags */ 401 #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 402 403 /* 404 * Time in ms for opportunistic D0I3 entry delay. 405 * This has been deliberately chosen to be long to avoid race conditions. 406 * Could be optimized in future. 407 */ 408 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 409 410 /* HDA DSP D0 substate */ 411 enum sof_hda_D0_substate { 412 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 413 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 414 }; 415 416 /* represents DSP HDA controller frontend - i.e. host facing control */ 417 struct sof_intel_hda_dev { 418 int boot_iteration; 419 420 struct hda_bus hbus; 421 422 /* hw config */ 423 const struct sof_intel_dsp_desc *desc; 424 425 /* trace */ 426 struct hdac_ext_stream *dtrace_stream; 427 428 /* if position update IPC needed */ 429 u32 no_ipc_position; 430 431 /* the maximum number of streams (playback + capture) supported */ 432 u32 stream_max; 433 434 /* PM related */ 435 bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 436 437 /* DMIC device */ 438 struct platform_device *dmic_dev; 439 440 /* delayed work to enter D0I3 opportunistically */ 441 struct delayed_work d0i3_work; 442 443 /* ACPI information stored between scan and probe steps */ 444 struct sdw_intel_acpi_info info; 445 446 /* sdw context allocated by SoundWire driver */ 447 struct sdw_intel_ctx *sdw; 448 449 /* FW clock config, 0:HPRO, 1:LPRO */ 450 bool clk_config_lpro; 451 }; 452 453 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 454 { 455 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 456 457 return &hda->hbus.core; 458 } 459 460 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 461 { 462 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 463 464 return &hda->hbus; 465 } 466 467 struct sof_intel_hda_stream { 468 struct snd_sof_dev *sdev; 469 struct hdac_ext_stream hext_stream; 470 struct sof_intel_stream sof_intel_stream; 471 int host_reserved; /* reserve host DMA channel */ 472 u32 flags; 473 }; 474 475 #define hstream_to_sof_hda_stream(hstream) \ 476 container_of(hstream, struct sof_intel_hda_stream, hext_stream) 477 478 #define bus_to_sof_hda(bus) \ 479 container_of(bus, struct sof_intel_hda_dev, hbus.core) 480 481 #define SOF_STREAM_SD_OFFSET(s) \ 482 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 483 + SOF_HDA_ADSP_LOADER_BASE) 484 485 #define SOF_STREAM_SD_OFFSET_CRST 0x1 486 487 /* 488 * DSP Core services. 489 */ 490 int hda_dsp_probe(struct snd_sof_dev *sdev); 491 int hda_dsp_remove(struct snd_sof_dev *sdev); 492 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 493 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 494 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 495 unsigned int core_mask); 496 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); 497 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 498 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 499 500 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 501 const struct sof_dsp_power_state *target_state); 502 503 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 504 int hda_dsp_resume(struct snd_sof_dev *sdev); 505 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 506 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 507 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 508 int hda_dsp_shutdown(struct snd_sof_dev *sdev); 509 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 510 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 511 void hda_ipc_dump(struct snd_sof_dev *sdev); 512 void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 513 void hda_dsp_d0i3_work(struct work_struct *work); 514 515 /* 516 * DSP PCM Operations. 517 */ 518 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 519 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 520 int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 521 struct snd_pcm_substream *substream); 522 int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 523 struct snd_pcm_substream *substream); 524 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 525 struct snd_pcm_substream *substream, 526 struct snd_pcm_hw_params *params, 527 struct sof_ipc_stream_params *ipc_params); 528 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 529 struct snd_pcm_substream *substream); 530 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 531 struct snd_pcm_substream *substream, int cmd); 532 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 533 struct snd_pcm_substream *substream); 534 int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 535 536 /* 537 * DSP Stream Operations. 538 */ 539 540 int hda_dsp_stream_init(struct snd_sof_dev *sdev); 541 void hda_dsp_stream_free(struct snd_sof_dev *sdev); 542 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 543 struct hdac_ext_stream *hext_stream, 544 struct snd_dma_buffer *dmab, 545 struct snd_pcm_hw_params *params); 546 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, 547 struct hdac_ext_stream *hext_stream, 548 struct snd_dma_buffer *dmab, 549 struct snd_pcm_hw_params *params); 550 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 551 struct hdac_ext_stream *hext_stream, int cmd); 552 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 553 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 554 struct snd_dma_buffer *dmab, 555 struct hdac_stream *hstream); 556 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 557 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 558 559 struct hdac_ext_stream * 560 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); 561 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 562 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 563 struct hdac_ext_stream *hext_stream, 564 int enable, u32 size); 565 566 int hda_ipc_msg_data(struct snd_sof_dev *sdev, 567 struct snd_pcm_substream *substream, 568 void *p, size_t sz); 569 int hda_ipc_pcm_params(struct snd_sof_dev *sdev, 570 struct snd_pcm_substream *substream, 571 const struct sof_ipc_pcm_params_reply *reply); 572 573 /* 574 * DSP IPC Operations. 575 */ 576 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 577 struct snd_sof_ipc_msg *msg); 578 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 579 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 580 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 581 582 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 583 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 584 585 /* 586 * DSP Code loader. 587 */ 588 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 589 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); 590 591 /* pre and post fw run ops */ 592 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 593 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 594 595 /* parse platform specific ext manifest ops */ 596 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 597 const struct sof_ext_man_elem_header *hdr); 598 599 /* 600 * HDA Controller Operations. 601 */ 602 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 603 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 604 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 605 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 606 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 607 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 608 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 609 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 610 /* 611 * HDA bus operations. 612 */ 613 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 614 615 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 616 /* 617 * HDA Codec operations. 618 */ 619 void hda_codec_probe_bus(struct snd_sof_dev *sdev, 620 bool hda_codec_use_common_hdmi); 621 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); 622 void hda_codec_jack_check(struct snd_sof_dev *sdev); 623 624 #endif /* CONFIG_SND_SOC_SOF_HDA */ 625 626 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 627 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 628 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 629 630 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 631 int hda_codec_i915_init(struct snd_sof_dev *sdev); 632 int hda_codec_i915_exit(struct snd_sof_dev *sdev); 633 634 #else 635 636 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, 637 bool enable) { } 638 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 639 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 640 641 #endif 642 643 /* 644 * Trace Control. 645 */ 646 int hda_dsp_trace_init(struct snd_sof_dev *sdev, 647 struct sof_ipc_dma_trace_params_ext *dtrace_params); 648 int hda_dsp_trace_release(struct snd_sof_dev *sdev); 649 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 650 651 /* 652 * SoundWire support 653 */ 654 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 655 656 int hda_sdw_startup(struct snd_sof_dev *sdev); 657 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); 658 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); 659 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); 660 661 #else 662 663 static inline int hda_sdw_startup(struct snd_sof_dev *sdev) 664 { 665 return 0; 666 } 667 668 static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 669 { 670 } 671 672 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 673 { 674 } 675 676 static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 677 { 678 return false; 679 } 680 681 #endif 682 683 /* common dai driver */ 684 extern struct snd_soc_dai_driver skl_dai[]; 685 686 /* 687 * Platform Specific HW abstraction Ops. 688 */ 689 extern const struct snd_sof_dsp_ops sof_apl_ops; 690 extern const struct snd_sof_dsp_ops sof_cnl_ops; 691 extern const struct snd_sof_dsp_ops sof_tgl_ops; 692 extern const struct snd_sof_dsp_ops sof_icl_ops; 693 694 extern const struct sof_intel_dsp_desc apl_chip_info; 695 extern const struct sof_intel_dsp_desc cnl_chip_info; 696 extern const struct sof_intel_dsp_desc skl_chip_info; 697 extern const struct sof_intel_dsp_desc icl_chip_info; 698 extern const struct sof_intel_dsp_desc tgl_chip_info; 699 extern const struct sof_intel_dsp_desc tglh_chip_info; 700 extern const struct sof_intel_dsp_desc ehl_chip_info; 701 extern const struct sof_intel_dsp_desc jsl_chip_info; 702 extern const struct sof_intel_dsp_desc adls_chip_info; 703 704 /* Probes support */ 705 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 706 int hda_probes_register(struct snd_sof_dev *sdev); 707 void hda_probes_unregister(struct snd_sof_dev *sdev); 708 #else 709 static inline int hda_probes_register(struct snd_sof_dev *sdev) 710 { 711 return 0; 712 } 713 714 static inline void hda_probes_unregister(struct snd_sof_dev *sdev) 715 { 716 } 717 #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ 718 719 /* SOF client registration for HDA platforms */ 720 int hda_register_clients(struct snd_sof_dev *sdev); 721 void hda_unregister_clients(struct snd_sof_dev *sdev); 722 723 /* machine driver select */ 724 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); 725 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 726 struct snd_sof_dev *sdev); 727 728 /* PCI driver selection and probe */ 729 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); 730 731 struct snd_sof_dai; 732 struct sof_ipc_dai_config; 733 int hda_ctrl_dai_widget_setup(struct snd_soc_dapm_widget *w, unsigned int quirk_flags); 734 int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_flags); 735 736 #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ 737 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ 738 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ 739 740 extern int sof_hda_position_quirk; 741 742 #endif 743