1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <sound/hdaudio_ext.h> 19 #include <sound/hda_register.h> 20 21 #include <linux/acpi.h> 22 #include <linux/debugfs.h> 23 #include <linux/module.h> 24 #include <linux/soundwire/sdw.h> 25 #include <linux/soundwire/sdw_intel.h> 26 #include <sound/intel-dsp-config.h> 27 #include <sound/intel-nhlt.h> 28 #include <sound/soc-acpi-intel-ssp-common.h> 29 #include <sound/sof.h> 30 #include <sound/sof/xtensa.h> 31 #include <sound/hda-mlink.h> 32 #include "../sof-audio.h" 33 #include "../sof-pci-dev.h" 34 #include "../ops.h" 35 #include "../ipc4-topology.h" 36 #include "hda.h" 37 #include "telemetry.h" 38 #include "mtl.h" 39 40 #define CREATE_TRACE_POINTS 41 #include <trace/events/sof_intel.h> 42 43 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 44 #include <sound/soc-acpi-intel-match.h> 45 #endif 46 47 /* platform specific devices */ 48 #include "shim.h" 49 50 #define EXCEPT_MAX_HDR_SIZE 0x400 51 #define HDA_EXT_ROM_STATUS_SIZE 8 52 53 static void hda_get_interfaces(struct snd_sof_dev *sdev, u32 *interface_mask) 54 { 55 const struct sof_intel_dsp_desc *chip; 56 57 chip = get_chip_info(sdev->pdata); 58 switch (chip->hw_ip_version) { 59 case SOF_INTEL_TANGIER: 60 case SOF_INTEL_BAYTRAIL: 61 case SOF_INTEL_BROADWELL: 62 interface_mask[SOF_DAI_DSP_ACCESS] = BIT(SOF_DAI_INTEL_SSP); 63 break; 64 case SOF_INTEL_CAVS_1_5: 65 case SOF_INTEL_CAVS_1_5_PLUS: 66 interface_mask[SOF_DAI_DSP_ACCESS] = 67 BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | BIT(SOF_DAI_INTEL_HDA); 68 interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA); 69 break; 70 case SOF_INTEL_CAVS_1_8: 71 case SOF_INTEL_CAVS_2_0: 72 case SOF_INTEL_CAVS_2_5: 73 case SOF_INTEL_ACE_1_0: 74 interface_mask[SOF_DAI_DSP_ACCESS] = 75 BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 76 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 77 interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA); 78 break; 79 case SOF_INTEL_ACE_2_0: 80 interface_mask[SOF_DAI_DSP_ACCESS] = 81 BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 82 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 83 /* all interfaces accessible without DSP */ 84 interface_mask[SOF_DAI_HOST_ACCESS] = 85 interface_mask[SOF_DAI_DSP_ACCESS]; 86 break; 87 default: 88 break; 89 } 90 } 91 92 static u32 hda_get_interface_mask(struct snd_sof_dev *sdev) 93 { 94 u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 }; 95 96 hda_get_interfaces(sdev, interface_mask); 97 98 return interface_mask[sdev->dspless_mode_selected]; 99 } 100 101 bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type) 102 { 103 u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 }; 104 const struct sof_intel_dsp_desc *chip; 105 106 if (sdev->dspless_mode_selected) 107 return false; 108 109 hda_get_interfaces(sdev, interface_mask); 110 111 if (!(interface_mask[SOF_DAI_DSP_ACCESS] & BIT(dai_type))) 112 return false; 113 114 if (dai_type == SOF_DAI_INTEL_HDA) 115 return true; 116 117 switch (dai_type) { 118 case SOF_DAI_INTEL_SSP: 119 case SOF_DAI_INTEL_DMIC: 120 case SOF_DAI_INTEL_ALH: 121 chip = get_chip_info(sdev->pdata); 122 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) 123 return false; 124 return true; 125 default: 126 return false; 127 } 128 } 129 130 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 131 132 /* 133 * The default for SoundWire clock stop quirks is to power gate the IP 134 * and do a Bus Reset, this will need to be modified when the DSP 135 * needs to remain in D0i3 so that the Master does not lose context 136 * and enumeration is not required on clock restart 137 */ 138 static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET; 139 module_param(sdw_clock_stop_quirks, int, 0444); 140 MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks"); 141 142 static int sdw_params_stream(struct device *dev, 143 struct sdw_intel_stream_params_data *params_data) 144 { 145 struct snd_soc_dai *d = params_data->dai; 146 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->substream->stream); 147 struct snd_sof_dai_config_data data = { 0 }; 148 149 data.dai_index = (params_data->link_id << 8) | d->id; 150 data.dai_data = params_data->alh_stream_id; 151 data.dai_node_id = data.dai_data; 152 153 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data); 154 } 155 156 static int sdw_params_free(struct device *dev, struct sdw_intel_stream_free_data *free_data) 157 { 158 struct snd_soc_dai *d = free_data->dai; 159 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, free_data->substream->stream); 160 struct snd_sof_dev *sdev = widget_to_sdev(w); 161 162 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) { 163 struct snd_sof_widget *swidget = w->dobj.private; 164 struct snd_sof_dai *dai = swidget->private; 165 struct sof_ipc4_copier_data *copier_data; 166 struct sof_ipc4_copier *ipc4_copier; 167 168 ipc4_copier = dai->private; 169 ipc4_copier->dai_index = 0; 170 copier_data = &ipc4_copier->data; 171 172 /* clear the node ID */ 173 copier_data->gtw_cfg.node_id &= ~SOF_IPC4_NODE_INDEX_MASK; 174 } 175 176 return 0; 177 } 178 179 struct sdw_intel_ops sdw_callback = { 180 .params_stream = sdw_params_stream, 181 .free_stream = sdw_params_free, 182 }; 183 184 static int sdw_ace2x_params_stream(struct device *dev, 185 struct sdw_intel_stream_params_data *params_data) 186 { 187 return sdw_hda_dai_hw_params(params_data->substream, 188 params_data->hw_params, 189 params_data->dai, 190 params_data->link_id, 191 params_data->alh_stream_id); 192 } 193 194 static int sdw_ace2x_free_stream(struct device *dev, 195 struct sdw_intel_stream_free_data *free_data) 196 { 197 return sdw_hda_dai_hw_free(free_data->substream, 198 free_data->dai, 199 free_data->link_id); 200 } 201 202 static int sdw_ace2x_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) 203 { 204 return sdw_hda_dai_trigger(substream, cmd, dai); 205 } 206 207 static struct sdw_intel_ops sdw_ace2x_callback = { 208 .params_stream = sdw_ace2x_params_stream, 209 .free_stream = sdw_ace2x_free_stream, 210 .trigger = sdw_ace2x_trigger, 211 }; 212 213 void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 214 { 215 struct sof_intel_hda_dev *hdev; 216 217 hdev = sdev->pdata->hw_pdata; 218 219 if (!hdev->sdw) 220 return; 221 222 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2, 223 HDA_DSP_REG_ADSPIC2_SNDW, 224 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0); 225 } 226 227 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 228 { 229 u32 interface_mask = hda_get_interface_mask(sdev); 230 const struct sof_intel_dsp_desc *chip; 231 232 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 233 return; 234 235 chip = get_chip_info(sdev->pdata); 236 if (chip && chip->enable_sdw_irq) 237 chip->enable_sdw_irq(sdev, enable); 238 } 239 240 static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 241 { 242 u32 interface_mask = hda_get_interface_mask(sdev); 243 struct sof_intel_hda_dev *hdev; 244 acpi_handle handle; 245 int ret; 246 247 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 248 return -EINVAL; 249 250 handle = ACPI_HANDLE(sdev->dev); 251 252 /* save ACPI info for the probe step */ 253 hdev = sdev->pdata->hw_pdata; 254 255 ret = sdw_intel_acpi_scan(handle, &hdev->info); 256 if (ret < 0) 257 return -EINVAL; 258 259 return 0; 260 } 261 262 static int hda_sdw_probe(struct snd_sof_dev *sdev) 263 { 264 const struct sof_intel_dsp_desc *chip; 265 struct sof_intel_hda_dev *hdev; 266 struct sdw_intel_res res; 267 void *sdw; 268 269 hdev = sdev->pdata->hw_pdata; 270 271 memset(&res, 0, sizeof(res)); 272 273 chip = get_chip_info(sdev->pdata); 274 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) { 275 res.mmio_base = sdev->bar[HDA_DSP_BAR]; 276 res.hw_ops = &sdw_intel_cnl_hw_ops; 277 res.shim_base = hdev->desc->sdw_shim_base; 278 res.alh_base = hdev->desc->sdw_alh_base; 279 res.ext = false; 280 res.ops = &sdw_callback; 281 } else { 282 /* 283 * retrieve eml_lock needed to protect shared registers 284 * in the HDaudio multi-link areas 285 */ 286 res.eml_lock = hdac_bus_eml_get_mutex(sof_to_bus(sdev), true, 287 AZX_REG_ML_LEPTR_ID_SDW); 288 if (!res.eml_lock) 289 return -ENODEV; 290 291 res.mmio_base = sdev->bar[HDA_DSP_HDA_BAR]; 292 /* 293 * the SHIM and SoundWire register offsets are link-specific 294 * and will be determined when adding auxiliary devices 295 */ 296 res.hw_ops = &sdw_intel_lnl_hw_ops; 297 res.ext = true; 298 res.ops = &sdw_ace2x_callback; 299 300 } 301 res.irq = sdev->ipc_irq; 302 res.handle = hdev->info.handle; 303 res.parent = sdev->dev; 304 305 res.dev = sdev->dev; 306 res.clock_stop_quirks = sdw_clock_stop_quirks; 307 res.hbus = sof_to_bus(sdev); 308 309 /* 310 * ops and arg fields are not populated for now, 311 * they will be needed when the DAI callbacks are 312 * provided 313 */ 314 315 /* we could filter links here if needed, e.g for quirks */ 316 res.count = hdev->info.count; 317 res.link_mask = hdev->info.link_mask; 318 319 sdw = sdw_intel_probe(&res); 320 if (!sdw) { 321 dev_err(sdev->dev, "error: SoundWire probe failed\n"); 322 return -EINVAL; 323 } 324 325 /* save context */ 326 hdev->sdw = sdw; 327 328 return 0; 329 } 330 331 int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 332 { 333 struct sof_intel_hda_dev *hdev; 334 struct sdw_intel_ctx *ctx; 335 u32 caps; 336 337 hdev = sdev->pdata->hw_pdata; 338 ctx = hdev->sdw; 339 340 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); 341 caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 342 343 /* Check HW supported vs property value */ 344 if (caps < ctx->count) { 345 dev_err(sdev->dev, 346 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 347 __func__, ctx->count, caps); 348 return -EINVAL; 349 } 350 351 return 0; 352 } 353 354 int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) 355 { 356 struct sof_intel_hda_dev *hdev; 357 struct sdw_intel_ctx *ctx; 358 struct hdac_bus *bus; 359 u32 slcount; 360 361 bus = sof_to_bus(sdev); 362 363 hdev = sdev->pdata->hw_pdata; 364 ctx = hdev->sdw; 365 366 slcount = hdac_bus_eml_get_count(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 367 368 /* Check HW supported vs property value */ 369 if (slcount < ctx->count) { 370 dev_err(sdev->dev, 371 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 372 __func__, ctx->count, slcount); 373 return -EINVAL; 374 } 375 376 return 0; 377 } 378 379 static int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 380 { 381 const struct sof_intel_dsp_desc *chip; 382 383 chip = get_chip_info(sdev->pdata); 384 if (chip && chip->read_sdw_lcount) 385 return chip->read_sdw_lcount(sdev); 386 387 return 0; 388 } 389 390 int hda_sdw_startup(struct snd_sof_dev *sdev) 391 { 392 struct sof_intel_hda_dev *hdev; 393 struct snd_sof_pdata *pdata = sdev->pdata; 394 int ret; 395 396 hdev = sdev->pdata->hw_pdata; 397 398 if (!hdev->sdw) 399 return 0; 400 401 if (pdata->machine && !pdata->machine->mach_params.link_mask) 402 return 0; 403 404 ret = hda_sdw_check_lcount(sdev); 405 if (ret < 0) 406 return ret; 407 408 return sdw_intel_startup(hdev->sdw); 409 } 410 411 static int hda_sdw_exit(struct snd_sof_dev *sdev) 412 { 413 struct sof_intel_hda_dev *hdev; 414 415 hdev = sdev->pdata->hw_pdata; 416 417 hda_sdw_int_enable(sdev, false); 418 419 if (hdev->sdw) 420 sdw_intel_exit(hdev->sdw); 421 hdev->sdw = NULL; 422 423 return 0; 424 } 425 426 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 427 { 428 struct sof_intel_hda_dev *hdev; 429 bool ret = false; 430 u32 irq_status; 431 432 hdev = sdev->pdata->hw_pdata; 433 434 if (!hdev->sdw) 435 return ret; 436 437 /* store status */ 438 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); 439 440 /* invalid message ? */ 441 if (irq_status == 0xffffffff) 442 goto out; 443 444 /* SDW message ? */ 445 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW) 446 ret = true; 447 448 out: 449 return ret; 450 } 451 452 static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 453 { 454 u32 interface_mask = hda_get_interface_mask(sdev); 455 const struct sof_intel_dsp_desc *chip; 456 457 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 458 return false; 459 460 chip = get_chip_info(sdev->pdata); 461 if (chip && chip->check_sdw_irq) 462 return chip->check_sdw_irq(sdev); 463 464 return false; 465 } 466 467 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 468 { 469 return sdw_intel_thread(irq, context); 470 } 471 472 bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev) 473 { 474 struct sof_intel_hda_dev *hdev; 475 476 hdev = sdev->pdata->hw_pdata; 477 if (hdev->sdw && 478 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 479 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS)) 480 return true; 481 482 return false; 483 } 484 485 static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 486 { 487 u32 interface_mask = hda_get_interface_mask(sdev); 488 const struct sof_intel_dsp_desc *chip; 489 490 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 491 return false; 492 493 chip = get_chip_info(sdev->pdata); 494 if (chip && chip->check_sdw_wakeen_irq) 495 return chip->check_sdw_wakeen_irq(sdev); 496 497 return false; 498 } 499 500 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 501 { 502 u32 interface_mask = hda_get_interface_mask(sdev); 503 struct sof_intel_hda_dev *hdev; 504 505 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 506 return; 507 508 hdev = sdev->pdata->hw_pdata; 509 if (!hdev->sdw) 510 return; 511 512 sdw_intel_process_wakeen_event(hdev->sdw); 513 } 514 515 #else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 516 static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 517 { 518 return 0; 519 } 520 521 static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 522 { 523 return 0; 524 } 525 526 static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 527 { 528 return 0; 529 } 530 531 static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 532 { 533 return false; 534 } 535 536 static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 537 { 538 return IRQ_HANDLED; 539 } 540 541 static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 542 { 543 return false; 544 } 545 546 #endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 547 548 /* 549 * Debug 550 */ 551 552 struct hda_dsp_msg_code { 553 u32 code; 554 const char *text; 555 }; 556 557 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 558 static bool hda_use_msi = true; 559 module_param_named(use_msi, hda_use_msi, bool, 0444); 560 MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode"); 561 #else 562 #define hda_use_msi (1) 563 #endif 564 565 int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 566 module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 567 MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 568 569 static char *hda_model; 570 module_param(hda_model, charp, 0444); 571 MODULE_PARM_DESC(hda_model, "Use the given HDA board model."); 572 573 static int dmic_num_override = -1; 574 module_param_named(dmic_num, dmic_num_override, int, 0444); 575 MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number"); 576 577 static int mclk_id_override = -1; 578 module_param_named(mclk_id, mclk_id_override, int, 0444); 579 MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id"); 580 581 static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { 582 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"}, 583 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"}, 584 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"}, 585 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"}, 586 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"}, 587 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"}, 588 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"}, 589 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"}, 590 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"}, 591 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"}, 592 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"}, 593 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"}, 594 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"}, 595 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"}, 596 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"}, 597 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"}, 598 }; 599 600 #define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} 601 static const struct hda_dsp_msg_code cavs_fsr_rom_state_names[] = { 602 FSR_ROM_STATE_ENTRY(INIT), 603 FSR_ROM_STATE_ENTRY(INIT_DONE), 604 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 605 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 606 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 607 FSR_ROM_STATE_ENTRY(FW_ENTERED), 608 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 609 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 610 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT), 611 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE), 612 /* CSE states */ 613 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST), 614 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED), 615 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST), 616 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED), 617 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT), 618 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1), 619 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY), 620 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL), 621 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), 622 }; 623 624 static const struct hda_dsp_msg_code ace_fsr_rom_state_names[] = { 625 FSR_ROM_STATE_ENTRY(INIT), 626 FSR_ROM_STATE_ENTRY(INIT_DONE), 627 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 628 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 629 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 630 FSR_ROM_STATE_ENTRY(FW_ENTERED), 631 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 632 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 633 FSR_ROM_STATE_ENTRY(RESET_VECTOR_DONE), 634 FSR_ROM_STATE_ENTRY(PURGE_BOOT), 635 FSR_ROM_STATE_ENTRY(RESTORE_BOOT), 636 FSR_ROM_STATE_ENTRY(FW_ENTRY_POINT), 637 FSR_ROM_STATE_ENTRY(VALIDATE_PUB_KEY), 638 FSR_ROM_STATE_ENTRY(POWER_DOWN_HPSRAM), 639 FSR_ROM_STATE_ENTRY(POWER_DOWN_ULPSRAM), 640 FSR_ROM_STATE_ENTRY(POWER_UP_ULPSRAM_STACK), 641 FSR_ROM_STATE_ENTRY(POWER_UP_HPSRAM_DMA), 642 FSR_ROM_STATE_ENTRY(BEFORE_EP_POINTER_READ), 643 FSR_ROM_STATE_ENTRY(VALIDATE_MANIFEST), 644 FSR_ROM_STATE_ENTRY(VALIDATE_FW_MODULE), 645 FSR_ROM_STATE_ENTRY(PROTECT_IMR_REGION), 646 FSR_ROM_STATE_ENTRY(PUSH_MODEL_ROUTINE), 647 FSR_ROM_STATE_ENTRY(PULL_MODEL_ROUTINE), 648 FSR_ROM_STATE_ENTRY(VALIDATE_PKG_DIR), 649 FSR_ROM_STATE_ENTRY(VALIDATE_CPD), 650 FSR_ROM_STATE_ENTRY(VALIDATE_CSS_MAN_HEADER), 651 FSR_ROM_STATE_ENTRY(VALIDATE_BLOB_SVN), 652 FSR_ROM_STATE_ENTRY(VERIFY_IFWI_PARTITION), 653 FSR_ROM_STATE_ENTRY(REMOVE_ACCESS_CONTROL), 654 FSR_ROM_STATE_ENTRY(AUTH_BYPASS), 655 FSR_ROM_STATE_ENTRY(AUTH_ENABLED), 656 FSR_ROM_STATE_ENTRY(INIT_DMA), 657 FSR_ROM_STATE_ENTRY(PURGE_FW_ENTRY), 658 FSR_ROM_STATE_ENTRY(PURGE_FW_END), 659 FSR_ROM_STATE_ENTRY(CLEAN_UP_BSS_DONE), 660 FSR_ROM_STATE_ENTRY(IMR_RESTORE_ENTRY), 661 FSR_ROM_STATE_ENTRY(IMR_RESTORE_END), 662 FSR_ROM_STATE_ENTRY(FW_MANIFEST_IN_DMA_BUFF), 663 FSR_ROM_STATE_ENTRY(LOAD_CSE_MAN_TO_IMR), 664 FSR_ROM_STATE_ENTRY(LOAD_FW_MAN_TO_IMR), 665 FSR_ROM_STATE_ENTRY(LOAD_FW_CODE_TO_IMR), 666 FSR_ROM_STATE_ENTRY(FW_LOADING_DONE), 667 FSR_ROM_STATE_ENTRY(FW_CODE_LOADED), 668 FSR_ROM_STATE_ENTRY(VERIFY_IMAGE_TYPE), 669 FSR_ROM_STATE_ENTRY(AUTH_API_INIT), 670 FSR_ROM_STATE_ENTRY(AUTH_API_PROC), 671 FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_BUSY), 672 FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_RESULT), 673 FSR_ROM_STATE_ENTRY(AUTH_API_CLEANUP), 674 }; 675 676 #define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} 677 static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { 678 FSR_BRINGUP_STATE_ENTRY(INIT), 679 FSR_BRINGUP_STATE_ENTRY(INIT_DONE), 680 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD), 681 FSR_BRINGUP_STATE_ENTRY(UNPACK_START), 682 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE), 683 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED), 684 }; 685 686 #define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state} 687 static const struct hda_dsp_msg_code fsr_wait_state_names[] = { 688 FSR_WAIT_STATE_ENTRY(IPC_BUSY), 689 FSR_WAIT_STATE_ENTRY(IPC_DONE), 690 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION), 691 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF), 692 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL), 693 FSR_WAIT_STATE_ENTRY(CSE_CSR), 694 }; 695 696 #define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod 697 static const char * const fsr_module_names[] = { 698 FSR_MODULE_NAME_ENTRY(ROM), 699 FSR_MODULE_NAME_ENTRY(ROM_BYP), 700 FSR_MODULE_NAME_ENTRY(BASE_FW), 701 FSR_MODULE_NAME_ENTRY(LP_BOOT), 702 FSR_MODULE_NAME_ENTRY(BRNGUP), 703 FSR_MODULE_NAME_ENTRY(ROM_EXT), 704 }; 705 706 static const char * 707 hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, 708 size_t array_size) 709 { 710 int i; 711 712 for (i = 0; i < array_size; i++) { 713 if (code == msg_code[i].code) 714 return msg_code[i].text; 715 } 716 717 return NULL; 718 } 719 720 void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) 721 { 722 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 723 const char *state_text, *error_text, *module_text; 724 u32 fsr, state, wait_state, module, error_code; 725 726 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); 727 state = FSR_TO_STATE_CODE(fsr); 728 wait_state = FSR_TO_WAIT_STATE_CODE(fsr); 729 module = FSR_TO_MODULE_CODE(fsr); 730 731 if (module > FSR_MOD_ROM_EXT) 732 module_text = "unknown"; 733 else 734 module_text = fsr_module_names[module]; 735 736 if (module == FSR_MOD_BRNGUP) { 737 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, 738 ARRAY_SIZE(fsr_bringup_state_names)); 739 } else { 740 if (chip->hw_ip_version < SOF_INTEL_ACE_1_0) 741 state_text = hda_dsp_get_state_text(state, 742 cavs_fsr_rom_state_names, 743 ARRAY_SIZE(cavs_fsr_rom_state_names)); 744 else 745 state_text = hda_dsp_get_state_text(state, 746 ace_fsr_rom_state_names, 747 ARRAY_SIZE(ace_fsr_rom_state_names)); 748 } 749 750 /* not for us, must be generic sof message */ 751 if (!state_text) { 752 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); 753 return; 754 } 755 756 if (wait_state) { 757 const char *wait_state_text; 758 759 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names, 760 ARRAY_SIZE(fsr_wait_state_names)); 761 if (!wait_state_text) 762 wait_state_text = "unknown"; 763 764 dev_printk(level, sdev->dev, 765 "%#010x: module: %s, state: %s, waiting for: %s, %s\n", 766 fsr, module_text, state_text, wait_state_text, 767 fsr & FSR_HALTED ? "not running" : "running"); 768 } else { 769 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", 770 fsr, module_text, state_text, 771 fsr & FSR_HALTED ? "not running" : "running"); 772 } 773 774 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); 775 if (!error_code) 776 return; 777 778 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts, 779 ARRAY_SIZE(hda_dsp_rom_fw_error_texts)); 780 if (!error_text) 781 error_text = "unknown"; 782 783 if (state == FSR_STATE_FW_ENTERED) 784 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, 785 error_text); 786 else 787 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, 788 error_text); 789 } 790 791 static void hda_dsp_get_registers(struct snd_sof_dev *sdev, 792 struct sof_ipc_dsp_oops_xtensa *xoops, 793 struct sof_ipc_panic_info *panic_info, 794 u32 *stack, size_t stack_words) 795 { 796 u32 offset = sdev->dsp_oops_offset; 797 798 /* first read registers */ 799 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 800 801 /* note: variable AR register array is not read */ 802 803 /* then get panic info */ 804 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 805 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 806 xoops->arch_hdr.totalsize); 807 return; 808 } 809 offset += xoops->arch_hdr.totalsize; 810 sof_block_read(sdev, sdev->mmio_bar, offset, 811 panic_info, sizeof(*panic_info)); 812 813 /* then get the stack */ 814 offset += sizeof(*panic_info); 815 sof_block_read(sdev, sdev->mmio_bar, offset, stack, 816 stack_words * sizeof(u32)); 817 } 818 819 /* dump the first 8 dwords representing the extended ROM status */ 820 static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 821 u32 flags) 822 { 823 const struct sof_intel_dsp_desc *chip; 824 char msg[128]; 825 int len = 0; 826 u32 value; 827 int i; 828 829 chip = get_chip_info(sdev->pdata); 830 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) { 831 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); 832 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); 833 } 834 835 dev_printk(level, sdev->dev, "extended rom status: %s", msg); 836 837 } 838 839 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 840 { 841 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 842 struct sof_ipc_dsp_oops_xtensa xoops; 843 struct sof_ipc_panic_info panic_info; 844 u32 stack[HDA_DSP_STACK_DUMP_SIZE]; 845 846 /* print ROM/FW status */ 847 hda_dsp_get_state(sdev, level); 848 849 /* The firmware register dump only available with IPC3 */ 850 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC_TYPE_3) { 851 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS); 852 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP); 853 854 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack, 855 HDA_DSP_STACK_DUMP_SIZE); 856 sof_print_oops_and_stack(sdev, level, status, panic, &xoops, 857 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE); 858 } else { 859 hda_dsp_dump_ext_rom_status(sdev, level, flags); 860 } 861 } 862 863 void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 864 { 865 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 866 867 /* print ROM/FW status */ 868 hda_dsp_get_state(sdev, level); 869 870 if (flags & SOF_DBG_DUMP_REGS) 871 sof_ipc4_intel_dump_telemetry_state(sdev, flags); 872 else 873 hda_dsp_dump_ext_rom_status(sdev, level, flags); 874 } 875 876 static bool hda_check_ipc_irq(struct snd_sof_dev *sdev) 877 { 878 const struct sof_intel_dsp_desc *chip; 879 880 chip = get_chip_info(sdev->pdata); 881 if (chip && chip->check_ipc_irq) 882 return chip->check_ipc_irq(sdev); 883 884 return false; 885 } 886 887 void hda_ipc_irq_dump(struct snd_sof_dev *sdev) 888 { 889 u32 adspis; 890 u32 intsts; 891 u32 intctl; 892 u32 ppsts; 893 u8 rirbsts; 894 895 /* read key IRQ stats and config registers */ 896 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS); 897 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 898 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL); 899 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS); 900 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS); 901 902 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", 903 intsts, intctl, rirbsts); 904 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); 905 } 906 907 void hda_ipc_dump(struct snd_sof_dev *sdev) 908 { 909 u32 hipcie; 910 u32 hipct; 911 u32 hipcctl; 912 913 hda_ipc_irq_dump(sdev); 914 915 /* read IPC status */ 916 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 917 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 918 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 919 920 /* dump the IPC regs */ 921 /* TODO: parse the raw msg */ 922 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 923 hipcie, hipct, hipcctl); 924 } 925 926 void hda_ipc4_dump(struct snd_sof_dev *sdev) 927 { 928 u32 hipci, hipcie, hipct, hipcte, hipcctl; 929 930 hda_ipc_irq_dump(sdev); 931 932 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI); 933 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 934 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 935 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE); 936 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 937 938 /* dump the IPC regs */ 939 /* TODO: parse the raw msg */ 940 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", 941 hipci, hipcie, hipct, hipcte, hipcctl); 942 } 943 944 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev) 945 { 946 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 947 const struct sof_intel_dsp_desc *chip = hda->desc; 948 u32 val; 949 950 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); 951 952 return !!(val & chip->ipc_req_mask); 953 } 954 955 static int hda_init(struct snd_sof_dev *sdev) 956 { 957 struct hda_bus *hbus; 958 struct hdac_bus *bus; 959 struct pci_dev *pci = to_pci_dev(sdev->dev); 960 int ret; 961 962 hbus = sof_to_hbus(sdev); 963 bus = sof_to_bus(sdev); 964 965 /* HDA bus init */ 966 sof_hda_bus_init(sdev, &pci->dev); 967 968 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) 969 bus->use_posbuf = 0; 970 else 971 bus->use_posbuf = 1; 972 bus->bdl_pos_adj = 0; 973 bus->sync_write = 1; 974 975 mutex_init(&hbus->prepare_mutex); 976 hbus->pci = pci; 977 hbus->mixer_assigned = -1; 978 hbus->modelname = hda_model; 979 980 /* initialise hdac bus */ 981 bus->addr = pci_resource_start(pci, 0); 982 bus->remap_addr = pci_ioremap_bar(pci, 0); 983 if (!bus->remap_addr) { 984 dev_err(bus->dev, "error: ioremap error\n"); 985 return -ENXIO; 986 } 987 988 /* HDA base */ 989 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr; 990 991 /* init i915 and HDMI codecs */ 992 ret = hda_codec_i915_init(sdev); 993 if (ret < 0 && ret != -ENODEV) { 994 dev_err_probe(sdev->dev, ret, "init of i915 and HDMI codec failed\n"); 995 goto out; 996 } 997 998 /* get controller capabilities */ 999 ret = hda_dsp_ctrl_get_caps(sdev); 1000 if (ret < 0) { 1001 dev_err(sdev->dev, "error: get caps error\n"); 1002 hda_codec_i915_exit(sdev); 1003 } 1004 1005 out: 1006 if (ret < 0) 1007 iounmap(sof_to_bus(sdev)->remap_addr); 1008 1009 return ret; 1010 } 1011 1012 static int check_dmic_num(struct snd_sof_dev *sdev) 1013 { 1014 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1015 struct nhlt_acpi_table *nhlt; 1016 int dmic_num = 0; 1017 1018 nhlt = hdev->nhlt; 1019 if (nhlt) 1020 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt); 1021 1022 /* allow for module parameter override */ 1023 if (dmic_num_override != -1) { 1024 dev_dbg(sdev->dev, 1025 "overriding DMICs detected in NHLT tables %d by kernel param %d\n", 1026 dmic_num, dmic_num_override); 1027 dmic_num = dmic_num_override; 1028 } 1029 1030 if (dmic_num < 0 || dmic_num > 4) { 1031 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num); 1032 dmic_num = 0; 1033 } 1034 1035 return dmic_num; 1036 } 1037 1038 static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev) 1039 { 1040 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1041 struct nhlt_acpi_table *nhlt; 1042 int ssp_mask = 0; 1043 1044 nhlt = hdev->nhlt; 1045 if (!nhlt) 1046 return ssp_mask; 1047 1048 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) { 1049 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S); 1050 if (ssp_mask) 1051 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask); 1052 } 1053 1054 return ssp_mask; 1055 } 1056 1057 static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num) 1058 { 1059 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1060 struct nhlt_acpi_table *nhlt; 1061 1062 nhlt = hdev->nhlt; 1063 if (!nhlt) 1064 return 0; 1065 1066 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num); 1067 } 1068 1069 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1070 1071 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 1072 const char *sof_tplg_filename, 1073 const char *idisp_str, 1074 const char *dmic_str) 1075 { 1076 const char *tplg_filename = NULL; 1077 char *filename, *tmp; 1078 const char *split_ext; 1079 1080 filename = kstrdup(sof_tplg_filename, GFP_KERNEL); 1081 if (!filename) 1082 return NULL; 1083 1084 /* this assumes a .tplg extension */ 1085 tmp = filename; 1086 split_ext = strsep(&tmp, "."); 1087 if (split_ext) 1088 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1089 "%s%s%s.tplg", 1090 split_ext, idisp_str, dmic_str); 1091 kfree(filename); 1092 1093 return tplg_filename; 1094 } 1095 1096 static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev, 1097 const char **tplg_filename, 1098 const char *idisp_str, 1099 int *dmic_found, 1100 bool tplg_fixup) 1101 { 1102 const char *dmic_str; 1103 int dmic_num; 1104 1105 /* first check for DMICs (using NHLT or module parameter) */ 1106 dmic_num = check_dmic_num(sdev); 1107 1108 switch (dmic_num) { 1109 case 1: 1110 dmic_str = "-1ch"; 1111 break; 1112 case 2: 1113 dmic_str = "-2ch"; 1114 break; 1115 case 3: 1116 dmic_str = "-3ch"; 1117 break; 1118 case 4: 1119 dmic_str = "-4ch"; 1120 break; 1121 default: 1122 dmic_num = 0; 1123 dmic_str = ""; 1124 break; 1125 } 1126 1127 if (tplg_fixup) { 1128 const char *default_tplg_filename = *tplg_filename; 1129 const char *fixed_tplg_filename; 1130 1131 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename, 1132 idisp_str, dmic_str); 1133 if (!fixed_tplg_filename) 1134 return -ENOMEM; 1135 *tplg_filename = fixed_tplg_filename; 1136 } 1137 1138 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num); 1139 *dmic_found = dmic_num; 1140 1141 return 0; 1142 } 1143 #endif 1144 1145 static int hda_init_caps(struct snd_sof_dev *sdev) 1146 { 1147 u32 interface_mask = hda_get_interface_mask(sdev); 1148 struct hdac_bus *bus = sof_to_bus(sdev); 1149 struct snd_sof_pdata *pdata = sdev->pdata; 1150 struct sof_intel_hda_dev *hdev = pdata->hw_pdata; 1151 u32 link_mask; 1152 int ret = 0; 1153 1154 /* check if dsp is there */ 1155 if (bus->ppcap) 1156 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n"); 1157 1158 /* Init HDA controller after i915 init */ 1159 ret = hda_dsp_ctrl_init_chip(sdev); 1160 if (ret < 0) { 1161 dev_err(bus->dev, "error: init chip failed with ret: %d\n", 1162 ret); 1163 return ret; 1164 } 1165 1166 hda_bus_ml_init(bus); 1167 1168 /* Skip SoundWire if it is not supported */ 1169 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1170 goto skip_soundwire; 1171 1172 /* scan SoundWire capabilities exposed by DSDT */ 1173 ret = hda_sdw_acpi_scan(sdev); 1174 if (ret < 0) { 1175 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 1176 goto skip_soundwire; 1177 } 1178 1179 link_mask = hdev->info.link_mask; 1180 if (!link_mask) { 1181 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n"); 1182 goto skip_soundwire; 1183 } 1184 1185 /* 1186 * probe/allocate SoundWire resources. 1187 * The hardware configuration takes place in hda_sdw_startup 1188 * after power rails are enabled. 1189 * It's entirely possible to have a mix of I2S/DMIC/SoundWire 1190 * devices, so we allocate the resources in all cases. 1191 */ 1192 ret = hda_sdw_probe(sdev); 1193 if (ret < 0) { 1194 dev_err(sdev->dev, "error: SoundWire probe error\n"); 1195 return ret; 1196 } 1197 1198 skip_soundwire: 1199 1200 /* create codec instances */ 1201 hda_codec_probe_bus(sdev); 1202 1203 if (!HDA_IDISP_CODEC(bus->codec_mask)) 1204 hda_codec_i915_display_power(sdev, false); 1205 1206 hda_bus_ml_put_all(bus); 1207 1208 return 0; 1209 } 1210 1211 static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context) 1212 { 1213 struct snd_sof_dev *sdev = context; 1214 1215 /* 1216 * Get global interrupt status. It includes all hardware interrupt 1217 * sources in the Intel HD Audio controller. 1218 */ 1219 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) & 1220 SOF_HDA_INTSTS_GIS) { 1221 1222 /* disable GIE interrupt */ 1223 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1224 SOF_HDA_INTCTL, 1225 SOF_HDA_INT_GLOBAL_EN, 1226 0); 1227 1228 return IRQ_WAKE_THREAD; 1229 } 1230 1231 return IRQ_NONE; 1232 } 1233 1234 static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context) 1235 { 1236 struct snd_sof_dev *sdev = context; 1237 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1238 1239 /* deal with streams and controller first */ 1240 if (hda_dsp_check_stream_irq(sdev)) { 1241 trace_sof_intel_hda_irq(sdev, "stream"); 1242 hda_dsp_stream_threaded_handler(irq, sdev); 1243 } 1244 1245 if (hda_check_ipc_irq(sdev)) { 1246 trace_sof_intel_hda_irq(sdev, "ipc"); 1247 sof_ops(sdev)->irq_thread(irq, sdev); 1248 } 1249 1250 if (hda_dsp_check_sdw_irq(sdev)) { 1251 trace_sof_intel_hda_irq(sdev, "sdw"); 1252 hda_dsp_sdw_thread(irq, hdev->sdw); 1253 } 1254 1255 if (hda_sdw_check_wakeen_irq(sdev)) { 1256 trace_sof_intel_hda_irq(sdev, "wakeen"); 1257 hda_sdw_process_wakeen(sdev); 1258 } 1259 1260 hda_codec_check_for_state_change(sdev); 1261 1262 /* enable GIE interrupt */ 1263 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1264 SOF_HDA_INTCTL, 1265 SOF_HDA_INT_GLOBAL_EN, 1266 SOF_HDA_INT_GLOBAL_EN); 1267 1268 return IRQ_HANDLED; 1269 } 1270 1271 int hda_dsp_probe_early(struct snd_sof_dev *sdev) 1272 { 1273 struct pci_dev *pci = to_pci_dev(sdev->dev); 1274 struct sof_intel_hda_dev *hdev; 1275 const struct sof_intel_dsp_desc *chip; 1276 int ret = 0; 1277 1278 if (!sdev->dspless_mode_selected) { 1279 /* 1280 * detect DSP by checking class/subclass/prog-id information 1281 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required 1282 * class=04 subclass 01 prog-if 00: DSP is present 1283 * (and may be required e.g. for DMIC or SSP support) 1284 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works 1285 */ 1286 if (pci->class == 0x040300) { 1287 dev_err(sdev->dev, "the DSP is not enabled on this platform, aborting probe\n"); 1288 return -ENODEV; 1289 } else if (pci->class != 0x040100 && pci->class != 0x040380) { 1290 dev_err(sdev->dev, "unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", 1291 pci->class); 1292 return -ENODEV; 1293 } 1294 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", 1295 pci->class); 1296 } 1297 1298 chip = get_chip_info(sdev->pdata); 1299 if (!chip) { 1300 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n", 1301 pci->device); 1302 ret = -EIO; 1303 goto err; 1304 } 1305 1306 sdev->num_cores = chip->cores_num; 1307 1308 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL); 1309 if (!hdev) 1310 return -ENOMEM; 1311 sdev->pdata->hw_pdata = hdev; 1312 hdev->desc = chip; 1313 ret = hda_init(sdev); 1314 1315 err: 1316 return ret; 1317 } 1318 1319 int hda_dsp_probe(struct snd_sof_dev *sdev) 1320 { 1321 struct pci_dev *pci = to_pci_dev(sdev->dev); 1322 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1323 const struct sof_intel_dsp_desc *chip; 1324 int ret = 0; 1325 1326 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1327 PLATFORM_DEVID_NONE, 1328 NULL, 0); 1329 if (IS_ERR(hdev->dmic_dev)) { 1330 dev_err(sdev->dev, "error: failed to create DMIC device\n"); 1331 return PTR_ERR(hdev->dmic_dev); 1332 } 1333 1334 /* 1335 * use position update IPC if either it is forced 1336 * or we don't have other choice 1337 */ 1338 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION) 1339 hdev->no_ipc_position = 0; 1340 #else 1341 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0; 1342 #endif 1343 1344 if (sdev->dspless_mode_selected) 1345 hdev->no_ipc_position = 1; 1346 1347 if (sdev->dspless_mode_selected) 1348 goto skip_dsp_setup; 1349 1350 /* DSP base */ 1351 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); 1352 if (!sdev->bar[HDA_DSP_BAR]) { 1353 dev_err(sdev->dev, "error: ioremap error\n"); 1354 ret = -ENXIO; 1355 goto hdac_bus_unmap; 1356 } 1357 1358 sdev->mmio_bar = HDA_DSP_BAR; 1359 sdev->mailbox_bar = HDA_DSP_BAR; 1360 skip_dsp_setup: 1361 1362 /* allow 64bit DMA address if supported by H/W */ 1363 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) { 1364 dev_dbg(sdev->dev, "DMA mask is 32 bit\n"); 1365 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1366 } 1367 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1368 1369 /* init streams */ 1370 ret = hda_dsp_stream_init(sdev); 1371 if (ret < 0) { 1372 dev_err(sdev->dev, "error: failed to init streams\n"); 1373 /* 1374 * not all errors are due to memory issues, but trying 1375 * to free everything does not harm 1376 */ 1377 goto free_streams; 1378 } 1379 1380 /* 1381 * register our IRQ 1382 * let's try to enable msi firstly 1383 * if it fails, use legacy interrupt mode 1384 * TODO: support msi multiple vectors 1385 */ 1386 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) { 1387 dev_info(sdev->dev, "use msi interrupt mode\n"); 1388 sdev->ipc_irq = pci_irq_vector(pci, 0); 1389 /* initialised to "false" by kzalloc() */ 1390 sdev->msi_enabled = true; 1391 } 1392 1393 if (!sdev->msi_enabled) { 1394 dev_info(sdev->dev, "use legacy interrupt mode\n"); 1395 /* 1396 * in IO-APIC mode, hda->irq and ipc_irq are using the same 1397 * irq number of pci->irq 1398 */ 1399 sdev->ipc_irq = pci->irq; 1400 } 1401 1402 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq); 1403 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler, 1404 hda_dsp_interrupt_thread, 1405 IRQF_SHARED, "AudioDSP", sdev); 1406 if (ret < 0) { 1407 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n", 1408 sdev->ipc_irq); 1409 goto free_irq_vector; 1410 } 1411 1412 pci_set_master(pci); 1413 synchronize_irq(pci->irq); 1414 1415 /* 1416 * clear TCSEL to clear playback on some HD Audio 1417 * codecs. PCI TCSEL is defined in the Intel manuals. 1418 */ 1419 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 1420 1421 /* init HDA capabilities */ 1422 ret = hda_init_caps(sdev); 1423 if (ret < 0) 1424 goto free_ipc_irq; 1425 1426 if (!sdev->dspless_mode_selected) { 1427 /* enable ppcap interrupt */ 1428 hda_dsp_ctrl_ppcap_enable(sdev, true); 1429 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 1430 1431 /* set default mailbox offset for FW ready message */ 1432 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET; 1433 1434 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work); 1435 } 1436 1437 chip = get_chip_info(sdev->pdata); 1438 if (chip && chip->hw_ip_version >= SOF_INTEL_ACE_2_0) { 1439 ret = hda_sdw_startup(sdev); 1440 if (ret < 0) { 1441 dev_err(sdev->dev, "could not startup SoundWire links\n"); 1442 goto disable_pp_cap; 1443 } 1444 1445 hda_sdw_int_enable(sdev, true); 1446 } 1447 1448 init_waitqueue_head(&hdev->waitq); 1449 1450 hdev->nhlt = intel_nhlt_init(sdev->dev); 1451 1452 return 0; 1453 1454 disable_pp_cap: 1455 if (!sdev->dspless_mode_selected) { 1456 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 1457 hda_dsp_ctrl_ppcap_enable(sdev, false); 1458 } 1459 free_ipc_irq: 1460 free_irq(sdev->ipc_irq, sdev); 1461 free_irq_vector: 1462 if (sdev->msi_enabled) 1463 pci_free_irq_vectors(pci); 1464 free_streams: 1465 hda_dsp_stream_free(sdev); 1466 /* dsp_unmap: not currently used */ 1467 if (!sdev->dspless_mode_selected) 1468 iounmap(sdev->bar[HDA_DSP_BAR]); 1469 hdac_bus_unmap: 1470 platform_device_unregister(hdev->dmic_dev); 1471 1472 return ret; 1473 } 1474 1475 void hda_dsp_remove(struct snd_sof_dev *sdev) 1476 { 1477 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1478 const struct sof_intel_dsp_desc *chip = hda->desc; 1479 struct pci_dev *pci = to_pci_dev(sdev->dev); 1480 struct nhlt_acpi_table *nhlt = hda->nhlt; 1481 1482 if (nhlt) 1483 intel_nhlt_free(nhlt); 1484 1485 if (!sdev->dspless_mode_selected) 1486 /* cancel any attempt for DSP D0I3 */ 1487 cancel_delayed_work_sync(&hda->d0i3_work); 1488 1489 hda_codec_device_remove(sdev); 1490 1491 hda_sdw_exit(sdev); 1492 1493 if (!IS_ERR_OR_NULL(hda->dmic_dev)) 1494 platform_device_unregister(hda->dmic_dev); 1495 1496 if (!sdev->dspless_mode_selected) { 1497 /* disable DSP IRQ */ 1498 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 1499 } 1500 1501 /* disable CIE and GIE interrupts */ 1502 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 1503 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0); 1504 1505 if (sdev->dspless_mode_selected) 1506 goto skip_disable_dsp; 1507 1508 /* no need to check for error as the DSP will be disabled anyway */ 1509 if (chip && chip->power_down_dsp) 1510 chip->power_down_dsp(sdev); 1511 1512 /* disable DSP */ 1513 hda_dsp_ctrl_ppcap_enable(sdev, false); 1514 1515 skip_disable_dsp: 1516 free_irq(sdev->ipc_irq, sdev); 1517 if (sdev->msi_enabled) 1518 pci_free_irq_vectors(pci); 1519 1520 hda_dsp_stream_free(sdev); 1521 1522 hda_bus_ml_free(sof_to_bus(sdev)); 1523 1524 if (!sdev->dspless_mode_selected) 1525 iounmap(sdev->bar[HDA_DSP_BAR]); 1526 } 1527 1528 void hda_dsp_remove_late(struct snd_sof_dev *sdev) 1529 { 1530 iounmap(sof_to_bus(sdev)->remap_addr); 1531 sof_hda_bus_exit(sdev); 1532 hda_codec_i915_exit(sdev); 1533 } 1534 1535 int hda_power_down_dsp(struct snd_sof_dev *sdev) 1536 { 1537 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1538 const struct sof_intel_dsp_desc *chip = hda->desc; 1539 1540 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 1541 } 1542 1543 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 1544 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1545 struct snd_soc_acpi_mach **mach) 1546 { 1547 struct hdac_bus *bus = sof_to_bus(sdev); 1548 struct snd_soc_acpi_mach_params *mach_params; 1549 struct snd_soc_acpi_mach *hda_mach; 1550 struct snd_sof_pdata *pdata = sdev->pdata; 1551 const char *tplg_filename; 1552 const char *idisp_str; 1553 int dmic_num = 0; 1554 int codec_num = 0; 1555 int ret; 1556 int i; 1557 1558 /* codec detection */ 1559 if (!bus->codec_mask) { 1560 dev_info(bus->dev, "no hda codecs found!\n"); 1561 } else { 1562 dev_info(bus->dev, "hda codecs found, mask %lx\n", 1563 bus->codec_mask); 1564 1565 for (i = 0; i < HDA_MAX_CODECS; i++) { 1566 if (bus->codec_mask & (1 << i)) 1567 codec_num++; 1568 } 1569 1570 /* 1571 * If no machine driver is found, then: 1572 * 1573 * generic hda machine driver can handle: 1574 * - one HDMI codec, and/or 1575 * - one external HDAudio codec 1576 */ 1577 if (!*mach && codec_num <= 2) { 1578 bool tplg_fixup; 1579 1580 hda_mach = snd_soc_acpi_intel_hda_machines; 1581 1582 dev_info(bus->dev, "using HDA machine driver %s now\n", 1583 hda_mach->drv_name); 1584 1585 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask)) 1586 idisp_str = "-idisp"; 1587 else 1588 idisp_str = ""; 1589 1590 /* topology: use the info from hda_machines */ 1591 if (pdata->tplg_filename) { 1592 tplg_fixup = false; 1593 tplg_filename = pdata->tplg_filename; 1594 } else { 1595 tplg_fixup = true; 1596 tplg_filename = hda_mach->sof_tplg_filename; 1597 } 1598 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num, 1599 tplg_fixup); 1600 if (ret < 0) 1601 return; 1602 1603 hda_mach->mach_params.dmic_num = dmic_num; 1604 pdata->tplg_filename = tplg_filename; 1605 1606 if (codec_num == 2 || 1607 (codec_num == 1 && !HDA_IDISP_CODEC(bus->codec_mask))) { 1608 /* 1609 * Prevent SoundWire links from starting when an external 1610 * HDaudio codec is used 1611 */ 1612 hda_mach->mach_params.link_mask = 0; 1613 } else { 1614 /* 1615 * Allow SoundWire links to start when no external HDaudio codec 1616 * was detected. This will not create a SoundWire card but 1617 * will help detect if any SoundWire codec reports as ATTACHED. 1618 */ 1619 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1620 1621 hda_mach->mach_params.link_mask = hdev->info.link_mask; 1622 } 1623 1624 *mach = hda_mach; 1625 } 1626 } 1627 1628 /* used by hda machine driver to create dai links */ 1629 if (*mach) { 1630 mach_params = &(*mach)->mach_params; 1631 mach_params->codec_mask = bus->codec_mask; 1632 mach_params->common_hdmi_codec_drv = true; 1633 } 1634 } 1635 #else 1636 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1637 struct snd_soc_acpi_mach **mach) 1638 { 1639 } 1640 #endif 1641 1642 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1643 1644 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1645 { 1646 struct snd_sof_pdata *pdata = sdev->pdata; 1647 const struct snd_soc_acpi_link_adr *link; 1648 struct sdw_extended_slave_id *ids; 1649 struct snd_soc_acpi_mach *mach; 1650 struct sof_intel_hda_dev *hdev; 1651 u32 link_mask; 1652 int i; 1653 1654 hdev = pdata->hw_pdata; 1655 link_mask = hdev->info.link_mask; 1656 1657 if (!link_mask) { 1658 dev_info(sdev->dev, "SoundWire links not enabled\n"); 1659 return NULL; 1660 } 1661 1662 if (!hdev->sdw) { 1663 dev_dbg(sdev->dev, "SoundWire context not allocated\n"); 1664 return NULL; 1665 } 1666 1667 if (!hdev->sdw->num_slaves) { 1668 dev_warn(sdev->dev, "No SoundWire peripheral detected in ACPI tables\n"); 1669 return NULL; 1670 } 1671 1672 /* 1673 * Select SoundWire machine driver if needed using the 1674 * alternate tables. This case deals with SoundWire-only 1675 * machines, for mixed cases with I2C/I2S the detection relies 1676 * on the HID list. 1677 */ 1678 for (mach = pdata->desc->alt_machines; 1679 mach && mach->link_mask; mach++) { 1680 /* 1681 * On some platforms such as Up Extreme all links 1682 * are enabled but only one link can be used by 1683 * external codec. Instead of exact match of two masks, 1684 * first check whether link_mask of mach is subset of 1685 * link_mask supported by hw and then go on searching 1686 * link_adr 1687 */ 1688 if (~link_mask & mach->link_mask) 1689 continue; 1690 1691 /* No need to match adr if there is no links defined */ 1692 if (!mach->links) 1693 break; 1694 1695 link = mach->links; 1696 for (i = 0; i < hdev->info.count && link->num_adr; 1697 i++, link++) { 1698 /* 1699 * Try next machine if any expected Slaves 1700 * are not found on this link. 1701 */ 1702 if (!snd_soc_acpi_sdw_link_slaves_found(sdev->dev, link, 1703 hdev->sdw->ids, 1704 hdev->sdw->num_slaves)) 1705 break; 1706 } 1707 /* Found if all Slaves are checked */ 1708 if (i == hdev->info.count || !link->num_adr) 1709 break; 1710 } 1711 if (mach && mach->link_mask) { 1712 int dmic_num = 0; 1713 bool tplg_fixup; 1714 const char *tplg_filename; 1715 1716 mach->mach_params.links = mach->links; 1717 mach->mach_params.link_mask = mach->link_mask; 1718 mach->mach_params.platform = dev_name(sdev->dev); 1719 1720 if (pdata->tplg_filename) { 1721 tplg_fixup = false; 1722 } else { 1723 tplg_fixup = true; 1724 tplg_filename = mach->sof_tplg_filename; 1725 } 1726 1727 /* 1728 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire 1729 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics 1730 * if all conditions are true: 1731 * a) 2 or fewer links are used by SoundWire 1732 * b) the NHLT table reports the presence of microphones 1733 */ 1734 if (hweight_long(mach->link_mask) <= 2) { 1735 int ret; 1736 1737 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "", 1738 &dmic_num, tplg_fixup); 1739 if (ret < 0) 1740 return NULL; 1741 } 1742 if (tplg_fixup) 1743 pdata->tplg_filename = tplg_filename; 1744 mach->mach_params.dmic_num = dmic_num; 1745 1746 dev_dbg(sdev->dev, 1747 "SoundWire machine driver %s topology %s\n", 1748 mach->drv_name, 1749 pdata->tplg_filename); 1750 1751 return mach; 1752 } 1753 1754 dev_info(sdev->dev, "No SoundWire machine driver found for the ACPI-reported configuration:\n"); 1755 ids = hdev->sdw->ids; 1756 for (i = 0; i < hdev->sdw->num_slaves; i++) 1757 dev_info(sdev->dev, "link %d mfg_id 0x%04x part_id 0x%04x version %#x\n", 1758 ids[i].link_id, ids[i].id.mfg_id, ids[i].id.part_id, ids[i].id.sdw_version); 1759 1760 return NULL; 1761 } 1762 #else 1763 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1764 { 1765 return NULL; 1766 } 1767 #endif 1768 1769 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 1770 struct snd_sof_dev *sdev) 1771 { 1772 struct snd_sof_pdata *pdata = sdev->pdata; 1773 const struct sof_dev_desc *desc = pdata->desc; 1774 struct snd_soc_acpi_mach_params *mach_params; 1775 1776 mach_params = &mach->mach_params; 1777 mach_params->platform = dev_name(sdev->dev); 1778 if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) && 1779 sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC)) 1780 mach_params->num_dai_drivers = SOF_SKL_NUM_DAIS_NOCODEC; 1781 else 1782 mach_params->num_dai_drivers = desc->ops->num_drv; 1783 mach_params->dai_drivers = desc->ops->drv; 1784 } 1785 1786 static int check_tplg_quirk_mask(struct snd_soc_acpi_mach *mach) 1787 { 1788 u32 dmic_ssp_quirk; 1789 u32 codec_amp_name_quirk; 1790 1791 /* 1792 * In current implementation dmic and ssp quirks are designed for es8336 1793 * machine driver and could not be mixed with codec name and amp name 1794 * quirks. 1795 */ 1796 dmic_ssp_quirk = mach->tplg_quirk_mask & 1797 (SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER | SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER); 1798 codec_amp_name_quirk = mach->tplg_quirk_mask & 1799 (SND_SOC_ACPI_TPLG_INTEL_AMP_NAME | SND_SOC_ACPI_TPLG_INTEL_CODEC_NAME); 1800 1801 if (dmic_ssp_quirk && codec_amp_name_quirk) 1802 return -EINVAL; 1803 1804 return 0; 1805 } 1806 1807 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev) 1808 { 1809 u32 interface_mask = hda_get_interface_mask(sdev); 1810 struct snd_sof_pdata *sof_pdata = sdev->pdata; 1811 const struct sof_dev_desc *desc = sof_pdata->desc; 1812 struct snd_soc_acpi_mach *mach = NULL; 1813 enum snd_soc_acpi_intel_codec codec_type; 1814 const char *tplg_filename; 1815 const char *tplg_suffix; 1816 1817 /* Try I2S or DMIC if it is supported */ 1818 if (interface_mask & (BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC))) 1819 mach = snd_soc_acpi_find_machine(desc->machines); 1820 1821 if (mach) { 1822 bool add_extension = false; 1823 bool tplg_fixup = false; 1824 1825 /* 1826 * If tplg file name is overridden, use it instead of 1827 * the one set in mach table 1828 */ 1829 if (!sof_pdata->tplg_filename) { 1830 sof_pdata->tplg_filename = mach->sof_tplg_filename; 1831 tplg_fixup = true; 1832 } 1833 1834 /* 1835 * Checking quirk mask integrity; some quirk flags could not be 1836 * set concurrently. 1837 */ 1838 if (tplg_fixup && 1839 check_tplg_quirk_mask(mach)) { 1840 dev_err(sdev->dev, "Invalid tplg quirk mask 0x%x\n", 1841 mach->tplg_quirk_mask); 1842 return NULL; 1843 } 1844 1845 /* report to machine driver if any DMICs are found */ 1846 mach->mach_params.dmic_num = check_dmic_num(sdev); 1847 1848 if (tplg_fixup && 1849 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER && 1850 mach->mach_params.dmic_num) { 1851 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1852 "%s%s%d%s", 1853 sof_pdata->tplg_filename, 1854 "-dmic", 1855 mach->mach_params.dmic_num, 1856 "ch"); 1857 if (!tplg_filename) 1858 return NULL; 1859 1860 sof_pdata->tplg_filename = tplg_filename; 1861 add_extension = true; 1862 } 1863 1864 if (mach->link_mask) { 1865 mach->mach_params.links = mach->links; 1866 mach->mach_params.link_mask = mach->link_mask; 1867 } 1868 1869 /* report SSP link mask to machine driver */ 1870 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev); 1871 1872 if (tplg_fixup && 1873 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER && 1874 mach->mach_params.i2s_link_mask) { 1875 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 1876 int ssp_num; 1877 int mclk_mask; 1878 1879 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 && 1880 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB)) 1881 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n"); 1882 1883 /* fls returns 1-based results, SSPs indices are 0-based */ 1884 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1; 1885 1886 if (ssp_num >= chip->ssp_count) { 1887 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n", 1888 ssp_num, chip->ssp_count); 1889 return NULL; 1890 } 1891 1892 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1893 "%s%s%d", 1894 sof_pdata->tplg_filename, 1895 "-ssp", 1896 ssp_num); 1897 if (!tplg_filename) 1898 return NULL; 1899 1900 sof_pdata->tplg_filename = tplg_filename; 1901 add_extension = true; 1902 1903 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); 1904 1905 if (mclk_mask < 0) { 1906 dev_err(sdev->dev, "Invalid MCLK configuration\n"); 1907 return NULL; 1908 } 1909 1910 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); 1911 1912 if (mclk_mask) { 1913 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); 1914 sdev->mclk_id_override = true; 1915 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; 1916 } 1917 } 1918 1919 codec_type = snd_soc_acpi_intel_detect_amp_type(sdev->dev); 1920 1921 if (tplg_fixup && 1922 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_AMP_NAME && 1923 codec_type != CODEC_NONE) { 1924 tplg_suffix = snd_soc_acpi_intel_get_amp_tplg_suffix(codec_type); 1925 if (!tplg_suffix) { 1926 dev_err(sdev->dev, "no tplg suffix found, amp %d\n", 1927 codec_type); 1928 return NULL; 1929 } 1930 1931 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1932 "%s-%s", 1933 sof_pdata->tplg_filename, 1934 tplg_suffix); 1935 if (!tplg_filename) 1936 return NULL; 1937 1938 sof_pdata->tplg_filename = tplg_filename; 1939 add_extension = true; 1940 } 1941 1942 codec_type = snd_soc_acpi_intel_detect_codec_type(sdev->dev); 1943 1944 if (tplg_fixup && 1945 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_CODEC_NAME && 1946 codec_type != CODEC_NONE) { 1947 tplg_suffix = snd_soc_acpi_intel_get_codec_tplg_suffix(codec_type); 1948 if (!tplg_suffix) { 1949 dev_err(sdev->dev, "no tplg suffix found, codec %d\n", 1950 codec_type); 1951 return NULL; 1952 } 1953 1954 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1955 "%s-%s", 1956 sof_pdata->tplg_filename, 1957 tplg_suffix); 1958 if (!tplg_filename) 1959 return NULL; 1960 1961 sof_pdata->tplg_filename = tplg_filename; 1962 add_extension = true; 1963 } 1964 1965 if (tplg_fixup && add_extension) { 1966 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1967 "%s%s", 1968 sof_pdata->tplg_filename, 1969 ".tplg"); 1970 if (!tplg_filename) 1971 return NULL; 1972 1973 sof_pdata->tplg_filename = tplg_filename; 1974 } 1975 1976 /* check if mclk_id should be modified from topology defaults */ 1977 if (mclk_id_override >= 0) { 1978 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override); 1979 sdev->mclk_id_override = true; 1980 sdev->mclk_id_quirk = mclk_id_override; 1981 } 1982 } 1983 1984 /* If I2S fails, try SoundWire if it is supported */ 1985 if (!mach && (interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1986 mach = hda_sdw_machine_select(sdev); 1987 1988 /* 1989 * Choose HDA generic machine driver if mach is NULL. 1990 * Otherwise, set certain mach params. 1991 */ 1992 hda_generic_machine_select(sdev, &mach); 1993 if (!mach) 1994 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 1995 1996 return mach; 1997 } 1998 1999 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2000 { 2001 int ret; 2002 2003 ret = snd_intel_dsp_driver_probe(pci); 2004 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 2005 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n"); 2006 return -ENODEV; 2007 } 2008 2009 return sof_pci_probe(pci, pci_id); 2010 } 2011 EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON); 2012 2013 int hda_register_clients(struct snd_sof_dev *sdev) 2014 { 2015 return hda_probes_register(sdev); 2016 } 2017 2018 void hda_unregister_clients(struct snd_sof_dev *sdev) 2019 { 2020 hda_probes_unregister(sdev); 2021 } 2022 2023 MODULE_LICENSE("Dual BSD/GPL"); 2024 MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); 2025 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC); 2026 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915); 2027 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 2028 MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI); 2029 MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT); 2030 MODULE_IMPORT_NS(SOUNDWIRE_INTEL); 2031 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK); 2032 MODULE_IMPORT_NS(SND_SOC_ACPI_INTEL_MATCH); 2033