1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <sound/hdaudio_ext.h> 19 #include <sound/hda_register.h> 20 21 #include <linux/acpi.h> 22 #include <linux/module.h> 23 #include <linux/soundwire/sdw.h> 24 #include <linux/soundwire/sdw_intel.h> 25 #include <sound/intel-dsp-config.h> 26 #include <sound/intel-nhlt.h> 27 #include <sound/sof.h> 28 #include <sound/sof/xtensa.h> 29 #include <sound/hda-mlink.h> 30 #include "../sof-audio.h" 31 #include "../sof-pci-dev.h" 32 #include "../ops.h" 33 #include "hda.h" 34 35 #define CREATE_TRACE_POINTS 36 #include <trace/events/sof_intel.h> 37 38 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 39 #include <sound/soc-acpi-intel-match.h> 40 #endif 41 42 /* platform specific devices */ 43 #include "shim.h" 44 45 #define EXCEPT_MAX_HDR_SIZE 0x400 46 #define HDA_EXT_ROM_STATUS_SIZE 8 47 48 static u32 hda_get_interface_mask(struct snd_sof_dev *sdev) 49 { 50 const struct sof_intel_dsp_desc *chip; 51 u32 interface_mask[2] = { 0 }; 52 53 chip = get_chip_info(sdev->pdata); 54 switch (chip->hw_ip_version) { 55 case SOF_INTEL_TANGIER: 56 case SOF_INTEL_BAYTRAIL: 57 case SOF_INTEL_BROADWELL: 58 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP); 59 break; 60 case SOF_INTEL_CAVS_1_5: 61 case SOF_INTEL_CAVS_1_5_PLUS: 62 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 63 BIT(SOF_DAI_INTEL_HDA); 64 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 65 break; 66 case SOF_INTEL_CAVS_1_8: 67 case SOF_INTEL_CAVS_2_0: 68 case SOF_INTEL_CAVS_2_5: 69 case SOF_INTEL_ACE_1_0: 70 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 71 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 72 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 73 break; 74 default: 75 break; 76 } 77 78 return interface_mask[sdev->dspless_mode_selected]; 79 } 80 81 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 82 83 /* 84 * The default for SoundWire clock stop quirks is to power gate the IP 85 * and do a Bus Reset, this will need to be modified when the DSP 86 * needs to remain in D0i3 so that the Master does not lose context 87 * and enumeration is not required on clock restart 88 */ 89 static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET; 90 module_param(sdw_clock_stop_quirks, int, 0444); 91 MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks"); 92 93 static int sdw_params_stream(struct device *dev, 94 struct sdw_intel_stream_params_data *params_data) 95 { 96 struct snd_soc_dai *d = params_data->dai; 97 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->stream); 98 struct snd_sof_dai_config_data data = { 0 }; 99 100 data.dai_index = (params_data->link_id << 8) | d->id; 101 data.dai_data = params_data->alh_stream_id; 102 103 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data); 104 } 105 106 struct sdw_intel_ops sdw_callback = { 107 .params_stream = sdw_params_stream, 108 }; 109 110 void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 111 { 112 struct sof_intel_hda_dev *hdev; 113 114 hdev = sdev->pdata->hw_pdata; 115 116 if (!hdev->sdw) 117 return; 118 119 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2, 120 HDA_DSP_REG_ADSPIC2_SNDW, 121 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0); 122 } 123 124 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 125 { 126 u32 interface_mask = hda_get_interface_mask(sdev); 127 const struct sof_intel_dsp_desc *chip; 128 129 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 130 return; 131 132 chip = get_chip_info(sdev->pdata); 133 if (chip && chip->enable_sdw_irq) 134 chip->enable_sdw_irq(sdev, enable); 135 } 136 137 static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 138 { 139 u32 interface_mask = hda_get_interface_mask(sdev); 140 struct sof_intel_hda_dev *hdev; 141 acpi_handle handle; 142 int ret; 143 144 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 145 return -EINVAL; 146 147 handle = ACPI_HANDLE(sdev->dev); 148 149 /* save ACPI info for the probe step */ 150 hdev = sdev->pdata->hw_pdata; 151 152 ret = sdw_intel_acpi_scan(handle, &hdev->info); 153 if (ret < 0) 154 return -EINVAL; 155 156 return 0; 157 } 158 159 static int hda_sdw_probe(struct snd_sof_dev *sdev) 160 { 161 struct sof_intel_hda_dev *hdev; 162 struct sdw_intel_res res; 163 void *sdw; 164 165 hdev = sdev->pdata->hw_pdata; 166 167 memset(&res, 0, sizeof(res)); 168 169 res.hw_ops = &sdw_intel_cnl_hw_ops; 170 res.mmio_base = sdev->bar[HDA_DSP_BAR]; 171 res.shim_base = hdev->desc->sdw_shim_base; 172 res.alh_base = hdev->desc->sdw_alh_base; 173 res.irq = sdev->ipc_irq; 174 res.handle = hdev->info.handle; 175 res.parent = sdev->dev; 176 res.ops = &sdw_callback; 177 res.dev = sdev->dev; 178 res.clock_stop_quirks = sdw_clock_stop_quirks; 179 180 /* 181 * ops and arg fields are not populated for now, 182 * they will be needed when the DAI callbacks are 183 * provided 184 */ 185 186 /* we could filter links here if needed, e.g for quirks */ 187 res.count = hdev->info.count; 188 res.link_mask = hdev->info.link_mask; 189 190 sdw = sdw_intel_probe(&res); 191 if (!sdw) { 192 dev_err(sdev->dev, "error: SoundWire probe failed\n"); 193 return -EINVAL; 194 } 195 196 /* save context */ 197 hdev->sdw = sdw; 198 199 return 0; 200 } 201 202 int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 203 { 204 struct sof_intel_hda_dev *hdev; 205 struct sdw_intel_ctx *ctx; 206 u32 caps; 207 208 hdev = sdev->pdata->hw_pdata; 209 ctx = hdev->sdw; 210 211 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); 212 caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 213 214 /* Check HW supported vs property value */ 215 if (caps < ctx->count) { 216 dev_err(sdev->dev, 217 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 218 __func__, ctx->count, caps); 219 return -EINVAL; 220 } 221 222 return 0; 223 } 224 225 static int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 226 { 227 const struct sof_intel_dsp_desc *chip; 228 229 chip = get_chip_info(sdev->pdata); 230 if (chip && chip->read_sdw_lcount) 231 return chip->read_sdw_lcount(sdev); 232 233 return 0; 234 } 235 236 int hda_sdw_startup(struct snd_sof_dev *sdev) 237 { 238 struct sof_intel_hda_dev *hdev; 239 struct snd_sof_pdata *pdata = sdev->pdata; 240 int ret; 241 242 hdev = sdev->pdata->hw_pdata; 243 244 if (!hdev->sdw) 245 return 0; 246 247 if (pdata->machine && !pdata->machine->mach_params.link_mask) 248 return 0; 249 250 ret = hda_sdw_check_lcount(sdev); 251 if (ret < 0) 252 return ret; 253 254 return sdw_intel_startup(hdev->sdw); 255 } 256 257 static int hda_sdw_exit(struct snd_sof_dev *sdev) 258 { 259 struct sof_intel_hda_dev *hdev; 260 261 hdev = sdev->pdata->hw_pdata; 262 263 hda_sdw_int_enable(sdev, false); 264 265 if (hdev->sdw) 266 sdw_intel_exit(hdev->sdw); 267 hdev->sdw = NULL; 268 269 return 0; 270 } 271 272 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 273 { 274 struct sof_intel_hda_dev *hdev; 275 bool ret = false; 276 u32 irq_status; 277 278 hdev = sdev->pdata->hw_pdata; 279 280 if (!hdev->sdw) 281 return ret; 282 283 /* store status */ 284 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); 285 286 /* invalid message ? */ 287 if (irq_status == 0xffffffff) 288 goto out; 289 290 /* SDW message ? */ 291 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW) 292 ret = true; 293 294 out: 295 return ret; 296 } 297 298 static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 299 { 300 u32 interface_mask = hda_get_interface_mask(sdev); 301 const struct sof_intel_dsp_desc *chip; 302 303 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 304 return false; 305 306 chip = get_chip_info(sdev->pdata); 307 if (chip && chip->check_sdw_irq) 308 return chip->check_sdw_irq(sdev); 309 310 return false; 311 } 312 313 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 314 { 315 return sdw_intel_thread(irq, context); 316 } 317 318 static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 319 { 320 u32 interface_mask = hda_get_interface_mask(sdev); 321 struct sof_intel_hda_dev *hdev; 322 323 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 324 return false; 325 326 hdev = sdev->pdata->hw_pdata; 327 if (hdev->sdw && 328 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 329 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS)) 330 return true; 331 332 return false; 333 } 334 335 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 336 { 337 u32 interface_mask = hda_get_interface_mask(sdev); 338 struct sof_intel_hda_dev *hdev; 339 340 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 341 return; 342 343 hdev = sdev->pdata->hw_pdata; 344 if (!hdev->sdw) 345 return; 346 347 sdw_intel_process_wakeen_event(hdev->sdw); 348 } 349 350 #else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 351 static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 352 { 353 return 0; 354 } 355 356 static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 357 { 358 return 0; 359 } 360 361 static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 362 { 363 return 0; 364 } 365 366 static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 367 { 368 return false; 369 } 370 371 static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 372 { 373 return IRQ_HANDLED; 374 } 375 376 static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 377 { 378 return false; 379 } 380 381 #endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 382 383 /* 384 * Debug 385 */ 386 387 struct hda_dsp_msg_code { 388 u32 code; 389 const char *text; 390 }; 391 392 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 393 static bool hda_use_msi = true; 394 module_param_named(use_msi, hda_use_msi, bool, 0444); 395 MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode"); 396 #else 397 #define hda_use_msi (1) 398 #endif 399 400 int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 401 module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 402 MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 403 404 static char *hda_model; 405 module_param(hda_model, charp, 0444); 406 MODULE_PARM_DESC(hda_model, "Use the given HDA board model."); 407 408 static int dmic_num_override = -1; 409 module_param_named(dmic_num, dmic_num_override, int, 0444); 410 MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number"); 411 412 static int mclk_id_override = -1; 413 module_param_named(mclk_id, mclk_id_override, int, 0444); 414 MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id"); 415 416 static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { 417 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"}, 418 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"}, 419 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"}, 420 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"}, 421 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"}, 422 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"}, 423 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"}, 424 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"}, 425 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"}, 426 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"}, 427 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"}, 428 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"}, 429 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"}, 430 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"}, 431 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"}, 432 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"}, 433 }; 434 435 #define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} 436 static const struct hda_dsp_msg_code fsr_rom_state_names[] = { 437 FSR_ROM_STATE_ENTRY(INIT), 438 FSR_ROM_STATE_ENTRY(INIT_DONE), 439 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 440 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 441 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 442 FSR_ROM_STATE_ENTRY(FW_ENTERED), 443 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 444 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 445 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT), 446 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE), 447 /* CSE states */ 448 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST), 449 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED), 450 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST), 451 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED), 452 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT), 453 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1), 454 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY), 455 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL), 456 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), 457 }; 458 459 #define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} 460 static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { 461 FSR_BRINGUP_STATE_ENTRY(INIT), 462 FSR_BRINGUP_STATE_ENTRY(INIT_DONE), 463 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD), 464 FSR_BRINGUP_STATE_ENTRY(UNPACK_START), 465 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE), 466 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED), 467 }; 468 469 #define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state} 470 static const struct hda_dsp_msg_code fsr_wait_state_names[] = { 471 FSR_WAIT_STATE_ENTRY(IPC_BUSY), 472 FSR_WAIT_STATE_ENTRY(IPC_DONE), 473 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION), 474 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF), 475 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL), 476 FSR_WAIT_STATE_ENTRY(CSE_CSR), 477 }; 478 479 #define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod 480 static const char * const fsr_module_names[] = { 481 FSR_MODULE_NAME_ENTRY(ROM), 482 FSR_MODULE_NAME_ENTRY(ROM_BYP), 483 FSR_MODULE_NAME_ENTRY(BASE_FW), 484 FSR_MODULE_NAME_ENTRY(LP_BOOT), 485 FSR_MODULE_NAME_ENTRY(BRNGUP), 486 FSR_MODULE_NAME_ENTRY(ROM_EXT), 487 }; 488 489 static const char * 490 hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, 491 size_t array_size) 492 { 493 int i; 494 495 for (i = 0; i < array_size; i++) { 496 if (code == msg_code[i].code) 497 return msg_code[i].text; 498 } 499 500 return NULL; 501 } 502 503 static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) 504 { 505 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 506 const char *state_text, *error_text, *module_text; 507 u32 fsr, state, wait_state, module, error_code; 508 509 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); 510 state = FSR_TO_STATE_CODE(fsr); 511 wait_state = FSR_TO_WAIT_STATE_CODE(fsr); 512 module = FSR_TO_MODULE_CODE(fsr); 513 514 if (module > FSR_MOD_ROM_EXT) 515 module_text = "unknown"; 516 else 517 module_text = fsr_module_names[module]; 518 519 if (module == FSR_MOD_BRNGUP) 520 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, 521 ARRAY_SIZE(fsr_bringup_state_names)); 522 else 523 state_text = hda_dsp_get_state_text(state, fsr_rom_state_names, 524 ARRAY_SIZE(fsr_rom_state_names)); 525 526 /* not for us, must be generic sof message */ 527 if (!state_text) { 528 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); 529 return; 530 } 531 532 if (wait_state) { 533 const char *wait_state_text; 534 535 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names, 536 ARRAY_SIZE(fsr_wait_state_names)); 537 if (!wait_state_text) 538 wait_state_text = "unknown"; 539 540 dev_printk(level, sdev->dev, 541 "%#010x: module: %s, state: %s, waiting for: %s, %s\n", 542 fsr, module_text, state_text, wait_state_text, 543 fsr & FSR_HALTED ? "not running" : "running"); 544 } else { 545 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", 546 fsr, module_text, state_text, 547 fsr & FSR_HALTED ? "not running" : "running"); 548 } 549 550 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); 551 if (!error_code) 552 return; 553 554 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts, 555 ARRAY_SIZE(hda_dsp_rom_fw_error_texts)); 556 if (!error_text) 557 error_text = "unknown"; 558 559 if (state == FSR_STATE_FW_ENTERED) 560 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, 561 error_text); 562 else 563 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, 564 error_text); 565 } 566 567 static void hda_dsp_get_registers(struct snd_sof_dev *sdev, 568 struct sof_ipc_dsp_oops_xtensa *xoops, 569 struct sof_ipc_panic_info *panic_info, 570 u32 *stack, size_t stack_words) 571 { 572 u32 offset = sdev->dsp_oops_offset; 573 574 /* first read registers */ 575 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 576 577 /* note: variable AR register array is not read */ 578 579 /* then get panic info */ 580 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 581 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 582 xoops->arch_hdr.totalsize); 583 return; 584 } 585 offset += xoops->arch_hdr.totalsize; 586 sof_block_read(sdev, sdev->mmio_bar, offset, 587 panic_info, sizeof(*panic_info)); 588 589 /* then get the stack */ 590 offset += sizeof(*panic_info); 591 sof_block_read(sdev, sdev->mmio_bar, offset, stack, 592 stack_words * sizeof(u32)); 593 } 594 595 /* dump the first 8 dwords representing the extended ROM status */ 596 static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 597 u32 flags) 598 { 599 const struct sof_intel_dsp_desc *chip; 600 char msg[128]; 601 int len = 0; 602 u32 value; 603 int i; 604 605 chip = get_chip_info(sdev->pdata); 606 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) { 607 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); 608 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); 609 } 610 611 dev_printk(level, sdev->dev, "extended rom status: %s", msg); 612 613 } 614 615 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 616 { 617 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 618 struct sof_ipc_dsp_oops_xtensa xoops; 619 struct sof_ipc_panic_info panic_info; 620 u32 stack[HDA_DSP_STACK_DUMP_SIZE]; 621 622 /* print ROM/FW status */ 623 hda_dsp_get_state(sdev, level); 624 625 /* The firmware register dump only available with IPC3 */ 626 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC) { 627 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS); 628 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP); 629 630 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack, 631 HDA_DSP_STACK_DUMP_SIZE); 632 sof_print_oops_and_stack(sdev, level, status, panic, &xoops, 633 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE); 634 } else { 635 hda_dsp_dump_ext_rom_status(sdev, level, flags); 636 } 637 } 638 639 static bool hda_check_ipc_irq(struct snd_sof_dev *sdev) 640 { 641 const struct sof_intel_dsp_desc *chip; 642 643 chip = get_chip_info(sdev->pdata); 644 if (chip && chip->check_ipc_irq) 645 return chip->check_ipc_irq(sdev); 646 647 return false; 648 } 649 650 void hda_ipc_irq_dump(struct snd_sof_dev *sdev) 651 { 652 u32 adspis; 653 u32 intsts; 654 u32 intctl; 655 u32 ppsts; 656 u8 rirbsts; 657 658 /* read key IRQ stats and config registers */ 659 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS); 660 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 661 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL); 662 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS); 663 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS); 664 665 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", 666 intsts, intctl, rirbsts); 667 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); 668 } 669 670 void hda_ipc_dump(struct snd_sof_dev *sdev) 671 { 672 u32 hipcie; 673 u32 hipct; 674 u32 hipcctl; 675 676 hda_ipc_irq_dump(sdev); 677 678 /* read IPC status */ 679 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 680 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 681 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 682 683 /* dump the IPC regs */ 684 /* TODO: parse the raw msg */ 685 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 686 hipcie, hipct, hipcctl); 687 } 688 689 void hda_ipc4_dump(struct snd_sof_dev *sdev) 690 { 691 u32 hipci, hipcie, hipct, hipcte, hipcctl; 692 693 hda_ipc_irq_dump(sdev); 694 695 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI); 696 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 697 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 698 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE); 699 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 700 701 /* dump the IPC regs */ 702 /* TODO: parse the raw msg */ 703 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", 704 hipci, hipcie, hipct, hipcte, hipcctl); 705 } 706 707 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev) 708 { 709 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 710 const struct sof_intel_dsp_desc *chip = hda->desc; 711 u32 val; 712 713 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); 714 715 return !!(val & chip->ipc_req_mask); 716 } 717 718 static int hda_init(struct snd_sof_dev *sdev) 719 { 720 struct hda_bus *hbus; 721 struct hdac_bus *bus; 722 struct pci_dev *pci = to_pci_dev(sdev->dev); 723 int ret; 724 725 hbus = sof_to_hbus(sdev); 726 bus = sof_to_bus(sdev); 727 728 /* HDA bus init */ 729 sof_hda_bus_init(sdev, &pci->dev); 730 731 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) 732 bus->use_posbuf = 0; 733 else 734 bus->use_posbuf = 1; 735 bus->bdl_pos_adj = 0; 736 bus->sync_write = 1; 737 738 mutex_init(&hbus->prepare_mutex); 739 hbus->pci = pci; 740 hbus->mixer_assigned = -1; 741 hbus->modelname = hda_model; 742 743 /* initialise hdac bus */ 744 bus->addr = pci_resource_start(pci, 0); 745 bus->remap_addr = pci_ioremap_bar(pci, 0); 746 if (!bus->remap_addr) { 747 dev_err(bus->dev, "error: ioremap error\n"); 748 return -ENXIO; 749 } 750 751 /* HDA base */ 752 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr; 753 754 /* init i915 and HDMI codecs */ 755 ret = hda_codec_i915_init(sdev); 756 if (ret < 0) 757 dev_warn(sdev->dev, "init of i915 and HDMI codec failed\n"); 758 759 /* get controller capabilities */ 760 ret = hda_dsp_ctrl_get_caps(sdev); 761 if (ret < 0) 762 dev_err(sdev->dev, "error: get caps error\n"); 763 764 return ret; 765 } 766 767 static int check_dmic_num(struct snd_sof_dev *sdev) 768 { 769 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 770 struct nhlt_acpi_table *nhlt; 771 int dmic_num = 0; 772 773 nhlt = hdev->nhlt; 774 if (nhlt) 775 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt); 776 777 /* allow for module parameter override */ 778 if (dmic_num_override != -1) { 779 dev_dbg(sdev->dev, 780 "overriding DMICs detected in NHLT tables %d by kernel param %d\n", 781 dmic_num, dmic_num_override); 782 dmic_num = dmic_num_override; 783 } 784 785 if (dmic_num < 0 || dmic_num > 4) { 786 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num); 787 dmic_num = 0; 788 } 789 790 return dmic_num; 791 } 792 793 static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev) 794 { 795 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 796 struct nhlt_acpi_table *nhlt; 797 int ssp_mask = 0; 798 799 nhlt = hdev->nhlt; 800 if (!nhlt) 801 return ssp_mask; 802 803 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) { 804 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S); 805 if (ssp_mask) 806 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask); 807 } 808 809 return ssp_mask; 810 } 811 812 static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num) 813 { 814 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 815 struct nhlt_acpi_table *nhlt; 816 817 nhlt = hdev->nhlt; 818 if (!nhlt) 819 return 0; 820 821 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num); 822 } 823 824 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 825 826 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 827 const char *sof_tplg_filename, 828 const char *idisp_str, 829 const char *dmic_str) 830 { 831 const char *tplg_filename = NULL; 832 char *filename, *tmp; 833 const char *split_ext; 834 835 filename = kstrdup(sof_tplg_filename, GFP_KERNEL); 836 if (!filename) 837 return NULL; 838 839 /* this assumes a .tplg extension */ 840 tmp = filename; 841 split_ext = strsep(&tmp, "."); 842 if (split_ext) 843 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 844 "%s%s%s.tplg", 845 split_ext, idisp_str, dmic_str); 846 kfree(filename); 847 848 return tplg_filename; 849 } 850 851 static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev, 852 const char **tplg_filename, 853 const char *idisp_str, 854 int *dmic_found, 855 bool tplg_fixup) 856 { 857 const char *dmic_str; 858 int dmic_num; 859 860 /* first check for DMICs (using NHLT or module parameter) */ 861 dmic_num = check_dmic_num(sdev); 862 863 switch (dmic_num) { 864 case 1: 865 dmic_str = "-1ch"; 866 break; 867 case 2: 868 dmic_str = "-2ch"; 869 break; 870 case 3: 871 dmic_str = "-3ch"; 872 break; 873 case 4: 874 dmic_str = "-4ch"; 875 break; 876 default: 877 dmic_num = 0; 878 dmic_str = ""; 879 break; 880 } 881 882 if (tplg_fixup) { 883 const char *default_tplg_filename = *tplg_filename; 884 const char *fixed_tplg_filename; 885 886 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename, 887 idisp_str, dmic_str); 888 if (!fixed_tplg_filename) 889 return -ENOMEM; 890 *tplg_filename = fixed_tplg_filename; 891 } 892 893 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num); 894 *dmic_found = dmic_num; 895 896 return 0; 897 } 898 #endif 899 900 static int hda_init_caps(struct snd_sof_dev *sdev) 901 { 902 u32 interface_mask = hda_get_interface_mask(sdev); 903 struct hdac_bus *bus = sof_to_bus(sdev); 904 struct snd_sof_pdata *pdata = sdev->pdata; 905 struct sof_intel_hda_dev *hdev = pdata->hw_pdata; 906 u32 link_mask; 907 int ret = 0; 908 909 /* check if dsp is there */ 910 if (bus->ppcap) 911 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n"); 912 913 /* Init HDA controller after i915 init */ 914 ret = hda_dsp_ctrl_init_chip(sdev); 915 if (ret < 0) { 916 dev_err(bus->dev, "error: init chip failed with ret: %d\n", 917 ret); 918 return ret; 919 } 920 921 hda_bus_ml_init(bus); 922 923 /* Skip SoundWire if it is not supported */ 924 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 925 goto skip_soundwire; 926 927 /* scan SoundWire capabilities exposed by DSDT */ 928 ret = hda_sdw_acpi_scan(sdev); 929 if (ret < 0) { 930 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 931 goto skip_soundwire; 932 } 933 934 link_mask = hdev->info.link_mask; 935 if (!link_mask) { 936 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n"); 937 goto skip_soundwire; 938 } 939 940 /* 941 * probe/allocate SoundWire resources. 942 * The hardware configuration takes place in hda_sdw_startup 943 * after power rails are enabled. 944 * It's entirely possible to have a mix of I2S/DMIC/SoundWire 945 * devices, so we allocate the resources in all cases. 946 */ 947 ret = hda_sdw_probe(sdev); 948 if (ret < 0) { 949 dev_err(sdev->dev, "error: SoundWire probe error\n"); 950 return ret; 951 } 952 953 skip_soundwire: 954 955 /* create codec instances */ 956 hda_codec_probe_bus(sdev); 957 958 if (!HDA_IDISP_CODEC(bus->codec_mask)) 959 hda_codec_i915_display_power(sdev, false); 960 961 hda_bus_ml_put_all(bus); 962 963 return 0; 964 } 965 966 static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context) 967 { 968 struct snd_sof_dev *sdev = context; 969 970 /* 971 * Get global interrupt status. It includes all hardware interrupt 972 * sources in the Intel HD Audio controller. 973 */ 974 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) & 975 SOF_HDA_INTSTS_GIS) { 976 977 /* disable GIE interrupt */ 978 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 979 SOF_HDA_INTCTL, 980 SOF_HDA_INT_GLOBAL_EN, 981 0); 982 983 return IRQ_WAKE_THREAD; 984 } 985 986 return IRQ_NONE; 987 } 988 989 static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context) 990 { 991 struct snd_sof_dev *sdev = context; 992 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 993 994 /* deal with streams and controller first */ 995 if (hda_dsp_check_stream_irq(sdev)) { 996 trace_sof_intel_hda_irq(sdev, "stream"); 997 hda_dsp_stream_threaded_handler(irq, sdev); 998 } 999 1000 if (hda_check_ipc_irq(sdev)) { 1001 trace_sof_intel_hda_irq(sdev, "ipc"); 1002 sof_ops(sdev)->irq_thread(irq, sdev); 1003 } 1004 1005 if (hda_dsp_check_sdw_irq(sdev)) { 1006 trace_sof_intel_hda_irq(sdev, "sdw"); 1007 hda_dsp_sdw_thread(irq, hdev->sdw); 1008 } 1009 1010 if (hda_sdw_check_wakeen_irq(sdev)) { 1011 trace_sof_intel_hda_irq(sdev, "wakeen"); 1012 hda_sdw_process_wakeen(sdev); 1013 } 1014 1015 hda_codec_check_for_state_change(sdev); 1016 1017 /* enable GIE interrupt */ 1018 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1019 SOF_HDA_INTCTL, 1020 SOF_HDA_INT_GLOBAL_EN, 1021 SOF_HDA_INT_GLOBAL_EN); 1022 1023 return IRQ_HANDLED; 1024 } 1025 1026 int hda_dsp_probe(struct snd_sof_dev *sdev) 1027 { 1028 struct pci_dev *pci = to_pci_dev(sdev->dev); 1029 struct sof_intel_hda_dev *hdev; 1030 struct hdac_bus *bus; 1031 const struct sof_intel_dsp_desc *chip; 1032 int ret = 0; 1033 1034 if (!sdev->dspless_mode_selected) { 1035 /* 1036 * detect DSP by checking class/subclass/prog-id information 1037 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required 1038 * class=04 subclass 01 prog-if 00: DSP is present 1039 * (and may be required e.g. for DMIC or SSP support) 1040 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works 1041 */ 1042 if (pci->class == 0x040300) { 1043 dev_err(sdev->dev, "the DSP is not enabled on this platform, aborting probe\n"); 1044 return -ENODEV; 1045 } else if (pci->class != 0x040100 && pci->class != 0x040380) { 1046 dev_err(sdev->dev, "unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", 1047 pci->class); 1048 return -ENODEV; 1049 } 1050 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", 1051 pci->class); 1052 } 1053 1054 chip = get_chip_info(sdev->pdata); 1055 if (!chip) { 1056 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n", 1057 pci->device); 1058 ret = -EIO; 1059 goto err; 1060 } 1061 1062 sdev->num_cores = chip->cores_num; 1063 1064 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL); 1065 if (!hdev) 1066 return -ENOMEM; 1067 sdev->pdata->hw_pdata = hdev; 1068 hdev->desc = chip; 1069 1070 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1071 PLATFORM_DEVID_NONE, 1072 NULL, 0); 1073 if (IS_ERR(hdev->dmic_dev)) { 1074 dev_err(sdev->dev, "error: failed to create DMIC device\n"); 1075 return PTR_ERR(hdev->dmic_dev); 1076 } 1077 1078 /* 1079 * use position update IPC if either it is forced 1080 * or we don't have other choice 1081 */ 1082 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION) 1083 hdev->no_ipc_position = 0; 1084 #else 1085 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0; 1086 #endif 1087 1088 if (sdev->dspless_mode_selected) 1089 hdev->no_ipc_position = 1; 1090 1091 /* set up HDA base */ 1092 bus = sof_to_bus(sdev); 1093 ret = hda_init(sdev); 1094 if (ret < 0) 1095 goto hdac_bus_unmap; 1096 1097 if (sdev->dspless_mode_selected) 1098 goto skip_dsp_setup; 1099 1100 /* DSP base */ 1101 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); 1102 if (!sdev->bar[HDA_DSP_BAR]) { 1103 dev_err(sdev->dev, "error: ioremap error\n"); 1104 ret = -ENXIO; 1105 goto hdac_bus_unmap; 1106 } 1107 1108 sdev->mmio_bar = HDA_DSP_BAR; 1109 sdev->mailbox_bar = HDA_DSP_BAR; 1110 skip_dsp_setup: 1111 1112 /* allow 64bit DMA address if supported by H/W */ 1113 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) { 1114 dev_dbg(sdev->dev, "DMA mask is 32 bit\n"); 1115 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1116 } 1117 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1118 1119 /* init streams */ 1120 ret = hda_dsp_stream_init(sdev); 1121 if (ret < 0) { 1122 dev_err(sdev->dev, "error: failed to init streams\n"); 1123 /* 1124 * not all errors are due to memory issues, but trying 1125 * to free everything does not harm 1126 */ 1127 goto free_streams; 1128 } 1129 1130 /* 1131 * register our IRQ 1132 * let's try to enable msi firstly 1133 * if it fails, use legacy interrupt mode 1134 * TODO: support msi multiple vectors 1135 */ 1136 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) { 1137 dev_info(sdev->dev, "use msi interrupt mode\n"); 1138 sdev->ipc_irq = pci_irq_vector(pci, 0); 1139 /* initialised to "false" by kzalloc() */ 1140 sdev->msi_enabled = true; 1141 } 1142 1143 if (!sdev->msi_enabled) { 1144 dev_info(sdev->dev, "use legacy interrupt mode\n"); 1145 /* 1146 * in IO-APIC mode, hda->irq and ipc_irq are using the same 1147 * irq number of pci->irq 1148 */ 1149 sdev->ipc_irq = pci->irq; 1150 } 1151 1152 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq); 1153 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler, 1154 hda_dsp_interrupt_thread, 1155 IRQF_SHARED, "AudioDSP", sdev); 1156 if (ret < 0) { 1157 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n", 1158 sdev->ipc_irq); 1159 goto free_irq_vector; 1160 } 1161 1162 pci_set_master(pci); 1163 synchronize_irq(pci->irq); 1164 1165 /* 1166 * clear TCSEL to clear playback on some HD Audio 1167 * codecs. PCI TCSEL is defined in the Intel manuals. 1168 */ 1169 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 1170 1171 /* init HDA capabilities */ 1172 ret = hda_init_caps(sdev); 1173 if (ret < 0) 1174 goto free_ipc_irq; 1175 1176 if (!sdev->dspless_mode_selected) { 1177 /* enable ppcap interrupt */ 1178 hda_dsp_ctrl_ppcap_enable(sdev, true); 1179 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 1180 1181 /* set default mailbox offset for FW ready message */ 1182 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET; 1183 1184 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work); 1185 } 1186 1187 init_waitqueue_head(&hdev->waitq); 1188 1189 hdev->nhlt = intel_nhlt_init(sdev->dev); 1190 1191 return 0; 1192 1193 free_ipc_irq: 1194 free_irq(sdev->ipc_irq, sdev); 1195 free_irq_vector: 1196 if (sdev->msi_enabled) 1197 pci_free_irq_vectors(pci); 1198 free_streams: 1199 hda_dsp_stream_free(sdev); 1200 /* dsp_unmap: not currently used */ 1201 if (!sdev->dspless_mode_selected) 1202 iounmap(sdev->bar[HDA_DSP_BAR]); 1203 hdac_bus_unmap: 1204 platform_device_unregister(hdev->dmic_dev); 1205 iounmap(bus->remap_addr); 1206 hda_codec_i915_exit(sdev); 1207 err: 1208 return ret; 1209 } 1210 1211 int hda_dsp_remove(struct snd_sof_dev *sdev) 1212 { 1213 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1214 const struct sof_intel_dsp_desc *chip = hda->desc; 1215 struct hdac_bus *bus = sof_to_bus(sdev); 1216 struct pci_dev *pci = to_pci_dev(sdev->dev); 1217 struct nhlt_acpi_table *nhlt = hda->nhlt; 1218 1219 if (nhlt) 1220 intel_nhlt_free(nhlt); 1221 1222 if (!sdev->dspless_mode_selected) 1223 /* cancel any attempt for DSP D0I3 */ 1224 cancel_delayed_work_sync(&hda->d0i3_work); 1225 1226 hda_codec_device_remove(sdev); 1227 1228 hda_sdw_exit(sdev); 1229 1230 if (!IS_ERR_OR_NULL(hda->dmic_dev)) 1231 platform_device_unregister(hda->dmic_dev); 1232 1233 if (!sdev->dspless_mode_selected) { 1234 /* disable DSP IRQ */ 1235 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1236 SOF_HDA_PPCTL_PIE, 0); 1237 } 1238 1239 /* disable CIE and GIE interrupts */ 1240 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 1241 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0); 1242 1243 if (sdev->dspless_mode_selected) 1244 goto skip_disable_dsp; 1245 1246 /* no need to check for error as the DSP will be disabled anyway */ 1247 if (chip && chip->power_down_dsp) 1248 chip->power_down_dsp(sdev); 1249 1250 /* disable DSP */ 1251 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1252 SOF_HDA_PPCTL_GPROCEN, 0); 1253 1254 skip_disable_dsp: 1255 free_irq(sdev->ipc_irq, sdev); 1256 if (sdev->msi_enabled) 1257 pci_free_irq_vectors(pci); 1258 1259 hda_dsp_stream_free(sdev); 1260 1261 hda_bus_ml_free(sof_to_bus(sdev)); 1262 1263 if (!sdev->dspless_mode_selected) 1264 iounmap(sdev->bar[HDA_DSP_BAR]); 1265 1266 iounmap(bus->remap_addr); 1267 1268 sof_hda_bus_exit(sdev); 1269 1270 hda_codec_i915_exit(sdev); 1271 1272 return 0; 1273 } 1274 1275 int hda_power_down_dsp(struct snd_sof_dev *sdev) 1276 { 1277 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1278 const struct sof_intel_dsp_desc *chip = hda->desc; 1279 1280 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 1281 } 1282 1283 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 1284 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1285 struct snd_soc_acpi_mach **mach) 1286 { 1287 struct hdac_bus *bus = sof_to_bus(sdev); 1288 struct snd_soc_acpi_mach_params *mach_params; 1289 struct snd_soc_acpi_mach *hda_mach; 1290 struct snd_sof_pdata *pdata = sdev->pdata; 1291 const char *tplg_filename; 1292 const char *idisp_str; 1293 int dmic_num = 0; 1294 int codec_num = 0; 1295 int ret; 1296 int i; 1297 1298 /* codec detection */ 1299 if (!bus->codec_mask) { 1300 dev_info(bus->dev, "no hda codecs found!\n"); 1301 } else { 1302 dev_info(bus->dev, "hda codecs found, mask %lx\n", 1303 bus->codec_mask); 1304 1305 for (i = 0; i < HDA_MAX_CODECS; i++) { 1306 if (bus->codec_mask & (1 << i)) 1307 codec_num++; 1308 } 1309 1310 /* 1311 * If no machine driver is found, then: 1312 * 1313 * generic hda machine driver can handle: 1314 * - one HDMI codec, and/or 1315 * - one external HDAudio codec 1316 */ 1317 if (!*mach && codec_num <= 2) { 1318 bool tplg_fixup; 1319 1320 hda_mach = snd_soc_acpi_intel_hda_machines; 1321 1322 dev_info(bus->dev, "using HDA machine driver %s now\n", 1323 hda_mach->drv_name); 1324 1325 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask)) 1326 idisp_str = "-idisp"; 1327 else 1328 idisp_str = ""; 1329 1330 /* topology: use the info from hda_machines */ 1331 if (pdata->tplg_filename) { 1332 tplg_fixup = false; 1333 tplg_filename = pdata->tplg_filename; 1334 } else { 1335 tplg_fixup = true; 1336 tplg_filename = hda_mach->sof_tplg_filename; 1337 } 1338 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num, 1339 tplg_fixup); 1340 if (ret < 0) 1341 return; 1342 1343 hda_mach->mach_params.dmic_num = dmic_num; 1344 pdata->tplg_filename = tplg_filename; 1345 1346 if (codec_num == 2) { 1347 /* 1348 * Prevent SoundWire links from starting when an external 1349 * HDaudio codec is used 1350 */ 1351 hda_mach->mach_params.link_mask = 0; 1352 } 1353 1354 *mach = hda_mach; 1355 } 1356 } 1357 1358 /* used by hda machine driver to create dai links */ 1359 if (*mach) { 1360 mach_params = &(*mach)->mach_params; 1361 mach_params->codec_mask = bus->codec_mask; 1362 mach_params->common_hdmi_codec_drv = true; 1363 } 1364 } 1365 #else 1366 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1367 struct snd_soc_acpi_mach **mach) 1368 { 1369 } 1370 #endif 1371 1372 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1373 1374 #define SDW_CODEC_ADR_MASK(_adr) ((_adr) & (SDW_DISCO_LINK_ID_MASK | SDW_VERSION_MASK | \ 1375 SDW_MFG_ID_MASK | SDW_PART_ID_MASK)) 1376 1377 /* Check if all Slaves defined on the link can be found */ 1378 static bool link_slaves_found(struct snd_sof_dev *sdev, 1379 const struct snd_soc_acpi_link_adr *link, 1380 struct sdw_intel_ctx *sdw) 1381 { 1382 struct hdac_bus *bus = sof_to_bus(sdev); 1383 struct sdw_intel_slave_id *ids = sdw->ids; 1384 int num_slaves = sdw->num_slaves; 1385 unsigned int part_id, link_id, unique_id, mfg_id, version; 1386 int i, j, k; 1387 1388 for (i = 0; i < link->num_adr; i++) { 1389 u64 adr = link->adr_d[i].adr; 1390 int reported_part_count = 0; 1391 1392 mfg_id = SDW_MFG_ID(adr); 1393 part_id = SDW_PART_ID(adr); 1394 link_id = SDW_DISCO_LINK_ID(adr); 1395 version = SDW_VERSION(adr); 1396 1397 for (j = 0; j < num_slaves; j++) { 1398 /* find out how many identical parts were reported on that link */ 1399 if (ids[j].link_id == link_id && 1400 ids[j].id.part_id == part_id && 1401 ids[j].id.mfg_id == mfg_id && 1402 ids[j].id.sdw_version == version) 1403 reported_part_count++; 1404 } 1405 1406 for (j = 0; j < num_slaves; j++) { 1407 int expected_part_count = 0; 1408 1409 if (ids[j].link_id != link_id || 1410 ids[j].id.part_id != part_id || 1411 ids[j].id.mfg_id != mfg_id || 1412 ids[j].id.sdw_version != version) 1413 continue; 1414 1415 /* find out how many identical parts are expected */ 1416 for (k = 0; k < link->num_adr; k++) { 1417 u64 adr2 = link->adr_d[k].adr; 1418 1419 if (SDW_CODEC_ADR_MASK(adr2) == SDW_CODEC_ADR_MASK(adr)) 1420 expected_part_count++; 1421 } 1422 1423 if (reported_part_count == expected_part_count) { 1424 /* 1425 * we have to check unique id 1426 * if there is more than one 1427 * Slave on the link 1428 */ 1429 unique_id = SDW_UNIQUE_ID(adr); 1430 if (reported_part_count == 1 || 1431 ids[j].id.unique_id == unique_id) { 1432 dev_dbg(bus->dev, "found %x at link %d\n", 1433 part_id, link_id); 1434 break; 1435 } 1436 } else { 1437 dev_dbg(bus->dev, "part %x reported %d expected %d on link %d, skipping\n", 1438 part_id, reported_part_count, expected_part_count, link_id); 1439 } 1440 } 1441 if (j == num_slaves) { 1442 dev_dbg(bus->dev, 1443 "Slave %x not found\n", 1444 part_id); 1445 return false; 1446 } 1447 } 1448 return true; 1449 } 1450 1451 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1452 { 1453 struct snd_sof_pdata *pdata = sdev->pdata; 1454 const struct snd_soc_acpi_link_adr *link; 1455 struct snd_soc_acpi_mach *mach; 1456 struct sof_intel_hda_dev *hdev; 1457 u32 link_mask; 1458 int i; 1459 1460 hdev = pdata->hw_pdata; 1461 link_mask = hdev->info.link_mask; 1462 1463 /* 1464 * Select SoundWire machine driver if needed using the 1465 * alternate tables. This case deals with SoundWire-only 1466 * machines, for mixed cases with I2C/I2S the detection relies 1467 * on the HID list. 1468 */ 1469 if (link_mask) { 1470 for (mach = pdata->desc->alt_machines; 1471 mach && mach->link_mask; mach++) { 1472 /* 1473 * On some platforms such as Up Extreme all links 1474 * are enabled but only one link can be used by 1475 * external codec. Instead of exact match of two masks, 1476 * first check whether link_mask of mach is subset of 1477 * link_mask supported by hw and then go on searching 1478 * link_adr 1479 */ 1480 if (~link_mask & mach->link_mask) 1481 continue; 1482 1483 /* No need to match adr if there is no links defined */ 1484 if (!mach->links) 1485 break; 1486 1487 link = mach->links; 1488 for (i = 0; i < hdev->info.count && link->num_adr; 1489 i++, link++) { 1490 /* 1491 * Try next machine if any expected Slaves 1492 * are not found on this link. 1493 */ 1494 if (!link_slaves_found(sdev, link, hdev->sdw)) 1495 break; 1496 } 1497 /* Found if all Slaves are checked */ 1498 if (i == hdev->info.count || !link->num_adr) 1499 break; 1500 } 1501 if (mach && mach->link_mask) { 1502 int dmic_num = 0; 1503 bool tplg_fixup; 1504 const char *tplg_filename; 1505 1506 mach->mach_params.links = mach->links; 1507 mach->mach_params.link_mask = mach->link_mask; 1508 mach->mach_params.platform = dev_name(sdev->dev); 1509 1510 if (pdata->tplg_filename) { 1511 tplg_fixup = false; 1512 } else { 1513 tplg_fixup = true; 1514 tplg_filename = mach->sof_tplg_filename; 1515 } 1516 1517 /* 1518 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire 1519 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics 1520 * if all conditions are true: 1521 * a) 2 or fewer links are used by SoundWire 1522 * b) the NHLT table reports the presence of microphones 1523 */ 1524 if (hweight_long(mach->link_mask) <= 2) { 1525 int ret; 1526 1527 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "", 1528 &dmic_num, tplg_fixup); 1529 if (ret < 0) 1530 return NULL; 1531 } 1532 if (tplg_fixup) 1533 pdata->tplg_filename = tplg_filename; 1534 mach->mach_params.dmic_num = dmic_num; 1535 1536 dev_dbg(sdev->dev, 1537 "SoundWire machine driver %s topology %s\n", 1538 mach->drv_name, 1539 pdata->tplg_filename); 1540 1541 return mach; 1542 } 1543 1544 dev_info(sdev->dev, "No SoundWire machine driver found\n"); 1545 } 1546 1547 return NULL; 1548 } 1549 #else 1550 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1551 { 1552 return NULL; 1553 } 1554 #endif 1555 1556 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 1557 struct snd_sof_dev *sdev) 1558 { 1559 struct snd_sof_pdata *pdata = sdev->pdata; 1560 const struct sof_dev_desc *desc = pdata->desc; 1561 struct snd_soc_acpi_mach_params *mach_params; 1562 1563 mach_params = &mach->mach_params; 1564 mach_params->platform = dev_name(sdev->dev); 1565 mach_params->num_dai_drivers = desc->ops->num_drv; 1566 mach_params->dai_drivers = desc->ops->drv; 1567 } 1568 1569 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev) 1570 { 1571 u32 interface_mask = hda_get_interface_mask(sdev); 1572 struct snd_sof_pdata *sof_pdata = sdev->pdata; 1573 const struct sof_dev_desc *desc = sof_pdata->desc; 1574 struct snd_soc_acpi_mach *mach = NULL; 1575 const char *tplg_filename; 1576 1577 /* Try I2S or DMIC if it is supported */ 1578 if (interface_mask & (BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC))) 1579 mach = snd_soc_acpi_find_machine(desc->machines); 1580 1581 if (mach) { 1582 bool add_extension = false; 1583 bool tplg_fixup = false; 1584 1585 /* 1586 * If tplg file name is overridden, use it instead of 1587 * the one set in mach table 1588 */ 1589 if (!sof_pdata->tplg_filename) { 1590 sof_pdata->tplg_filename = mach->sof_tplg_filename; 1591 tplg_fixup = true; 1592 } 1593 1594 /* report to machine driver if any DMICs are found */ 1595 mach->mach_params.dmic_num = check_dmic_num(sdev); 1596 1597 if (tplg_fixup && 1598 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER && 1599 mach->mach_params.dmic_num) { 1600 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1601 "%s%s%d%s", 1602 sof_pdata->tplg_filename, 1603 "-dmic", 1604 mach->mach_params.dmic_num, 1605 "ch"); 1606 if (!tplg_filename) 1607 return NULL; 1608 1609 sof_pdata->tplg_filename = tplg_filename; 1610 add_extension = true; 1611 } 1612 1613 if (mach->link_mask) { 1614 mach->mach_params.links = mach->links; 1615 mach->mach_params.link_mask = mach->link_mask; 1616 } 1617 1618 /* report SSP link mask to machine driver */ 1619 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev); 1620 1621 if (tplg_fixup && 1622 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER && 1623 mach->mach_params.i2s_link_mask) { 1624 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 1625 int ssp_num; 1626 int mclk_mask; 1627 1628 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 && 1629 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB)) 1630 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n"); 1631 1632 /* fls returns 1-based results, SSPs indices are 0-based */ 1633 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1; 1634 1635 if (ssp_num >= chip->ssp_count) { 1636 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n", 1637 ssp_num, chip->ssp_count); 1638 return NULL; 1639 } 1640 1641 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1642 "%s%s%d", 1643 sof_pdata->tplg_filename, 1644 "-ssp", 1645 ssp_num); 1646 if (!tplg_filename) 1647 return NULL; 1648 1649 sof_pdata->tplg_filename = tplg_filename; 1650 add_extension = true; 1651 1652 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); 1653 1654 if (mclk_mask < 0) { 1655 dev_err(sdev->dev, "Invalid MCLK configuration\n"); 1656 return NULL; 1657 } 1658 1659 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); 1660 1661 if (mclk_mask) { 1662 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); 1663 sdev->mclk_id_override = true; 1664 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; 1665 } 1666 } 1667 1668 if (tplg_fixup && add_extension) { 1669 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1670 "%s%s", 1671 sof_pdata->tplg_filename, 1672 ".tplg"); 1673 if (!tplg_filename) 1674 return NULL; 1675 1676 sof_pdata->tplg_filename = tplg_filename; 1677 } 1678 1679 /* check if mclk_id should be modified from topology defaults */ 1680 if (mclk_id_override >= 0) { 1681 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override); 1682 sdev->mclk_id_override = true; 1683 sdev->mclk_id_quirk = mclk_id_override; 1684 } 1685 } 1686 1687 /* If I2S fails, try SoundWire if it is supported */ 1688 if (!mach && (interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1689 mach = hda_sdw_machine_select(sdev); 1690 1691 /* 1692 * Choose HDA generic machine driver if mach is NULL. 1693 * Otherwise, set certain mach params. 1694 */ 1695 hda_generic_machine_select(sdev, &mach); 1696 if (!mach) 1697 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 1698 1699 return mach; 1700 } 1701 1702 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1703 { 1704 int ret; 1705 1706 ret = snd_intel_dsp_driver_probe(pci); 1707 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1708 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n"); 1709 return -ENODEV; 1710 } 1711 1712 return sof_pci_probe(pci, pci_id); 1713 } 1714 EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON); 1715 1716 int hda_register_clients(struct snd_sof_dev *sdev) 1717 { 1718 return hda_probes_register(sdev); 1719 } 1720 1721 void hda_unregister_clients(struct snd_sof_dev *sdev) 1722 { 1723 hda_probes_unregister(sdev); 1724 } 1725 1726 MODULE_LICENSE("Dual BSD/GPL"); 1727 MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); 1728 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC); 1729 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915); 1730 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1731 MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI); 1732 MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT); 1733 MODULE_IMPORT_NS(SOUNDWIRE_INTEL); 1734 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK); 1735