1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <sound/hdaudio_ext.h> 19 #include <sound/hda_register.h> 20 21 #include <linux/acpi.h> 22 #include <linux/module.h> 23 #include <linux/soundwire/sdw.h> 24 #include <linux/soundwire/sdw_intel.h> 25 #include <sound/intel-dsp-config.h> 26 #include <sound/intel-nhlt.h> 27 #include <sound/soc-acpi-intel-ssp-common.h> 28 #include <sound/sof.h> 29 #include <sound/sof/xtensa.h> 30 #include <sound/hda-mlink.h> 31 #include "../sof-audio.h" 32 #include "../sof-pci-dev.h" 33 #include "../ops.h" 34 #include "../ipc4-topology.h" 35 #include "hda.h" 36 #include "telemetry.h" 37 38 #define CREATE_TRACE_POINTS 39 #include <trace/events/sof_intel.h> 40 41 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 42 #include <sound/soc-acpi-intel-match.h> 43 #endif 44 45 /* platform specific devices */ 46 #include "shim.h" 47 48 #define EXCEPT_MAX_HDR_SIZE 0x400 49 #define HDA_EXT_ROM_STATUS_SIZE 8 50 51 static void hda_get_interfaces(struct snd_sof_dev *sdev, u32 *interface_mask) 52 { 53 const struct sof_intel_dsp_desc *chip; 54 55 chip = get_chip_info(sdev->pdata); 56 switch (chip->hw_ip_version) { 57 case SOF_INTEL_TANGIER: 58 case SOF_INTEL_BAYTRAIL: 59 case SOF_INTEL_BROADWELL: 60 interface_mask[SOF_DAI_DSP_ACCESS] = BIT(SOF_DAI_INTEL_SSP); 61 break; 62 case SOF_INTEL_CAVS_1_5: 63 case SOF_INTEL_CAVS_1_5_PLUS: 64 interface_mask[SOF_DAI_DSP_ACCESS] = 65 BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | BIT(SOF_DAI_INTEL_HDA); 66 interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA); 67 break; 68 case SOF_INTEL_CAVS_1_8: 69 case SOF_INTEL_CAVS_2_0: 70 case SOF_INTEL_CAVS_2_5: 71 case SOF_INTEL_ACE_1_0: 72 interface_mask[SOF_DAI_DSP_ACCESS] = 73 BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 74 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 75 interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA); 76 break; 77 case SOF_INTEL_ACE_2_0: 78 interface_mask[SOF_DAI_DSP_ACCESS] = 79 BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 80 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 81 /* all interfaces accessible without DSP */ 82 interface_mask[SOF_DAI_HOST_ACCESS] = 83 interface_mask[SOF_DAI_DSP_ACCESS]; 84 break; 85 default: 86 break; 87 } 88 } 89 90 static u32 hda_get_interface_mask(struct snd_sof_dev *sdev) 91 { 92 u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 }; 93 94 hda_get_interfaces(sdev, interface_mask); 95 96 return interface_mask[sdev->dspless_mode_selected]; 97 } 98 99 bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type) 100 { 101 u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 }; 102 const struct sof_intel_dsp_desc *chip; 103 104 if (sdev->dspless_mode_selected) 105 return false; 106 107 hda_get_interfaces(sdev, interface_mask); 108 109 if (!(interface_mask[SOF_DAI_DSP_ACCESS] & BIT(dai_type))) 110 return false; 111 112 if (dai_type == SOF_DAI_INTEL_HDA) 113 return true; 114 115 switch (dai_type) { 116 case SOF_DAI_INTEL_SSP: 117 case SOF_DAI_INTEL_DMIC: 118 case SOF_DAI_INTEL_ALH: 119 chip = get_chip_info(sdev->pdata); 120 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) 121 return false; 122 return true; 123 default: 124 return false; 125 } 126 } 127 128 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 129 130 /* 131 * The default for SoundWire clock stop quirks is to power gate the IP 132 * and do a Bus Reset, this will need to be modified when the DSP 133 * needs to remain in D0i3 so that the Master does not lose context 134 * and enumeration is not required on clock restart 135 */ 136 static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET; 137 module_param(sdw_clock_stop_quirks, int, 0444); 138 MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks"); 139 140 static int sdw_params_stream(struct device *dev, 141 struct sdw_intel_stream_params_data *params_data) 142 { 143 struct snd_soc_dai *d = params_data->dai; 144 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->substream->stream); 145 struct snd_sof_dai_config_data data = { 0 }; 146 147 data.dai_index = (params_data->link_id << 8) | d->id; 148 data.dai_data = params_data->alh_stream_id; 149 data.dai_node_id = data.dai_data; 150 151 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data); 152 } 153 154 static int sdw_params_free(struct device *dev, struct sdw_intel_stream_free_data *free_data) 155 { 156 struct snd_soc_dai *d = free_data->dai; 157 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, free_data->substream->stream); 158 struct snd_sof_dev *sdev = widget_to_sdev(w); 159 160 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) { 161 struct snd_sof_widget *swidget = w->dobj.private; 162 struct snd_sof_dai *dai = swidget->private; 163 struct sof_ipc4_copier_data *copier_data; 164 struct sof_ipc4_copier *ipc4_copier; 165 166 ipc4_copier = dai->private; 167 ipc4_copier->dai_index = 0; 168 copier_data = &ipc4_copier->data; 169 170 /* clear the node ID */ 171 copier_data->gtw_cfg.node_id &= ~SOF_IPC4_NODE_INDEX_MASK; 172 } 173 174 return 0; 175 } 176 177 struct sdw_intel_ops sdw_callback = { 178 .params_stream = sdw_params_stream, 179 .free_stream = sdw_params_free, 180 }; 181 182 static int sdw_ace2x_params_stream(struct device *dev, 183 struct sdw_intel_stream_params_data *params_data) 184 { 185 return sdw_hda_dai_hw_params(params_data->substream, 186 params_data->hw_params, 187 params_data->dai, 188 params_data->link_id, 189 params_data->alh_stream_id); 190 } 191 192 static int sdw_ace2x_free_stream(struct device *dev, 193 struct sdw_intel_stream_free_data *free_data) 194 { 195 return sdw_hda_dai_hw_free(free_data->substream, 196 free_data->dai, 197 free_data->link_id); 198 } 199 200 static int sdw_ace2x_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) 201 { 202 return sdw_hda_dai_trigger(substream, cmd, dai); 203 } 204 205 static struct sdw_intel_ops sdw_ace2x_callback = { 206 .params_stream = sdw_ace2x_params_stream, 207 .free_stream = sdw_ace2x_free_stream, 208 .trigger = sdw_ace2x_trigger, 209 }; 210 211 void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 212 { 213 struct sof_intel_hda_dev *hdev; 214 215 hdev = sdev->pdata->hw_pdata; 216 217 if (!hdev->sdw) 218 return; 219 220 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2, 221 HDA_DSP_REG_ADSPIC2_SNDW, 222 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0); 223 } 224 225 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 226 { 227 u32 interface_mask = hda_get_interface_mask(sdev); 228 const struct sof_intel_dsp_desc *chip; 229 230 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 231 return; 232 233 chip = get_chip_info(sdev->pdata); 234 if (chip && chip->enable_sdw_irq) 235 chip->enable_sdw_irq(sdev, enable); 236 } 237 238 static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 239 { 240 u32 interface_mask = hda_get_interface_mask(sdev); 241 struct sof_intel_hda_dev *hdev; 242 acpi_handle handle; 243 int ret; 244 245 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 246 return -EINVAL; 247 248 handle = ACPI_HANDLE(sdev->dev); 249 250 /* save ACPI info for the probe step */ 251 hdev = sdev->pdata->hw_pdata; 252 253 ret = sdw_intel_acpi_scan(handle, &hdev->info); 254 if (ret < 0) 255 return -EINVAL; 256 257 return 0; 258 } 259 260 static int hda_sdw_probe(struct snd_sof_dev *sdev) 261 { 262 const struct sof_intel_dsp_desc *chip; 263 struct sof_intel_hda_dev *hdev; 264 struct sdw_intel_res res; 265 void *sdw; 266 267 hdev = sdev->pdata->hw_pdata; 268 269 memset(&res, 0, sizeof(res)); 270 271 chip = get_chip_info(sdev->pdata); 272 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) { 273 res.mmio_base = sdev->bar[HDA_DSP_BAR]; 274 res.hw_ops = &sdw_intel_cnl_hw_ops; 275 res.shim_base = hdev->desc->sdw_shim_base; 276 res.alh_base = hdev->desc->sdw_alh_base; 277 res.ext = false; 278 res.ops = &sdw_callback; 279 } else { 280 /* 281 * retrieve eml_lock needed to protect shared registers 282 * in the HDaudio multi-link areas 283 */ 284 res.eml_lock = hdac_bus_eml_get_mutex(sof_to_bus(sdev), true, 285 AZX_REG_ML_LEPTR_ID_SDW); 286 if (!res.eml_lock) 287 return -ENODEV; 288 289 res.mmio_base = sdev->bar[HDA_DSP_HDA_BAR]; 290 /* 291 * the SHIM and SoundWire register offsets are link-specific 292 * and will be determined when adding auxiliary devices 293 */ 294 res.hw_ops = &sdw_intel_lnl_hw_ops; 295 res.ext = true; 296 res.ops = &sdw_ace2x_callback; 297 298 } 299 res.irq = sdev->ipc_irq; 300 res.handle = hdev->info.handle; 301 res.parent = sdev->dev; 302 303 res.dev = sdev->dev; 304 res.clock_stop_quirks = sdw_clock_stop_quirks; 305 res.hbus = sof_to_bus(sdev); 306 307 /* 308 * ops and arg fields are not populated for now, 309 * they will be needed when the DAI callbacks are 310 * provided 311 */ 312 313 /* we could filter links here if needed, e.g for quirks */ 314 res.count = hdev->info.count; 315 res.link_mask = hdev->info.link_mask; 316 317 sdw = sdw_intel_probe(&res); 318 if (!sdw) { 319 dev_err(sdev->dev, "error: SoundWire probe failed\n"); 320 return -EINVAL; 321 } 322 323 /* save context */ 324 hdev->sdw = sdw; 325 326 return 0; 327 } 328 329 int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 330 { 331 struct sof_intel_hda_dev *hdev; 332 struct sdw_intel_ctx *ctx; 333 u32 caps; 334 335 hdev = sdev->pdata->hw_pdata; 336 ctx = hdev->sdw; 337 338 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); 339 caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 340 341 /* Check HW supported vs property value */ 342 if (caps < ctx->count) { 343 dev_err(sdev->dev, 344 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 345 __func__, ctx->count, caps); 346 return -EINVAL; 347 } 348 349 return 0; 350 } 351 352 int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) 353 { 354 struct sof_intel_hda_dev *hdev; 355 struct sdw_intel_ctx *ctx; 356 struct hdac_bus *bus; 357 u32 slcount; 358 359 bus = sof_to_bus(sdev); 360 361 hdev = sdev->pdata->hw_pdata; 362 ctx = hdev->sdw; 363 364 slcount = hdac_bus_eml_get_count(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 365 366 /* Check HW supported vs property value */ 367 if (slcount < ctx->count) { 368 dev_err(sdev->dev, 369 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 370 __func__, ctx->count, slcount); 371 return -EINVAL; 372 } 373 374 return 0; 375 } 376 377 static int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 378 { 379 const struct sof_intel_dsp_desc *chip; 380 381 chip = get_chip_info(sdev->pdata); 382 if (chip && chip->read_sdw_lcount) 383 return chip->read_sdw_lcount(sdev); 384 385 return 0; 386 } 387 388 int hda_sdw_startup(struct snd_sof_dev *sdev) 389 { 390 struct sof_intel_hda_dev *hdev; 391 struct snd_sof_pdata *pdata = sdev->pdata; 392 int ret; 393 394 hdev = sdev->pdata->hw_pdata; 395 396 if (!hdev->sdw) 397 return 0; 398 399 if (pdata->machine && !pdata->machine->mach_params.link_mask) 400 return 0; 401 402 ret = hda_sdw_check_lcount(sdev); 403 if (ret < 0) 404 return ret; 405 406 return sdw_intel_startup(hdev->sdw); 407 } 408 409 static int hda_sdw_exit(struct snd_sof_dev *sdev) 410 { 411 struct sof_intel_hda_dev *hdev; 412 413 hdev = sdev->pdata->hw_pdata; 414 415 hda_sdw_int_enable(sdev, false); 416 417 if (hdev->sdw) 418 sdw_intel_exit(hdev->sdw); 419 hdev->sdw = NULL; 420 421 return 0; 422 } 423 424 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 425 { 426 struct sof_intel_hda_dev *hdev; 427 bool ret = false; 428 u32 irq_status; 429 430 hdev = sdev->pdata->hw_pdata; 431 432 if (!hdev->sdw) 433 return ret; 434 435 /* store status */ 436 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); 437 438 /* invalid message ? */ 439 if (irq_status == 0xffffffff) 440 goto out; 441 442 /* SDW message ? */ 443 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW) 444 ret = true; 445 446 out: 447 return ret; 448 } 449 450 static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 451 { 452 u32 interface_mask = hda_get_interface_mask(sdev); 453 const struct sof_intel_dsp_desc *chip; 454 455 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 456 return false; 457 458 chip = get_chip_info(sdev->pdata); 459 if (chip && chip->check_sdw_irq) 460 return chip->check_sdw_irq(sdev); 461 462 return false; 463 } 464 465 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 466 { 467 return sdw_intel_thread(irq, context); 468 } 469 470 bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev) 471 { 472 struct sof_intel_hda_dev *hdev; 473 474 hdev = sdev->pdata->hw_pdata; 475 if (hdev->sdw && 476 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 477 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS)) 478 return true; 479 480 return false; 481 } 482 483 static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 484 { 485 u32 interface_mask = hda_get_interface_mask(sdev); 486 const struct sof_intel_dsp_desc *chip; 487 488 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 489 return false; 490 491 chip = get_chip_info(sdev->pdata); 492 if (chip && chip->check_sdw_wakeen_irq) 493 return chip->check_sdw_wakeen_irq(sdev); 494 495 return false; 496 } 497 498 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 499 { 500 u32 interface_mask = hda_get_interface_mask(sdev); 501 struct sof_intel_hda_dev *hdev; 502 503 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 504 return; 505 506 hdev = sdev->pdata->hw_pdata; 507 if (!hdev->sdw) 508 return; 509 510 sdw_intel_process_wakeen_event(hdev->sdw); 511 } 512 513 #else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 514 static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 515 { 516 return 0; 517 } 518 519 static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 520 { 521 return 0; 522 } 523 524 static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 525 { 526 return 0; 527 } 528 529 static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 530 { 531 return false; 532 } 533 534 static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 535 { 536 return IRQ_HANDLED; 537 } 538 539 static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 540 { 541 return false; 542 } 543 544 #endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 545 546 /* 547 * Debug 548 */ 549 550 struct hda_dsp_msg_code { 551 u32 code; 552 const char *text; 553 }; 554 555 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 556 static bool hda_use_msi = true; 557 module_param_named(use_msi, hda_use_msi, bool, 0444); 558 MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode"); 559 #else 560 #define hda_use_msi (1) 561 #endif 562 563 int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 564 module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 565 MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 566 567 static char *hda_model; 568 module_param(hda_model, charp, 0444); 569 MODULE_PARM_DESC(hda_model, "Use the given HDA board model."); 570 571 static int dmic_num_override = -1; 572 module_param_named(dmic_num, dmic_num_override, int, 0444); 573 MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number"); 574 575 static int mclk_id_override = -1; 576 module_param_named(mclk_id, mclk_id_override, int, 0444); 577 MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id"); 578 579 static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { 580 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"}, 581 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"}, 582 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"}, 583 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"}, 584 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"}, 585 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"}, 586 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"}, 587 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"}, 588 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"}, 589 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"}, 590 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"}, 591 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"}, 592 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"}, 593 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"}, 594 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"}, 595 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"}, 596 }; 597 598 #define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} 599 static const struct hda_dsp_msg_code fsr_rom_state_names[] = { 600 FSR_ROM_STATE_ENTRY(INIT), 601 FSR_ROM_STATE_ENTRY(INIT_DONE), 602 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 603 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 604 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 605 FSR_ROM_STATE_ENTRY(FW_ENTERED), 606 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 607 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 608 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT), 609 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE), 610 /* CSE states */ 611 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST), 612 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED), 613 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST), 614 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED), 615 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT), 616 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1), 617 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY), 618 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL), 619 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), 620 }; 621 622 #define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} 623 static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { 624 FSR_BRINGUP_STATE_ENTRY(INIT), 625 FSR_BRINGUP_STATE_ENTRY(INIT_DONE), 626 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD), 627 FSR_BRINGUP_STATE_ENTRY(UNPACK_START), 628 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE), 629 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED), 630 }; 631 632 #define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state} 633 static const struct hda_dsp_msg_code fsr_wait_state_names[] = { 634 FSR_WAIT_STATE_ENTRY(IPC_BUSY), 635 FSR_WAIT_STATE_ENTRY(IPC_DONE), 636 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION), 637 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF), 638 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL), 639 FSR_WAIT_STATE_ENTRY(CSE_CSR), 640 }; 641 642 #define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod 643 static const char * const fsr_module_names[] = { 644 FSR_MODULE_NAME_ENTRY(ROM), 645 FSR_MODULE_NAME_ENTRY(ROM_BYP), 646 FSR_MODULE_NAME_ENTRY(BASE_FW), 647 FSR_MODULE_NAME_ENTRY(LP_BOOT), 648 FSR_MODULE_NAME_ENTRY(BRNGUP), 649 FSR_MODULE_NAME_ENTRY(ROM_EXT), 650 }; 651 652 static const char * 653 hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, 654 size_t array_size) 655 { 656 int i; 657 658 for (i = 0; i < array_size; i++) { 659 if (code == msg_code[i].code) 660 return msg_code[i].text; 661 } 662 663 return NULL; 664 } 665 666 static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) 667 { 668 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 669 const char *state_text, *error_text, *module_text; 670 u32 fsr, state, wait_state, module, error_code; 671 672 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); 673 state = FSR_TO_STATE_CODE(fsr); 674 wait_state = FSR_TO_WAIT_STATE_CODE(fsr); 675 module = FSR_TO_MODULE_CODE(fsr); 676 677 if (module > FSR_MOD_ROM_EXT) 678 module_text = "unknown"; 679 else 680 module_text = fsr_module_names[module]; 681 682 if (module == FSR_MOD_BRNGUP) 683 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, 684 ARRAY_SIZE(fsr_bringup_state_names)); 685 else 686 state_text = hda_dsp_get_state_text(state, fsr_rom_state_names, 687 ARRAY_SIZE(fsr_rom_state_names)); 688 689 /* not for us, must be generic sof message */ 690 if (!state_text) { 691 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); 692 return; 693 } 694 695 if (wait_state) { 696 const char *wait_state_text; 697 698 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names, 699 ARRAY_SIZE(fsr_wait_state_names)); 700 if (!wait_state_text) 701 wait_state_text = "unknown"; 702 703 dev_printk(level, sdev->dev, 704 "%#010x: module: %s, state: %s, waiting for: %s, %s\n", 705 fsr, module_text, state_text, wait_state_text, 706 fsr & FSR_HALTED ? "not running" : "running"); 707 } else { 708 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", 709 fsr, module_text, state_text, 710 fsr & FSR_HALTED ? "not running" : "running"); 711 } 712 713 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); 714 if (!error_code) 715 return; 716 717 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts, 718 ARRAY_SIZE(hda_dsp_rom_fw_error_texts)); 719 if (!error_text) 720 error_text = "unknown"; 721 722 if (state == FSR_STATE_FW_ENTERED) 723 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, 724 error_text); 725 else 726 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, 727 error_text); 728 } 729 730 static void hda_dsp_get_registers(struct snd_sof_dev *sdev, 731 struct sof_ipc_dsp_oops_xtensa *xoops, 732 struct sof_ipc_panic_info *panic_info, 733 u32 *stack, size_t stack_words) 734 { 735 u32 offset = sdev->dsp_oops_offset; 736 737 /* first read registers */ 738 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 739 740 /* note: variable AR register array is not read */ 741 742 /* then get panic info */ 743 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 744 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 745 xoops->arch_hdr.totalsize); 746 return; 747 } 748 offset += xoops->arch_hdr.totalsize; 749 sof_block_read(sdev, sdev->mmio_bar, offset, 750 panic_info, sizeof(*panic_info)); 751 752 /* then get the stack */ 753 offset += sizeof(*panic_info); 754 sof_block_read(sdev, sdev->mmio_bar, offset, stack, 755 stack_words * sizeof(u32)); 756 } 757 758 /* dump the first 8 dwords representing the extended ROM status */ 759 static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 760 u32 flags) 761 { 762 const struct sof_intel_dsp_desc *chip; 763 char msg[128]; 764 int len = 0; 765 u32 value; 766 int i; 767 768 chip = get_chip_info(sdev->pdata); 769 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) { 770 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); 771 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); 772 } 773 774 dev_printk(level, sdev->dev, "extended rom status: %s", msg); 775 776 } 777 778 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 779 { 780 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 781 struct sof_ipc_dsp_oops_xtensa xoops; 782 struct sof_ipc_panic_info panic_info; 783 u32 stack[HDA_DSP_STACK_DUMP_SIZE]; 784 785 /* print ROM/FW status */ 786 hda_dsp_get_state(sdev, level); 787 788 /* The firmware register dump only available with IPC3 */ 789 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC_TYPE_3) { 790 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS); 791 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP); 792 793 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack, 794 HDA_DSP_STACK_DUMP_SIZE); 795 sof_print_oops_and_stack(sdev, level, status, panic, &xoops, 796 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE); 797 } else { 798 hda_dsp_dump_ext_rom_status(sdev, level, flags); 799 } 800 } 801 802 void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 803 { 804 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 805 806 /* print ROM/FW status */ 807 hda_dsp_get_state(sdev, level); 808 809 if (flags & SOF_DBG_DUMP_REGS) 810 sof_ipc4_intel_dump_telemetry_state(sdev, flags); 811 else 812 hda_dsp_dump_ext_rom_status(sdev, level, flags); 813 } 814 815 static bool hda_check_ipc_irq(struct snd_sof_dev *sdev) 816 { 817 const struct sof_intel_dsp_desc *chip; 818 819 chip = get_chip_info(sdev->pdata); 820 if (chip && chip->check_ipc_irq) 821 return chip->check_ipc_irq(sdev); 822 823 return false; 824 } 825 826 void hda_ipc_irq_dump(struct snd_sof_dev *sdev) 827 { 828 u32 adspis; 829 u32 intsts; 830 u32 intctl; 831 u32 ppsts; 832 u8 rirbsts; 833 834 /* read key IRQ stats and config registers */ 835 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS); 836 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 837 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL); 838 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS); 839 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS); 840 841 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", 842 intsts, intctl, rirbsts); 843 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); 844 } 845 846 void hda_ipc_dump(struct snd_sof_dev *sdev) 847 { 848 u32 hipcie; 849 u32 hipct; 850 u32 hipcctl; 851 852 hda_ipc_irq_dump(sdev); 853 854 /* read IPC status */ 855 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 856 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 857 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 858 859 /* dump the IPC regs */ 860 /* TODO: parse the raw msg */ 861 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 862 hipcie, hipct, hipcctl); 863 } 864 865 void hda_ipc4_dump(struct snd_sof_dev *sdev) 866 { 867 u32 hipci, hipcie, hipct, hipcte, hipcctl; 868 869 hda_ipc_irq_dump(sdev); 870 871 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI); 872 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 873 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 874 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE); 875 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 876 877 /* dump the IPC regs */ 878 /* TODO: parse the raw msg */ 879 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", 880 hipci, hipcie, hipct, hipcte, hipcctl); 881 } 882 883 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev) 884 { 885 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 886 const struct sof_intel_dsp_desc *chip = hda->desc; 887 u32 val; 888 889 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); 890 891 return !!(val & chip->ipc_req_mask); 892 } 893 894 static int hda_init(struct snd_sof_dev *sdev) 895 { 896 struct hda_bus *hbus; 897 struct hdac_bus *bus; 898 struct pci_dev *pci = to_pci_dev(sdev->dev); 899 int ret; 900 901 hbus = sof_to_hbus(sdev); 902 bus = sof_to_bus(sdev); 903 904 /* HDA bus init */ 905 sof_hda_bus_init(sdev, &pci->dev); 906 907 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) 908 bus->use_posbuf = 0; 909 else 910 bus->use_posbuf = 1; 911 bus->bdl_pos_adj = 0; 912 bus->sync_write = 1; 913 914 mutex_init(&hbus->prepare_mutex); 915 hbus->pci = pci; 916 hbus->mixer_assigned = -1; 917 hbus->modelname = hda_model; 918 919 /* initialise hdac bus */ 920 bus->addr = pci_resource_start(pci, 0); 921 bus->remap_addr = pci_ioremap_bar(pci, 0); 922 if (!bus->remap_addr) { 923 dev_err(bus->dev, "error: ioremap error\n"); 924 return -ENXIO; 925 } 926 927 /* HDA base */ 928 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr; 929 930 /* init i915 and HDMI codecs */ 931 ret = hda_codec_i915_init(sdev); 932 if (ret < 0 && ret != -ENODEV) { 933 dev_err_probe(sdev->dev, ret, "init of i915 and HDMI codec failed\n"); 934 goto out; 935 } 936 937 /* get controller capabilities */ 938 ret = hda_dsp_ctrl_get_caps(sdev); 939 if (ret < 0) { 940 dev_err(sdev->dev, "error: get caps error\n"); 941 hda_codec_i915_exit(sdev); 942 } 943 944 out: 945 if (ret < 0) 946 iounmap(sof_to_bus(sdev)->remap_addr); 947 948 return ret; 949 } 950 951 static int check_dmic_num(struct snd_sof_dev *sdev) 952 { 953 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 954 struct nhlt_acpi_table *nhlt; 955 int dmic_num = 0; 956 957 nhlt = hdev->nhlt; 958 if (nhlt) 959 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt); 960 961 /* allow for module parameter override */ 962 if (dmic_num_override != -1) { 963 dev_dbg(sdev->dev, 964 "overriding DMICs detected in NHLT tables %d by kernel param %d\n", 965 dmic_num, dmic_num_override); 966 dmic_num = dmic_num_override; 967 } 968 969 if (dmic_num < 0 || dmic_num > 4) { 970 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num); 971 dmic_num = 0; 972 } 973 974 return dmic_num; 975 } 976 977 static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev) 978 { 979 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 980 struct nhlt_acpi_table *nhlt; 981 int ssp_mask = 0; 982 983 nhlt = hdev->nhlt; 984 if (!nhlt) 985 return ssp_mask; 986 987 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) { 988 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S); 989 if (ssp_mask) 990 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask); 991 } 992 993 return ssp_mask; 994 } 995 996 static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num) 997 { 998 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 999 struct nhlt_acpi_table *nhlt; 1000 1001 nhlt = hdev->nhlt; 1002 if (!nhlt) 1003 return 0; 1004 1005 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num); 1006 } 1007 1008 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1009 1010 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 1011 const char *sof_tplg_filename, 1012 const char *idisp_str, 1013 const char *dmic_str) 1014 { 1015 const char *tplg_filename = NULL; 1016 char *filename, *tmp; 1017 const char *split_ext; 1018 1019 filename = kstrdup(sof_tplg_filename, GFP_KERNEL); 1020 if (!filename) 1021 return NULL; 1022 1023 /* this assumes a .tplg extension */ 1024 tmp = filename; 1025 split_ext = strsep(&tmp, "."); 1026 if (split_ext) 1027 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1028 "%s%s%s.tplg", 1029 split_ext, idisp_str, dmic_str); 1030 kfree(filename); 1031 1032 return tplg_filename; 1033 } 1034 1035 static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev, 1036 const char **tplg_filename, 1037 const char *idisp_str, 1038 int *dmic_found, 1039 bool tplg_fixup) 1040 { 1041 const char *dmic_str; 1042 int dmic_num; 1043 1044 /* first check for DMICs (using NHLT or module parameter) */ 1045 dmic_num = check_dmic_num(sdev); 1046 1047 switch (dmic_num) { 1048 case 1: 1049 dmic_str = "-1ch"; 1050 break; 1051 case 2: 1052 dmic_str = "-2ch"; 1053 break; 1054 case 3: 1055 dmic_str = "-3ch"; 1056 break; 1057 case 4: 1058 dmic_str = "-4ch"; 1059 break; 1060 default: 1061 dmic_num = 0; 1062 dmic_str = ""; 1063 break; 1064 } 1065 1066 if (tplg_fixup) { 1067 const char *default_tplg_filename = *tplg_filename; 1068 const char *fixed_tplg_filename; 1069 1070 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename, 1071 idisp_str, dmic_str); 1072 if (!fixed_tplg_filename) 1073 return -ENOMEM; 1074 *tplg_filename = fixed_tplg_filename; 1075 } 1076 1077 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num); 1078 *dmic_found = dmic_num; 1079 1080 return 0; 1081 } 1082 #endif 1083 1084 static int hda_init_caps(struct snd_sof_dev *sdev) 1085 { 1086 u32 interface_mask = hda_get_interface_mask(sdev); 1087 struct hdac_bus *bus = sof_to_bus(sdev); 1088 struct snd_sof_pdata *pdata = sdev->pdata; 1089 struct sof_intel_hda_dev *hdev = pdata->hw_pdata; 1090 u32 link_mask; 1091 int ret = 0; 1092 1093 /* check if dsp is there */ 1094 if (bus->ppcap) 1095 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n"); 1096 1097 /* Init HDA controller after i915 init */ 1098 ret = hda_dsp_ctrl_init_chip(sdev); 1099 if (ret < 0) { 1100 dev_err(bus->dev, "error: init chip failed with ret: %d\n", 1101 ret); 1102 return ret; 1103 } 1104 1105 hda_bus_ml_init(bus); 1106 1107 /* Skip SoundWire if it is not supported */ 1108 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1109 goto skip_soundwire; 1110 1111 /* scan SoundWire capabilities exposed by DSDT */ 1112 ret = hda_sdw_acpi_scan(sdev); 1113 if (ret < 0) { 1114 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 1115 goto skip_soundwire; 1116 } 1117 1118 link_mask = hdev->info.link_mask; 1119 if (!link_mask) { 1120 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n"); 1121 goto skip_soundwire; 1122 } 1123 1124 /* 1125 * probe/allocate SoundWire resources. 1126 * The hardware configuration takes place in hda_sdw_startup 1127 * after power rails are enabled. 1128 * It's entirely possible to have a mix of I2S/DMIC/SoundWire 1129 * devices, so we allocate the resources in all cases. 1130 */ 1131 ret = hda_sdw_probe(sdev); 1132 if (ret < 0) { 1133 dev_err(sdev->dev, "error: SoundWire probe error\n"); 1134 return ret; 1135 } 1136 1137 skip_soundwire: 1138 1139 /* create codec instances */ 1140 hda_codec_probe_bus(sdev); 1141 1142 if (!HDA_IDISP_CODEC(bus->codec_mask)) 1143 hda_codec_i915_display_power(sdev, false); 1144 1145 hda_bus_ml_put_all(bus); 1146 1147 return 0; 1148 } 1149 1150 static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context) 1151 { 1152 struct snd_sof_dev *sdev = context; 1153 1154 /* 1155 * Get global interrupt status. It includes all hardware interrupt 1156 * sources in the Intel HD Audio controller. 1157 */ 1158 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) & 1159 SOF_HDA_INTSTS_GIS) { 1160 1161 /* disable GIE interrupt */ 1162 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1163 SOF_HDA_INTCTL, 1164 SOF_HDA_INT_GLOBAL_EN, 1165 0); 1166 1167 return IRQ_WAKE_THREAD; 1168 } 1169 1170 return IRQ_NONE; 1171 } 1172 1173 static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context) 1174 { 1175 struct snd_sof_dev *sdev = context; 1176 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1177 1178 /* deal with streams and controller first */ 1179 if (hda_dsp_check_stream_irq(sdev)) { 1180 trace_sof_intel_hda_irq(sdev, "stream"); 1181 hda_dsp_stream_threaded_handler(irq, sdev); 1182 } 1183 1184 if (hda_check_ipc_irq(sdev)) { 1185 trace_sof_intel_hda_irq(sdev, "ipc"); 1186 sof_ops(sdev)->irq_thread(irq, sdev); 1187 } 1188 1189 if (hda_dsp_check_sdw_irq(sdev)) { 1190 trace_sof_intel_hda_irq(sdev, "sdw"); 1191 hda_dsp_sdw_thread(irq, hdev->sdw); 1192 } 1193 1194 if (hda_sdw_check_wakeen_irq(sdev)) { 1195 trace_sof_intel_hda_irq(sdev, "wakeen"); 1196 hda_sdw_process_wakeen(sdev); 1197 } 1198 1199 hda_codec_check_for_state_change(sdev); 1200 1201 /* enable GIE interrupt */ 1202 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1203 SOF_HDA_INTCTL, 1204 SOF_HDA_INT_GLOBAL_EN, 1205 SOF_HDA_INT_GLOBAL_EN); 1206 1207 return IRQ_HANDLED; 1208 } 1209 1210 int hda_dsp_probe_early(struct snd_sof_dev *sdev) 1211 { 1212 struct pci_dev *pci = to_pci_dev(sdev->dev); 1213 struct sof_intel_hda_dev *hdev; 1214 const struct sof_intel_dsp_desc *chip; 1215 int ret = 0; 1216 1217 if (!sdev->dspless_mode_selected) { 1218 /* 1219 * detect DSP by checking class/subclass/prog-id information 1220 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required 1221 * class=04 subclass 01 prog-if 00: DSP is present 1222 * (and may be required e.g. for DMIC or SSP support) 1223 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works 1224 */ 1225 if (pci->class == 0x040300) { 1226 dev_err(sdev->dev, "the DSP is not enabled on this platform, aborting probe\n"); 1227 return -ENODEV; 1228 } else if (pci->class != 0x040100 && pci->class != 0x040380) { 1229 dev_err(sdev->dev, "unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", 1230 pci->class); 1231 return -ENODEV; 1232 } 1233 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", 1234 pci->class); 1235 } 1236 1237 chip = get_chip_info(sdev->pdata); 1238 if (!chip) { 1239 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n", 1240 pci->device); 1241 ret = -EIO; 1242 goto err; 1243 } 1244 1245 sdev->num_cores = chip->cores_num; 1246 1247 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL); 1248 if (!hdev) 1249 return -ENOMEM; 1250 sdev->pdata->hw_pdata = hdev; 1251 hdev->desc = chip; 1252 ret = hda_init(sdev); 1253 1254 err: 1255 return ret; 1256 } 1257 1258 int hda_dsp_probe(struct snd_sof_dev *sdev) 1259 { 1260 struct pci_dev *pci = to_pci_dev(sdev->dev); 1261 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1262 const struct sof_intel_dsp_desc *chip; 1263 int ret = 0; 1264 1265 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1266 PLATFORM_DEVID_NONE, 1267 NULL, 0); 1268 if (IS_ERR(hdev->dmic_dev)) { 1269 dev_err(sdev->dev, "error: failed to create DMIC device\n"); 1270 return PTR_ERR(hdev->dmic_dev); 1271 } 1272 1273 /* 1274 * use position update IPC if either it is forced 1275 * or we don't have other choice 1276 */ 1277 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION) 1278 hdev->no_ipc_position = 0; 1279 #else 1280 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0; 1281 #endif 1282 1283 if (sdev->dspless_mode_selected) 1284 hdev->no_ipc_position = 1; 1285 1286 if (sdev->dspless_mode_selected) 1287 goto skip_dsp_setup; 1288 1289 /* DSP base */ 1290 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); 1291 if (!sdev->bar[HDA_DSP_BAR]) { 1292 dev_err(sdev->dev, "error: ioremap error\n"); 1293 ret = -ENXIO; 1294 goto hdac_bus_unmap; 1295 } 1296 1297 sdev->mmio_bar = HDA_DSP_BAR; 1298 sdev->mailbox_bar = HDA_DSP_BAR; 1299 skip_dsp_setup: 1300 1301 /* allow 64bit DMA address if supported by H/W */ 1302 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) { 1303 dev_dbg(sdev->dev, "DMA mask is 32 bit\n"); 1304 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1305 } 1306 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1307 1308 /* init streams */ 1309 ret = hda_dsp_stream_init(sdev); 1310 if (ret < 0) { 1311 dev_err(sdev->dev, "error: failed to init streams\n"); 1312 /* 1313 * not all errors are due to memory issues, but trying 1314 * to free everything does not harm 1315 */ 1316 goto free_streams; 1317 } 1318 1319 /* 1320 * register our IRQ 1321 * let's try to enable msi firstly 1322 * if it fails, use legacy interrupt mode 1323 * TODO: support msi multiple vectors 1324 */ 1325 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) { 1326 dev_info(sdev->dev, "use msi interrupt mode\n"); 1327 sdev->ipc_irq = pci_irq_vector(pci, 0); 1328 /* initialised to "false" by kzalloc() */ 1329 sdev->msi_enabled = true; 1330 } 1331 1332 if (!sdev->msi_enabled) { 1333 dev_info(sdev->dev, "use legacy interrupt mode\n"); 1334 /* 1335 * in IO-APIC mode, hda->irq and ipc_irq are using the same 1336 * irq number of pci->irq 1337 */ 1338 sdev->ipc_irq = pci->irq; 1339 } 1340 1341 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq); 1342 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler, 1343 hda_dsp_interrupt_thread, 1344 IRQF_SHARED, "AudioDSP", sdev); 1345 if (ret < 0) { 1346 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n", 1347 sdev->ipc_irq); 1348 goto free_irq_vector; 1349 } 1350 1351 pci_set_master(pci); 1352 synchronize_irq(pci->irq); 1353 1354 /* 1355 * clear TCSEL to clear playback on some HD Audio 1356 * codecs. PCI TCSEL is defined in the Intel manuals. 1357 */ 1358 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 1359 1360 /* init HDA capabilities */ 1361 ret = hda_init_caps(sdev); 1362 if (ret < 0) 1363 goto free_ipc_irq; 1364 1365 if (!sdev->dspless_mode_selected) { 1366 /* enable ppcap interrupt */ 1367 hda_dsp_ctrl_ppcap_enable(sdev, true); 1368 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 1369 1370 /* set default mailbox offset for FW ready message */ 1371 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET; 1372 1373 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work); 1374 } 1375 1376 chip = get_chip_info(sdev->pdata); 1377 if (chip && chip->hw_ip_version >= SOF_INTEL_ACE_2_0) { 1378 ret = hda_sdw_startup(sdev); 1379 if (ret < 0) { 1380 dev_err(sdev->dev, "could not startup SoundWire links\n"); 1381 goto disable_pp_cap; 1382 } 1383 1384 hda_sdw_int_enable(sdev, true); 1385 } 1386 1387 init_waitqueue_head(&hdev->waitq); 1388 1389 hdev->nhlt = intel_nhlt_init(sdev->dev); 1390 1391 return 0; 1392 1393 disable_pp_cap: 1394 if (!sdev->dspless_mode_selected) { 1395 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 1396 hda_dsp_ctrl_ppcap_enable(sdev, false); 1397 } 1398 free_ipc_irq: 1399 free_irq(sdev->ipc_irq, sdev); 1400 free_irq_vector: 1401 if (sdev->msi_enabled) 1402 pci_free_irq_vectors(pci); 1403 free_streams: 1404 hda_dsp_stream_free(sdev); 1405 /* dsp_unmap: not currently used */ 1406 if (!sdev->dspless_mode_selected) 1407 iounmap(sdev->bar[HDA_DSP_BAR]); 1408 hdac_bus_unmap: 1409 platform_device_unregister(hdev->dmic_dev); 1410 1411 return ret; 1412 } 1413 1414 void hda_dsp_remove(struct snd_sof_dev *sdev) 1415 { 1416 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1417 const struct sof_intel_dsp_desc *chip = hda->desc; 1418 struct pci_dev *pci = to_pci_dev(sdev->dev); 1419 struct nhlt_acpi_table *nhlt = hda->nhlt; 1420 1421 if (nhlt) 1422 intel_nhlt_free(nhlt); 1423 1424 if (!sdev->dspless_mode_selected) 1425 /* cancel any attempt for DSP D0I3 */ 1426 cancel_delayed_work_sync(&hda->d0i3_work); 1427 1428 hda_codec_device_remove(sdev); 1429 1430 hda_sdw_exit(sdev); 1431 1432 if (!IS_ERR_OR_NULL(hda->dmic_dev)) 1433 platform_device_unregister(hda->dmic_dev); 1434 1435 if (!sdev->dspless_mode_selected) { 1436 /* disable DSP IRQ */ 1437 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 1438 } 1439 1440 /* disable CIE and GIE interrupts */ 1441 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 1442 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0); 1443 1444 if (sdev->dspless_mode_selected) 1445 goto skip_disable_dsp; 1446 1447 /* no need to check for error as the DSP will be disabled anyway */ 1448 if (chip && chip->power_down_dsp) 1449 chip->power_down_dsp(sdev); 1450 1451 /* disable DSP */ 1452 hda_dsp_ctrl_ppcap_enable(sdev, false); 1453 1454 skip_disable_dsp: 1455 free_irq(sdev->ipc_irq, sdev); 1456 if (sdev->msi_enabled) 1457 pci_free_irq_vectors(pci); 1458 1459 hda_dsp_stream_free(sdev); 1460 1461 hda_bus_ml_free(sof_to_bus(sdev)); 1462 1463 if (!sdev->dspless_mode_selected) 1464 iounmap(sdev->bar[HDA_DSP_BAR]); 1465 } 1466 1467 void hda_dsp_remove_late(struct snd_sof_dev *sdev) 1468 { 1469 iounmap(sof_to_bus(sdev)->remap_addr); 1470 sof_hda_bus_exit(sdev); 1471 hda_codec_i915_exit(sdev); 1472 } 1473 1474 int hda_power_down_dsp(struct snd_sof_dev *sdev) 1475 { 1476 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1477 const struct sof_intel_dsp_desc *chip = hda->desc; 1478 1479 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 1480 } 1481 1482 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 1483 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1484 struct snd_soc_acpi_mach **mach) 1485 { 1486 struct hdac_bus *bus = sof_to_bus(sdev); 1487 struct snd_soc_acpi_mach_params *mach_params; 1488 struct snd_soc_acpi_mach *hda_mach; 1489 struct snd_sof_pdata *pdata = sdev->pdata; 1490 const char *tplg_filename; 1491 const char *idisp_str; 1492 int dmic_num = 0; 1493 int codec_num = 0; 1494 int ret; 1495 int i; 1496 1497 /* codec detection */ 1498 if (!bus->codec_mask) { 1499 dev_info(bus->dev, "no hda codecs found!\n"); 1500 } else { 1501 dev_info(bus->dev, "hda codecs found, mask %lx\n", 1502 bus->codec_mask); 1503 1504 for (i = 0; i < HDA_MAX_CODECS; i++) { 1505 if (bus->codec_mask & (1 << i)) 1506 codec_num++; 1507 } 1508 1509 /* 1510 * If no machine driver is found, then: 1511 * 1512 * generic hda machine driver can handle: 1513 * - one HDMI codec, and/or 1514 * - one external HDAudio codec 1515 */ 1516 if (!*mach && codec_num <= 2) { 1517 bool tplg_fixup; 1518 1519 hda_mach = snd_soc_acpi_intel_hda_machines; 1520 1521 dev_info(bus->dev, "using HDA machine driver %s now\n", 1522 hda_mach->drv_name); 1523 1524 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask)) 1525 idisp_str = "-idisp"; 1526 else 1527 idisp_str = ""; 1528 1529 /* topology: use the info from hda_machines */ 1530 if (pdata->tplg_filename) { 1531 tplg_fixup = false; 1532 tplg_filename = pdata->tplg_filename; 1533 } else { 1534 tplg_fixup = true; 1535 tplg_filename = hda_mach->sof_tplg_filename; 1536 } 1537 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num, 1538 tplg_fixup); 1539 if (ret < 0) 1540 return; 1541 1542 hda_mach->mach_params.dmic_num = dmic_num; 1543 pdata->tplg_filename = tplg_filename; 1544 1545 if (codec_num == 2 || 1546 (codec_num == 1 && !HDA_IDISP_CODEC(bus->codec_mask))) { 1547 /* 1548 * Prevent SoundWire links from starting when an external 1549 * HDaudio codec is used 1550 */ 1551 hda_mach->mach_params.link_mask = 0; 1552 } else { 1553 /* 1554 * Allow SoundWire links to start when no external HDaudio codec 1555 * was detected. This will not create a SoundWire card but 1556 * will help detect if any SoundWire codec reports as ATTACHED. 1557 */ 1558 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1559 1560 hda_mach->mach_params.link_mask = hdev->info.link_mask; 1561 } 1562 1563 *mach = hda_mach; 1564 } 1565 } 1566 1567 /* used by hda machine driver to create dai links */ 1568 if (*mach) { 1569 mach_params = &(*mach)->mach_params; 1570 mach_params->codec_mask = bus->codec_mask; 1571 mach_params->common_hdmi_codec_drv = true; 1572 } 1573 } 1574 #else 1575 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1576 struct snd_soc_acpi_mach **mach) 1577 { 1578 } 1579 #endif 1580 1581 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1582 1583 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1584 { 1585 struct snd_sof_pdata *pdata = sdev->pdata; 1586 const struct snd_soc_acpi_link_adr *link; 1587 struct snd_soc_acpi_mach *mach; 1588 struct sof_intel_hda_dev *hdev; 1589 u32 link_mask; 1590 int i; 1591 1592 hdev = pdata->hw_pdata; 1593 link_mask = hdev->info.link_mask; 1594 1595 /* 1596 * Select SoundWire machine driver if needed using the 1597 * alternate tables. This case deals with SoundWire-only 1598 * machines, for mixed cases with I2C/I2S the detection relies 1599 * on the HID list. 1600 */ 1601 if (link_mask) { 1602 for (mach = pdata->desc->alt_machines; 1603 mach && mach->link_mask; mach++) { 1604 /* 1605 * On some platforms such as Up Extreme all links 1606 * are enabled but only one link can be used by 1607 * external codec. Instead of exact match of two masks, 1608 * first check whether link_mask of mach is subset of 1609 * link_mask supported by hw and then go on searching 1610 * link_adr 1611 */ 1612 if (~link_mask & mach->link_mask) 1613 continue; 1614 1615 /* No need to match adr if there is no links defined */ 1616 if (!mach->links) 1617 break; 1618 1619 link = mach->links; 1620 for (i = 0; i < hdev->info.count && link->num_adr; 1621 i++, link++) { 1622 /* 1623 * Try next machine if any expected Slaves 1624 * are not found on this link. 1625 */ 1626 if (!snd_soc_acpi_sdw_link_slaves_found(sdev->dev, link, 1627 hdev->sdw->ids, 1628 hdev->sdw->num_slaves)) 1629 break; 1630 } 1631 /* Found if all Slaves are checked */ 1632 if (i == hdev->info.count || !link->num_adr) 1633 break; 1634 } 1635 if (mach && mach->link_mask) { 1636 int dmic_num = 0; 1637 bool tplg_fixup; 1638 const char *tplg_filename; 1639 1640 mach->mach_params.links = mach->links; 1641 mach->mach_params.link_mask = mach->link_mask; 1642 mach->mach_params.platform = dev_name(sdev->dev); 1643 1644 if (pdata->tplg_filename) { 1645 tplg_fixup = false; 1646 } else { 1647 tplg_fixup = true; 1648 tplg_filename = mach->sof_tplg_filename; 1649 } 1650 1651 /* 1652 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire 1653 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics 1654 * if all conditions are true: 1655 * a) 2 or fewer links are used by SoundWire 1656 * b) the NHLT table reports the presence of microphones 1657 */ 1658 if (hweight_long(mach->link_mask) <= 2) { 1659 int ret; 1660 1661 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "", 1662 &dmic_num, tplg_fixup); 1663 if (ret < 0) 1664 return NULL; 1665 } 1666 if (tplg_fixup) 1667 pdata->tplg_filename = tplg_filename; 1668 mach->mach_params.dmic_num = dmic_num; 1669 1670 dev_dbg(sdev->dev, 1671 "SoundWire machine driver %s topology %s\n", 1672 mach->drv_name, 1673 pdata->tplg_filename); 1674 1675 return mach; 1676 } 1677 1678 dev_info(sdev->dev, "No SoundWire machine driver found\n"); 1679 } 1680 1681 return NULL; 1682 } 1683 #else 1684 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1685 { 1686 return NULL; 1687 } 1688 #endif 1689 1690 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 1691 struct snd_sof_dev *sdev) 1692 { 1693 struct snd_sof_pdata *pdata = sdev->pdata; 1694 const struct sof_dev_desc *desc = pdata->desc; 1695 struct snd_soc_acpi_mach_params *mach_params; 1696 1697 mach_params = &mach->mach_params; 1698 mach_params->platform = dev_name(sdev->dev); 1699 if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) && 1700 sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC)) 1701 mach_params->num_dai_drivers = SOF_SKL_NUM_DAIS_NOCODEC; 1702 else 1703 mach_params->num_dai_drivers = desc->ops->num_drv; 1704 mach_params->dai_drivers = desc->ops->drv; 1705 } 1706 1707 static int check_tplg_quirk_mask(struct snd_soc_acpi_mach *mach) 1708 { 1709 u32 dmic_ssp_quirk; 1710 u32 codec_amp_name_quirk; 1711 1712 /* 1713 * In current implementation dmic and ssp quirks are designed for es8336 1714 * machine driver and could not be mixed with codec name and amp name 1715 * quirks. 1716 */ 1717 dmic_ssp_quirk = mach->tplg_quirk_mask & 1718 (SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER | SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER); 1719 codec_amp_name_quirk = mach->tplg_quirk_mask & 1720 (SND_SOC_ACPI_TPLG_INTEL_AMP_NAME | SND_SOC_ACPI_TPLG_INTEL_CODEC_NAME); 1721 1722 if (dmic_ssp_quirk && codec_amp_name_quirk) 1723 return -EINVAL; 1724 1725 return 0; 1726 } 1727 1728 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev) 1729 { 1730 u32 interface_mask = hda_get_interface_mask(sdev); 1731 struct snd_sof_pdata *sof_pdata = sdev->pdata; 1732 const struct sof_dev_desc *desc = sof_pdata->desc; 1733 struct snd_soc_acpi_mach *mach = NULL; 1734 enum snd_soc_acpi_intel_codec codec_type; 1735 const char *tplg_filename; 1736 const char *tplg_suffix; 1737 1738 /* Try I2S or DMIC if it is supported */ 1739 if (interface_mask & (BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC))) 1740 mach = snd_soc_acpi_find_machine(desc->machines); 1741 1742 if (mach) { 1743 bool add_extension = false; 1744 bool tplg_fixup = false; 1745 1746 /* 1747 * If tplg file name is overridden, use it instead of 1748 * the one set in mach table 1749 */ 1750 if (!sof_pdata->tplg_filename) { 1751 sof_pdata->tplg_filename = mach->sof_tplg_filename; 1752 tplg_fixup = true; 1753 } 1754 1755 /* 1756 * Checking quirk mask integrity; some quirk flags could not be 1757 * set concurrently. 1758 */ 1759 if (tplg_fixup && 1760 check_tplg_quirk_mask(mach)) { 1761 dev_err(sdev->dev, "Invalid tplg quirk mask 0x%x\n", 1762 mach->tplg_quirk_mask); 1763 return NULL; 1764 } 1765 1766 /* report to machine driver if any DMICs are found */ 1767 mach->mach_params.dmic_num = check_dmic_num(sdev); 1768 1769 if (tplg_fixup && 1770 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER && 1771 mach->mach_params.dmic_num) { 1772 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1773 "%s%s%d%s", 1774 sof_pdata->tplg_filename, 1775 "-dmic", 1776 mach->mach_params.dmic_num, 1777 "ch"); 1778 if (!tplg_filename) 1779 return NULL; 1780 1781 sof_pdata->tplg_filename = tplg_filename; 1782 add_extension = true; 1783 } 1784 1785 if (mach->link_mask) { 1786 mach->mach_params.links = mach->links; 1787 mach->mach_params.link_mask = mach->link_mask; 1788 } 1789 1790 /* report SSP link mask to machine driver */ 1791 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev); 1792 1793 if (tplg_fixup && 1794 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER && 1795 mach->mach_params.i2s_link_mask) { 1796 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 1797 int ssp_num; 1798 int mclk_mask; 1799 1800 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 && 1801 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB)) 1802 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n"); 1803 1804 /* fls returns 1-based results, SSPs indices are 0-based */ 1805 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1; 1806 1807 if (ssp_num >= chip->ssp_count) { 1808 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n", 1809 ssp_num, chip->ssp_count); 1810 return NULL; 1811 } 1812 1813 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1814 "%s%s%d", 1815 sof_pdata->tplg_filename, 1816 "-ssp", 1817 ssp_num); 1818 if (!tplg_filename) 1819 return NULL; 1820 1821 sof_pdata->tplg_filename = tplg_filename; 1822 add_extension = true; 1823 1824 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); 1825 1826 if (mclk_mask < 0) { 1827 dev_err(sdev->dev, "Invalid MCLK configuration\n"); 1828 return NULL; 1829 } 1830 1831 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); 1832 1833 if (mclk_mask) { 1834 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); 1835 sdev->mclk_id_override = true; 1836 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; 1837 } 1838 } 1839 1840 codec_type = snd_soc_acpi_intel_detect_amp_type(sdev->dev); 1841 1842 if (tplg_fixup && 1843 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_AMP_NAME && 1844 codec_type != CODEC_NONE) { 1845 tplg_suffix = snd_soc_acpi_intel_get_amp_tplg_suffix(codec_type); 1846 if (!tplg_suffix) { 1847 dev_err(sdev->dev, "no tplg suffix found, amp %d\n", 1848 codec_type); 1849 return NULL; 1850 } 1851 1852 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1853 "%s-%s", 1854 sof_pdata->tplg_filename, 1855 tplg_suffix); 1856 if (!tplg_filename) 1857 return NULL; 1858 1859 sof_pdata->tplg_filename = tplg_filename; 1860 add_extension = true; 1861 } 1862 1863 codec_type = snd_soc_acpi_intel_detect_codec_type(sdev->dev); 1864 1865 if (tplg_fixup && 1866 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_CODEC_NAME && 1867 codec_type != CODEC_NONE) { 1868 tplg_suffix = snd_soc_acpi_intel_get_codec_tplg_suffix(codec_type); 1869 if (!tplg_suffix) { 1870 dev_err(sdev->dev, "no tplg suffix found, codec %d\n", 1871 codec_type); 1872 return NULL; 1873 } 1874 1875 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1876 "%s-%s", 1877 sof_pdata->tplg_filename, 1878 tplg_suffix); 1879 if (!tplg_filename) 1880 return NULL; 1881 1882 sof_pdata->tplg_filename = tplg_filename; 1883 add_extension = true; 1884 } 1885 1886 if (tplg_fixup && add_extension) { 1887 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1888 "%s%s", 1889 sof_pdata->tplg_filename, 1890 ".tplg"); 1891 if (!tplg_filename) 1892 return NULL; 1893 1894 sof_pdata->tplg_filename = tplg_filename; 1895 } 1896 1897 /* check if mclk_id should be modified from topology defaults */ 1898 if (mclk_id_override >= 0) { 1899 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override); 1900 sdev->mclk_id_override = true; 1901 sdev->mclk_id_quirk = mclk_id_override; 1902 } 1903 } 1904 1905 /* If I2S fails, try SoundWire if it is supported */ 1906 if (!mach && (interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1907 mach = hda_sdw_machine_select(sdev); 1908 1909 /* 1910 * Choose HDA generic machine driver if mach is NULL. 1911 * Otherwise, set certain mach params. 1912 */ 1913 hda_generic_machine_select(sdev, &mach); 1914 if (!mach) 1915 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 1916 1917 return mach; 1918 } 1919 1920 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1921 { 1922 int ret; 1923 1924 ret = snd_intel_dsp_driver_probe(pci); 1925 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1926 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n"); 1927 return -ENODEV; 1928 } 1929 1930 return sof_pci_probe(pci, pci_id); 1931 } 1932 EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON); 1933 1934 int hda_register_clients(struct snd_sof_dev *sdev) 1935 { 1936 return hda_probes_register(sdev); 1937 } 1938 1939 void hda_unregister_clients(struct snd_sof_dev *sdev) 1940 { 1941 hda_probes_unregister(sdev); 1942 } 1943 1944 MODULE_LICENSE("Dual BSD/GPL"); 1945 MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); 1946 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC); 1947 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915); 1948 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1949 MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI); 1950 MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT); 1951 MODULE_IMPORT_NS(SOUNDWIRE_INTEL); 1952 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK); 1953 MODULE_IMPORT_NS(SND_SOC_ACPI_INTEL_MATCH); 1954