1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <sound/hdaudio_ext.h> 19 #include <sound/hda_register.h> 20 #include <sound/sof.h> 21 #include <trace/events/sof_intel.h> 22 #include "../ops.h" 23 #include "../sof-audio.h" 24 #include "../ipc4-priv.h" 25 #include "hda.h" 26 27 int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 28 module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 29 MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 30 EXPORT_SYMBOL_NS(sof_hda_position_quirk, "SND_SOC_SOF_INTEL_HDA_COMMON"); 31 32 #define HDA_LTRP_GB_VALUE_US 95 33 34 static inline const char *hda_hstream_direction_str(struct hdac_stream *hstream) 35 { 36 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) 37 return "Playback"; 38 else 39 return "Capture"; 40 } 41 42 static char *hda_hstream_dbg_get_stream_info_str(struct hdac_stream *hstream) 43 { 44 struct snd_soc_pcm_runtime *rtd; 45 46 if (hstream->substream) 47 rtd = snd_soc_substream_to_rtd(hstream->substream); 48 else if (hstream->cstream) 49 rtd = hstream->cstream->private_data; 50 else 51 /* Non audio DMA user, like dma-trace */ 52 return kasprintf(GFP_KERNEL, "-- (%s, stream_tag: %u)", 53 hda_hstream_direction_str(hstream), 54 hstream->stream_tag); 55 56 return kasprintf(GFP_KERNEL, "dai_link \"%s\" (%s, stream_tag: %u)", 57 rtd->dai_link->name, hda_hstream_direction_str(hstream), 58 hstream->stream_tag); 59 } 60 61 /* 62 * set up one of BDL entries for a stream 63 */ 64 static int hda_setup_bdle(struct snd_sof_dev *sdev, 65 struct snd_dma_buffer *dmab, 66 struct hdac_stream *hstream, 67 struct sof_intel_dsp_bdl **bdlp, 68 int offset, int size, int ioc) 69 { 70 struct hdac_bus *bus = sof_to_bus(sdev); 71 struct sof_intel_dsp_bdl *bdl = *bdlp; 72 73 while (size > 0) { 74 dma_addr_t addr; 75 int chunk; 76 77 if (hstream->frags >= HDA_DSP_MAX_BDL_ENTRIES) { 78 dev_err(sdev->dev, "error: stream frags exceeded\n"); 79 return -EINVAL; 80 } 81 82 addr = snd_sgbuf_get_addr(dmab, offset); 83 /* program BDL addr */ 84 bdl->addr_l = cpu_to_le32(lower_32_bits(addr)); 85 bdl->addr_h = cpu_to_le32(upper_32_bits(addr)); 86 /* program BDL size */ 87 chunk = snd_sgbuf_get_chunk_size(dmab, offset, size); 88 /* one BDLE should not cross 4K boundary */ 89 if (bus->align_bdle_4k) { 90 u32 remain = 0x1000 - (offset & 0xfff); 91 92 if (chunk > remain) 93 chunk = remain; 94 } 95 bdl->size = cpu_to_le32(chunk); 96 /* only program IOC when the whole segment is processed */ 97 size -= chunk; 98 bdl->ioc = (size || !ioc) ? 0 : cpu_to_le32(0x01); 99 bdl++; 100 hstream->frags++; 101 offset += chunk; 102 } 103 104 *bdlp = bdl; 105 return offset; 106 } 107 108 /* 109 * set up Buffer Descriptor List (BDL) for host memory transfer 110 * BDL describes the location of the individual buffers and is little endian. 111 */ 112 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 113 struct snd_dma_buffer *dmab, 114 struct hdac_stream *hstream) 115 { 116 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 117 struct sof_intel_dsp_bdl *bdl; 118 int i, offset, period_bytes, periods; 119 int remain, ioc; 120 121 period_bytes = hstream->period_bytes; 122 dev_dbg(sdev->dev, "period_bytes: %#x, bufsize: %#x\n", period_bytes, 123 hstream->bufsize); 124 125 if (!period_bytes) { 126 unsigned int chunk_size; 127 128 chunk_size = snd_sgbuf_get_chunk_size(dmab, 0, hstream->bufsize); 129 130 period_bytes = hstream->bufsize; 131 132 /* 133 * HDA spec demands that the LVI value must be at least one 134 * before the DMA operation can begin. This means that there 135 * must be at least two BDLE present for the transfer. 136 * 137 * If the buffer is not a single continuous area then the 138 * hda_setup_bdle() will create multiple BDLEs for each segment. 139 * If the memory is a single continuous area, force it to be 140 * split into two 'periods', otherwise the transfer will be 141 * split to multiple BDLE for each chunk in hda_setup_bdle() 142 * 143 * Note: period_bytes == 0 can only happen for firmware or 144 * library loading. The data size is 4K aligned, which ensures 145 * that the second chunk's start address will be 128-byte 146 * aligned. 147 */ 148 if (chunk_size == hstream->bufsize) 149 period_bytes /= 2; 150 } 151 152 periods = hstream->bufsize / period_bytes; 153 154 dev_dbg(sdev->dev, "periods: %d\n", periods); 155 156 remain = hstream->bufsize % period_bytes; 157 if (remain) 158 periods++; 159 160 /* program the initial BDL entries */ 161 bdl = (struct sof_intel_dsp_bdl *)hstream->bdl.area; 162 offset = 0; 163 hstream->frags = 0; 164 165 /* 166 * set IOC if don't use position IPC 167 * and period_wakeup needed. 168 */ 169 ioc = hda->no_ipc_position ? 170 !hstream->no_period_wakeup : 0; 171 172 for (i = 0; i < periods; i++) { 173 if (i == (periods - 1) && remain) 174 /* set the last small entry */ 175 offset = hda_setup_bdle(sdev, dmab, 176 hstream, &bdl, offset, 177 remain, 0); 178 else 179 offset = hda_setup_bdle(sdev, dmab, 180 hstream, &bdl, offset, 181 period_bytes, ioc); 182 } 183 184 return offset; 185 } 186 187 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 188 struct hdac_ext_stream *hext_stream, 189 int enable, u32 size) 190 { 191 struct hdac_stream *hstream = &hext_stream->hstream; 192 u32 mask; 193 194 if (!sdev->bar[HDA_DSP_SPIB_BAR]) { 195 dev_err(sdev->dev, "error: address of spib capability is NULL\n"); 196 return -EINVAL; 197 } 198 199 mask = (1 << hstream->index); 200 201 /* Reset the spib_addr before disabling SPIB */ 202 if (!enable) 203 sof_io_write(sdev, hstream->spib_addr, 0); 204 205 /* enable/disable SPIB for the stream */ 206 snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR, 207 SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask, 208 enable << hstream->index); 209 210 /* set the SPIB value */ 211 if (enable) 212 sof_io_write(sdev, hstream->spib_addr, size); 213 214 return 0; 215 } 216 217 /* get next unused stream */ 218 static struct hdac_ext_stream * 219 _hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags, bool pair) 220 { 221 const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata); 222 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 223 struct hdac_bus *bus = sof_to_bus(sdev); 224 struct sof_intel_hda_stream *hda_stream; 225 struct hdac_ext_stream *hext_stream = NULL; 226 struct hdac_stream *s; 227 228 spin_lock_irq(&bus->reg_lock); 229 230 /* get an unused stream */ 231 list_for_each_entry(s, &bus->stream_list, list) { 232 if (s->direction == direction && !s->opened) { 233 hext_stream = stream_to_hdac_ext_stream(s); 234 hda_stream = container_of(hext_stream, 235 struct sof_intel_hda_stream, 236 hext_stream); 237 /* check if the host DMA channel is reserved */ 238 if (hda_stream->host_reserved) 239 continue; 240 241 if (pair && hext_stream->link_locked) 242 continue; 243 244 s->opened = true; 245 246 if (pair) 247 hext_stream->link_locked = true; 248 249 break; 250 } 251 } 252 253 spin_unlock_irq(&bus->reg_lock); 254 255 /* stream found ? */ 256 if (!hext_stream) { 257 dev_err(sdev->dev, "error: no free %s streams\n", snd_pcm_direction_name(direction)); 258 return hext_stream; 259 } 260 261 hda_stream->flags = flags; 262 263 /* 264 * Prevent DMI Link L1 entry for streams that don't support it. 265 * Workaround to address a known issue with host DMA that results 266 * in xruns during pause/release in capture scenarios. This is not needed for the ACE IP. 267 */ 268 if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 && 269 !(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) { 270 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 271 HDA_VS_INTEL_EM2, 272 HDA_VS_INTEL_EM2_L1SEN, 0); 273 hda->l1_disabled = true; 274 } 275 276 return hext_stream; 277 } 278 279 struct hdac_ext_stream * 280 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags) 281 { 282 return _hda_dsp_stream_get(sdev, direction, flags, false); 283 } 284 285 struct hdac_ext_stream * 286 hda_dsp_stream_pair_get(struct snd_sof_dev *sdev, int direction, u32 flags) 287 { 288 return _hda_dsp_stream_get(sdev, direction, flags, true); 289 } 290 291 /* free a stream */ 292 static int _hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag, bool pair) 293 { 294 const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata); 295 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 296 struct hdac_bus *bus = sof_to_bus(sdev); 297 struct sof_intel_hda_stream *hda_stream; 298 struct hdac_ext_stream *hext_stream; 299 struct hdac_ext_stream *link_stream; 300 struct hdac_stream *s; 301 bool dmi_l1_enable = true; 302 bool found = false; 303 304 spin_lock_irq(&bus->reg_lock); 305 306 /* 307 * close stream matching the stream tag and check if there are any open streams 308 * that are DMI L1 incompatible. 309 */ 310 list_for_each_entry(s, &bus->stream_list, list) { 311 hext_stream = stream_to_hdac_ext_stream(s); 312 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, hext_stream); 313 314 if (!s->opened) 315 continue; 316 317 if (s->direction == direction && s->stream_tag == stream_tag) { 318 s->opened = false; 319 found = true; 320 if (pair) 321 link_stream = hext_stream; 322 } else if (!(hda_stream->flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) { 323 dmi_l1_enable = false; 324 } 325 } 326 327 spin_unlock_irq(&bus->reg_lock); 328 329 /* Enable DMI L1 if permitted */ 330 if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 && dmi_l1_enable) { 331 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, 332 HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN); 333 hda->l1_disabled = false; 334 } 335 336 if (!found) { 337 dev_err(sdev->dev, "%s: stream_tag %d not opened!\n", 338 __func__, stream_tag); 339 return -ENODEV; 340 } 341 342 if (pair) 343 snd_hdac_ext_stream_release(link_stream, HDAC_EXT_STREAM_TYPE_LINK); 344 345 return 0; 346 } 347 348 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag) 349 { 350 return _hda_dsp_stream_put(sdev, direction, stream_tag, false); 351 } 352 353 int hda_dsp_stream_pair_put(struct snd_sof_dev *sdev, int direction, int stream_tag) 354 { 355 return _hda_dsp_stream_put(sdev, direction, stream_tag, true); 356 } 357 358 static int hda_dsp_stream_reset(struct snd_sof_dev *sdev, struct hdac_stream *hstream) 359 { 360 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 361 int timeout = HDA_DSP_STREAM_RESET_TIMEOUT; 362 u32 val; 363 364 /* enter stream reset */ 365 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 366 SOF_STREAM_SD_OFFSET_CRST); 367 do { 368 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset); 369 if (val & SOF_STREAM_SD_OFFSET_CRST) 370 break; 371 } while (--timeout); 372 if (timeout == 0) { 373 dev_err(sdev->dev, "timeout waiting for stream reset\n"); 374 return -ETIMEDOUT; 375 } 376 377 timeout = HDA_DSP_STREAM_RESET_TIMEOUT; 378 379 /* exit stream reset and wait to read a zero before reading any other register */ 380 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 0x0); 381 382 /* wait for hardware to report that stream is out of reset */ 383 udelay(3); 384 do { 385 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset); 386 if ((val & SOF_STREAM_SD_OFFSET_CRST) == 0) 387 break; 388 } while (--timeout); 389 if (timeout == 0) { 390 dev_err(sdev->dev, "timeout waiting for stream to exit reset\n"); 391 return -ETIMEDOUT; 392 } 393 394 return 0; 395 } 396 397 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 398 struct hdac_ext_stream *hext_stream, int cmd) 399 { 400 struct hdac_stream *hstream = &hext_stream->hstream; 401 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 402 u32 dma_start = SOF_HDA_SD_CTL_DMA_START; 403 int ret = 0; 404 u32 run; 405 406 /* cmd must be for audio stream */ 407 switch (cmd) { 408 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 409 if (!sdev->dspless_mode_selected) 410 break; 411 fallthrough; 412 case SNDRV_PCM_TRIGGER_START: 413 if (hstream->running) 414 break; 415 416 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 417 1 << hstream->index, 418 1 << hstream->index); 419 420 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 421 sd_offset, 422 SOF_HDA_SD_CTL_DMA_START | 423 SOF_HDA_CL_DMA_SD_INT_MASK, 424 SOF_HDA_SD_CTL_DMA_START | 425 SOF_HDA_CL_DMA_SD_INT_MASK); 426 427 ret = snd_sof_dsp_read_poll_timeout(sdev, 428 HDA_DSP_HDA_BAR, 429 sd_offset, run, 430 ((run & dma_start) == dma_start), 431 HDA_DSP_REG_POLL_INTERVAL_US, 432 HDA_DSP_STREAM_RUN_TIMEOUT); 433 434 if (ret >= 0) 435 hstream->running = true; 436 437 break; 438 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 439 if (!sdev->dspless_mode_selected) 440 break; 441 fallthrough; 442 case SNDRV_PCM_TRIGGER_SUSPEND: 443 case SNDRV_PCM_TRIGGER_STOP: 444 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 445 sd_offset, 446 SOF_HDA_SD_CTL_DMA_START | 447 SOF_HDA_CL_DMA_SD_INT_MASK, 0x0); 448 449 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR, 450 sd_offset, run, 451 !(run & dma_start), 452 HDA_DSP_REG_POLL_INTERVAL_US, 453 HDA_DSP_STREAM_RUN_TIMEOUT); 454 455 if (ret >= 0) { 456 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 457 sd_offset + SOF_HDA_ADSP_REG_SD_STS, 458 SOF_HDA_CL_DMA_SD_INT_MASK); 459 460 hstream->running = false; 461 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 462 SOF_HDA_INTCTL, 463 1 << hstream->index, 0x0); 464 } 465 break; 466 default: 467 dev_err(sdev->dev, "error: unknown command: %d\n", cmd); 468 return -EINVAL; 469 } 470 471 if (ret < 0) { 472 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream); 473 474 dev_err(sdev->dev, 475 "%s: cmd %d on %s: timeout on STREAM_SD_OFFSET read\n", 476 __func__, cmd, stream_name ? stream_name : "unknown stream"); 477 kfree(stream_name); 478 } 479 480 return ret; 481 } 482 483 /* minimal recommended programming for ICCMAX stream */ 484 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, 485 struct snd_dma_buffer *dmab, 486 struct snd_pcm_hw_params *params) 487 { 488 struct hdac_stream *hstream; 489 int sd_offset; 490 int ret; 491 u32 mask; 492 493 if (!hext_stream) { 494 dev_err(sdev->dev, "error: no stream available\n"); 495 return -ENODEV; 496 } 497 498 hstream = &hext_stream->hstream; 499 sd_offset = SOF_STREAM_SD_OFFSET(hstream); 500 mask = 0x1 << hstream->index; 501 502 if (!dmab) { 503 dev_err(sdev->dev, "error: no dma buffer allocated!\n"); 504 return -ENODEV; 505 } 506 507 if (hstream->posbuf) 508 *hstream->posbuf = 0; 509 510 /* reset BDL address */ 511 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 512 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 513 0x0); 514 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 515 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 516 0x0); 517 518 hstream->frags = 0; 519 520 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream); 521 if (ret < 0) { 522 dev_err(sdev->dev, "error: set up of BDL failed\n"); 523 return ret; 524 } 525 526 /* program BDL address */ 527 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 528 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 529 (u32)hstream->bdl.addr); 530 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 531 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 532 upper_32_bits(hstream->bdl.addr)); 533 534 /* program cyclic buffer length */ 535 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 536 sd_offset + SOF_HDA_ADSP_REG_SD_CBL, 537 hstream->bufsize); 538 539 /* program last valid index */ 540 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 541 sd_offset + SOF_HDA_ADSP_REG_SD_LVI, 542 0xffff, (hstream->frags - 1)); 543 544 /* decouple host and link DMA, enable DSP features */ 545 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 546 mask, mask); 547 548 /* Follow HW recommendation to set the guardband value to 95us during FW boot */ 549 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP, 550 HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US); 551 552 /* start DMA */ 553 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 554 SOF_HDA_SD_CTL_DMA_START, SOF_HDA_SD_CTL_DMA_START); 555 556 return 0; 557 } 558 559 /* 560 * prepare for common hdac registers settings, for both code loader 561 * and normal stream. 562 */ 563 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 564 struct hdac_ext_stream *hext_stream, 565 struct snd_dma_buffer *dmab, 566 struct snd_pcm_hw_params *params) 567 { 568 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 569 struct hdac_bus *bus = sof_to_bus(sdev); 570 struct hdac_stream *hstream; 571 int sd_offset, ret; 572 u32 dma_start = SOF_HDA_SD_CTL_DMA_START; 573 u32 mask; 574 u32 run; 575 576 if (!hext_stream) { 577 dev_err(sdev->dev, "error: no stream available\n"); 578 return -ENODEV; 579 } 580 581 if (!dmab) { 582 dev_err(sdev->dev, "error: no dma buffer allocated!\n"); 583 return -ENODEV; 584 } 585 586 hstream = &hext_stream->hstream; 587 sd_offset = SOF_STREAM_SD_OFFSET(hstream); 588 mask = BIT(hstream->index); 589 590 /* decouple host and link DMA if the DSP is used */ 591 if (!sdev->dspless_mode_selected) 592 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 593 mask, mask); 594 595 /* clear stream status */ 596 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 597 SOF_HDA_CL_DMA_SD_INT_MASK | 598 SOF_HDA_SD_CTL_DMA_START, 0); 599 600 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR, 601 sd_offset, run, 602 !(run & dma_start), 603 HDA_DSP_REG_POLL_INTERVAL_US, 604 HDA_DSP_STREAM_RUN_TIMEOUT); 605 606 if (ret < 0) { 607 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream); 608 609 dev_err(sdev->dev, 610 "%s: on %s: timeout on STREAM_SD_OFFSET read1\n", 611 __func__, stream_name ? stream_name : "unknown stream"); 612 kfree(stream_name); 613 return ret; 614 } 615 616 /* Host DMA is not running */ 617 hstream->running = false; 618 619 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 620 sd_offset + SOF_HDA_ADSP_REG_SD_STS, 621 SOF_HDA_CL_DMA_SD_INT_MASK, 622 SOF_HDA_CL_DMA_SD_INT_MASK); 623 624 /* stream reset */ 625 ret = hda_dsp_stream_reset(sdev, hstream); 626 if (ret < 0) 627 return ret; 628 629 if (hstream->posbuf) 630 *hstream->posbuf = 0; 631 632 /* reset BDL address */ 633 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 634 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 635 0x0); 636 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 637 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 638 0x0); 639 640 /* clear stream status */ 641 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 642 SOF_HDA_CL_DMA_SD_INT_MASK | 643 SOF_HDA_SD_CTL_DMA_START, 0); 644 645 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR, 646 sd_offset, run, 647 !(run & dma_start), 648 HDA_DSP_REG_POLL_INTERVAL_US, 649 HDA_DSP_STREAM_RUN_TIMEOUT); 650 651 if (ret < 0) { 652 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream); 653 654 dev_err(sdev->dev, 655 "%s: on %s: timeout on STREAM_SD_OFFSET read1\n", 656 __func__, stream_name ? stream_name : "unknown stream"); 657 kfree(stream_name); 658 return ret; 659 } 660 661 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 662 sd_offset + SOF_HDA_ADSP_REG_SD_STS, 663 SOF_HDA_CL_DMA_SD_INT_MASK, 664 SOF_HDA_CL_DMA_SD_INT_MASK); 665 666 hstream->frags = 0; 667 668 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream); 669 if (ret < 0) { 670 dev_err(sdev->dev, "error: set up of BDL failed\n"); 671 return ret; 672 } 673 674 /* program stream tag to set up stream descriptor for DMA */ 675 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 676 SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK, 677 hstream->stream_tag << 678 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT); 679 680 /* program cyclic buffer length */ 681 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 682 sd_offset + SOF_HDA_ADSP_REG_SD_CBL, 683 hstream->bufsize); 684 685 /* 686 * Recommended hardware programming sequence for HDAudio DMA format 687 * on earlier platforms - this is not needed on newer platforms 688 * 689 * 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit 690 * for corresponding stream index before the time of writing 691 * format to SDxFMT register. 692 * 2. Write SDxFMT 693 * 3. Set PPCTL.PROCEN bit for corresponding stream index to 694 * enable decoupled mode 695 */ 696 697 if (!sdev->dspless_mode_selected && (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK)) 698 /* couple host and link DMA, disable DSP features */ 699 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 700 mask, 0); 701 702 /* program stream format */ 703 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 704 sd_offset + 705 SOF_HDA_ADSP_REG_SD_FORMAT, 706 0xffff, hstream->format_val); 707 708 if (!sdev->dspless_mode_selected && (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK)) 709 /* decouple host and link DMA, enable DSP features */ 710 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 711 mask, mask); 712 713 /* program last valid index */ 714 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 715 sd_offset + SOF_HDA_ADSP_REG_SD_LVI, 716 0xffff, (hstream->frags - 1)); 717 718 /* program BDL address */ 719 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 720 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 721 (u32)hstream->bdl.addr); 722 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 723 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 724 upper_32_bits(hstream->bdl.addr)); 725 726 /* enable position buffer, if needed */ 727 if (bus->use_posbuf && bus->posbuf.addr && 728 !(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE) 729 & SOF_HDA_ADSP_DPLBASE_ENABLE)) { 730 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE, 731 upper_32_bits(bus->posbuf.addr)); 732 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE, 733 (u32)bus->posbuf.addr | 734 SOF_HDA_ADSP_DPLBASE_ENABLE); 735 } 736 737 /* set interrupt enable bits */ 738 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 739 SOF_HDA_CL_DMA_SD_INT_MASK, 740 SOF_HDA_CL_DMA_SD_INT_MASK); 741 742 /* read FIFO size */ 743 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) { 744 hstream->fifo_size = 745 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 746 sd_offset + 747 SOF_HDA_ADSP_REG_SD_FIFOSIZE); 748 hstream->fifo_size &= SOF_HDA_SD_FIFOSIZE_FIFOS_MASK; 749 hstream->fifo_size += 1; 750 } else { 751 hstream->fifo_size = 0; 752 } 753 754 return ret; 755 } 756 757 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 758 struct snd_pcm_substream *substream) 759 { 760 struct hdac_stream *hstream = substream->runtime->private_data; 761 struct hdac_ext_stream *hext_stream = container_of(hstream, 762 struct hdac_ext_stream, 763 hstream); 764 int ret; 765 766 ret = hda_dsp_stream_reset(sdev, hstream); 767 if (ret < 0) 768 return ret; 769 770 if (!sdev->dspless_mode_selected) { 771 struct hdac_bus *bus = sof_to_bus(sdev); 772 u32 mask = BIT(hstream->index); 773 774 guard(spinlock_irq)(&bus->reg_lock); 775 776 /* couple host and link DMA if link DMA channel is idle */ 777 if (!hext_stream->link_locked) 778 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, 779 SOF_HDA_REG_PP_PPCTL, mask, 0); 780 } 781 782 hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0); 783 784 hstream->substream = NULL; 785 786 return 0; 787 } 788 EXPORT_SYMBOL_NS(hda_dsp_stream_hw_free, "SND_SOC_SOF_INTEL_HDA_COMMON"); 789 790 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev) 791 { 792 struct hdac_bus *bus = sof_to_bus(sdev); 793 bool ret = false; 794 u32 status; 795 796 /* The function can be called at irq thread, so use spin_lock_irq */ 797 guard(spinlock_irq)(&bus->reg_lock); 798 799 status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 800 801 trace_sof_intel_hda_dsp_check_stream_irq(sdev, status); 802 803 /* if Register inaccessible, ignore it.*/ 804 if (status != 0xffffffff) 805 ret = true; 806 807 return ret; 808 } 809 EXPORT_SYMBOL_NS(hda_dsp_check_stream_irq, "SND_SOC_SOF_INTEL_HDA_COMMON"); 810 811 static void 812 hda_dsp_compr_bytes_transferred(struct hdac_stream *hstream, int direction) 813 { 814 u64 buffer_size = hstream->bufsize; 815 u64 prev_pos, pos, num_bytes; 816 817 div64_u64_rem(hstream->curr_pos, buffer_size, &prev_pos); 818 pos = hda_dsp_stream_get_position(hstream, direction, false); 819 820 if (pos < prev_pos) 821 num_bytes = (buffer_size - prev_pos) + pos; 822 else 823 num_bytes = pos - prev_pos; 824 825 hstream->curr_pos += num_bytes; 826 } 827 828 static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status) 829 { 830 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus); 831 struct hdac_stream *s; 832 bool active = false; 833 u32 sd_status; 834 835 list_for_each_entry(s, &bus->stream_list, list) { 836 if (status & BIT(s->index) && s->opened) { 837 sd_status = readb(s->sd_addr + SOF_HDA_ADSP_REG_SD_STS); 838 839 trace_sof_intel_hda_dsp_stream_status(bus->dev, s, sd_status); 840 841 writeb(sd_status, s->sd_addr + SOF_HDA_ADSP_REG_SD_STS); 842 843 active = true; 844 if (!s->running) 845 continue; 846 if ((sd_status & SOF_HDA_CL_DMA_SD_INT_COMPLETE) == 0) 847 continue; 848 if (!s->substream && !s->cstream) { 849 /* 850 * when no substream is found, the DMA may used for code loading 851 * or data transfers which can rely on wait_for_completion() 852 */ 853 struct sof_intel_hda_stream *hda_stream; 854 struct hdac_ext_stream *hext_stream; 855 856 hext_stream = stream_to_hdac_ext_stream(s); 857 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, 858 hext_stream); 859 860 complete(&hda_stream->ioc); 861 continue; 862 } 863 864 /* Inform ALSA only if the IPC position is not used */ 865 if (s->substream && sof_hda->no_ipc_position) { 866 snd_sof_pcm_period_elapsed(s->substream); 867 } else if (s->cstream) { 868 hda_dsp_compr_bytes_transferred(s, s->cstream->direction); 869 snd_compr_fragment_elapsed(s->cstream); 870 } 871 } 872 } 873 874 return active; 875 } 876 877 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context) 878 { 879 struct snd_sof_dev *sdev = context; 880 struct hdac_bus *bus = sof_to_bus(sdev); 881 bool active; 882 u32 status; 883 int i; 884 885 /* 886 * Loop 10 times to handle missed interrupts caused by 887 * unsolicited responses from the codec 888 */ 889 for (i = 0, active = true; i < 10 && active; i++) { 890 guard(spinlock_irq)(&bus->reg_lock); 891 892 status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 893 894 /* check streams */ 895 active = hda_dsp_stream_check(bus, status); 896 897 /* check and clear RIRB interrupt */ 898 if (status & AZX_INT_CTRL_EN) { 899 active |= hda_codec_check_rirb_status(sdev); 900 } 901 } 902 903 return IRQ_HANDLED; 904 } 905 EXPORT_SYMBOL_NS(hda_dsp_stream_threaded_handler, "SND_SOC_SOF_INTEL_HDA_COMMON"); 906 907 int hda_dsp_stream_init(struct snd_sof_dev *sdev) 908 { 909 struct hdac_bus *bus = sof_to_bus(sdev); 910 struct hdac_ext_stream *hext_stream; 911 struct hdac_stream *hstream; 912 struct pci_dev *pci = to_pci_dev(sdev->dev); 913 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus); 914 int sd_offset; 915 int i, num_playback, num_capture, num_total, ret; 916 u32 gcap; 917 918 gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP); 919 dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap); 920 921 /* get stream count from GCAP */ 922 num_capture = (gcap >> 8) & 0x0f; 923 num_playback = (gcap >> 12) & 0x0f; 924 num_total = num_playback + num_capture; 925 926 dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n", 927 num_playback, num_capture); 928 929 if (num_playback >= SOF_HDA_PLAYBACK_STREAMS) { 930 dev_err(sdev->dev, "error: too many playback streams %d\n", 931 num_playback); 932 return -EINVAL; 933 } 934 935 if (num_capture >= SOF_HDA_CAPTURE_STREAMS) { 936 dev_err(sdev->dev, "error: too many capture streams %d\n", 937 num_capture); 938 return -EINVAL; 939 } 940 941 /* 942 * mem alloc for the position buffer 943 * TODO: check position buffer update 944 */ 945 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 946 SOF_HDA_DPIB_ENTRY_SIZE * num_total, 947 &bus->posbuf); 948 if (ret < 0) { 949 dev_err(sdev->dev, "error: posbuffer dma alloc failed\n"); 950 return -ENOMEM; 951 } 952 953 /* 954 * mem alloc for the CORB/RIRB ringbuffers - this will be used only for 955 * HDAudio codecs 956 */ 957 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 958 PAGE_SIZE, &bus->rb); 959 if (ret < 0) { 960 dev_err(sdev->dev, "error: RB alloc failed\n"); 961 return -ENOMEM; 962 } 963 964 /* create capture and playback streams */ 965 for (i = 0; i < num_total; i++) { 966 struct sof_intel_hda_stream *hda_stream; 967 968 hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream), 969 GFP_KERNEL); 970 if (!hda_stream) 971 return -ENOMEM; 972 973 hda_stream->sdev = sdev; 974 init_completion(&hda_stream->ioc); 975 976 hext_stream = &hda_stream->hext_stream; 977 978 if (sdev->bar[HDA_DSP_PP_BAR]) { 979 hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] + 980 SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i; 981 982 hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] + 983 SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total + 984 SOF_HDA_PPLC_INTERVAL * i; 985 } 986 987 hstream = &hext_stream->hstream; 988 989 /* do we support SPIB */ 990 if (sdev->bar[HDA_DSP_SPIB_BAR]) { 991 hstream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 992 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 993 SOF_HDA_SPIB_SPIB; 994 995 hstream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] + 996 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i + 997 SOF_HDA_SPIB_MAXFIFO; 998 } 999 1000 hstream->bus = bus; 1001 hstream->sd_int_sta_mask = 1 << i; 1002 hstream->index = i; 1003 sd_offset = SOF_STREAM_SD_OFFSET(hstream); 1004 hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset; 1005 hstream->opened = false; 1006 hstream->running = false; 1007 1008 if (i < num_capture) { 1009 hstream->stream_tag = i + 1; 1010 hstream->direction = SNDRV_PCM_STREAM_CAPTURE; 1011 } else { 1012 hstream->stream_tag = i - num_capture + 1; 1013 hstream->direction = SNDRV_PCM_STREAM_PLAYBACK; 1014 } 1015 1016 /* mem alloc for stream BDL */ 1017 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 1018 HDA_DSP_BDL_SIZE, &hstream->bdl); 1019 if (ret < 0) { 1020 dev_err(sdev->dev, "error: stream bdl dma alloc failed\n"); 1021 return -ENOMEM; 1022 } 1023 1024 hstream->posbuf = (__le32 *)(bus->posbuf.area + 1025 (hstream->index) * 8); 1026 1027 list_add_tail(&hstream->list, &bus->stream_list); 1028 } 1029 1030 /* store total stream count (playback + capture) from GCAP */ 1031 sof_hda->stream_max = num_total; 1032 1033 /* store stream count from GCAP required for CHAIN_DMA */ 1034 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) { 1035 struct sof_ipc4_fw_data *ipc4_data = sdev->private; 1036 1037 ipc4_data->num_playback_streams = num_playback; 1038 ipc4_data->num_capture_streams = num_capture; 1039 } 1040 1041 return 0; 1042 } 1043 EXPORT_SYMBOL_NS(hda_dsp_stream_init, "SND_SOC_SOF_INTEL_HDA_COMMON"); 1044 1045 void hda_dsp_stream_free(struct snd_sof_dev *sdev) 1046 { 1047 struct hdac_bus *bus = sof_to_bus(sdev); 1048 struct hdac_stream *s, *_s; 1049 struct hdac_ext_stream *hext_stream; 1050 struct sof_intel_hda_stream *hda_stream; 1051 1052 /* free position buffer */ 1053 if (bus->posbuf.area) 1054 snd_dma_free_pages(&bus->posbuf); 1055 1056 /* free CORB/RIRB buffer - only used for HDaudio codecs */ 1057 if (bus->rb.area) 1058 snd_dma_free_pages(&bus->rb); 1059 1060 list_for_each_entry_safe(s, _s, &bus->stream_list, list) { 1061 /* TODO: decouple */ 1062 1063 /* free bdl buffer */ 1064 if (s->bdl.area) 1065 snd_dma_free_pages(&s->bdl); 1066 list_del(&s->list); 1067 hext_stream = stream_to_hdac_ext_stream(s); 1068 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, 1069 hext_stream); 1070 devm_kfree(sdev->dev, hda_stream); 1071 } 1072 } 1073 EXPORT_SYMBOL_NS(hda_dsp_stream_free, "SND_SOC_SOF_INTEL_HDA_COMMON"); 1074 1075 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, 1076 int direction, bool can_sleep) 1077 { 1078 struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream); 1079 struct sof_intel_hda_stream *hda_stream = hstream_to_sof_hda_stream(hext_stream); 1080 struct snd_sof_dev *sdev = hda_stream->sdev; 1081 snd_pcm_uframes_t pos; 1082 1083 switch (sof_hda_position_quirk) { 1084 case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY: 1085 /* 1086 * This legacy code, inherited from the Skylake driver, 1087 * mixes DPIB registers and DPIB DDR updates and 1088 * does not seem to follow any known hardware recommendations. 1089 * It's not clear e.g. why there is a different flow 1090 * for capture and playback, the only information that matters is 1091 * what traffic class is used, and on all SOF-enabled platforms 1092 * only VC0 is supported so the work-around was likely not necessary 1093 * and quite possibly wrong. 1094 */ 1095 1096 /* DPIB/posbuf position mode: 1097 * For Playback, Use DPIB register from HDA space which 1098 * reflects the actual data transferred. 1099 * For Capture, Use the position buffer for pointer, as DPIB 1100 * is not accurate enough, its update may be completed 1101 * earlier than the data written to DDR. 1102 */ 1103 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1104 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 1105 AZX_REG_VS_SDXDPIB_XBASE + 1106 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1107 hstream->index)); 1108 } else { 1109 /* 1110 * For capture stream, we need more workaround to fix the 1111 * position incorrect issue: 1112 * 1113 * 1. Wait at least 20us before reading position buffer after 1114 * the interrupt generated(IOC), to make sure position update 1115 * happens on frame boundary i.e. 20.833uSec for 48KHz. 1116 * 2. Perform a dummy Read to DPIB register to flush DMA 1117 * position value. 1118 * 3. Read the DMA Position from posbuf. Now the readback 1119 * value should be >= period boundary. 1120 */ 1121 if (can_sleep) 1122 usleep_range(20, 21); 1123 1124 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 1125 AZX_REG_VS_SDXDPIB_XBASE + 1126 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1127 hstream->index)); 1128 pos = snd_hdac_stream_get_pos_posbuf(hstream); 1129 } 1130 break; 1131 case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS: 1132 /* 1133 * In case VC1 traffic is disabled this is the recommended option 1134 */ 1135 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, 1136 AZX_REG_VS_SDXDPIB_XBASE + 1137 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1138 hstream->index)); 1139 break; 1140 case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE: 1141 /* 1142 * This is the recommended option when VC1 is enabled. 1143 * While this isn't needed for SOF platforms it's added for 1144 * consistency and debug. 1145 */ 1146 pos = snd_hdac_stream_get_pos_posbuf(hstream); 1147 break; 1148 default: 1149 dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n", 1150 sof_hda_position_quirk); 1151 pos = 0; 1152 break; 1153 } 1154 1155 if (pos >= hstream->bufsize) 1156 pos = 0; 1157 1158 return pos; 1159 } 1160 EXPORT_SYMBOL_NS(hda_dsp_stream_get_position, "SND_SOC_SOF_INTEL_HDA_COMMON"); 1161 1162 #define merge_u64(u32_u, u32_l) (((u64)(u32_u) << 32) | (u32_l)) 1163 1164 /** 1165 * hda_dsp_get_stream_llp - Retrieve the LLP (Linear Link Position) of the stream 1166 * @sdev: SOF device 1167 * @component: ASoC component 1168 * @substream: PCM substream 1169 * 1170 * Returns the raw Linear Link Position value 1171 */ 1172 u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev, 1173 struct snd_soc_component *component, 1174 struct snd_pcm_substream *substream) 1175 { 1176 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1177 struct snd_soc_pcm_runtime *be_rtd = NULL; 1178 struct hdac_ext_stream *hext_stream; 1179 struct snd_soc_dai *cpu_dai; 1180 struct snd_soc_dpcm *dpcm; 1181 u32 llp_l, llp_u; 1182 1183 /* 1184 * The LLP needs to be read from the Link DMA used for this FE as it is 1185 * allowed to use any combination of Link and Host channels 1186 */ 1187 for_each_dpcm_be(rtd, substream->stream, dpcm) { 1188 if (dpcm->fe != rtd) 1189 continue; 1190 1191 be_rtd = dpcm->be; 1192 } 1193 1194 if (!be_rtd) 1195 return 0; 1196 1197 cpu_dai = snd_soc_rtd_to_cpu(be_rtd, 0); 1198 if (!cpu_dai) 1199 return 0; 1200 1201 hext_stream = snd_soc_dai_get_dma_data(cpu_dai, substream); 1202 if (!hext_stream) 1203 return 0; 1204 1205 /* 1206 * The pplc_addr have been calculated during probe in 1207 * hda_dsp_stream_init(): 1208 * pplc_addr = sdev->bar[HDA_DSP_PP_BAR] + 1209 * SOF_HDA_PPLC_BASE + 1210 * SOF_HDA_PPLC_MULTI * total_stream + 1211 * SOF_HDA_PPLC_INTERVAL * stream_index 1212 * 1213 * Use this pre-calculated address to avoid repeated re-calculation. 1214 */ 1215 llp_l = readl(hext_stream->pplc_addr + AZX_REG_PPLCLLPL); 1216 llp_u = readl(hext_stream->pplc_addr + AZX_REG_PPLCLLPU); 1217 1218 /* Compensate the LLP counter with the saved offset */ 1219 if (hext_stream->pplcllpl || hext_stream->pplcllpu) 1220 return merge_u64(llp_u, llp_l) - 1221 merge_u64(hext_stream->pplcllpu, hext_stream->pplcllpl); 1222 1223 return merge_u64(llp_u, llp_l); 1224 } 1225 EXPORT_SYMBOL_NS(hda_dsp_get_stream_llp, "SND_SOC_SOF_INTEL_HDA_COMMON"); 1226 1227 /** 1228 * hda_dsp_get_stream_ldp - Retrieve the LDP (Linear DMA Position) of the stream 1229 * @sdev: SOF device 1230 * @component: ASoC component 1231 * @substream: PCM substream 1232 * 1233 * Returns the raw Linear Link Position value 1234 */ 1235 u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev, 1236 struct snd_soc_component *component, 1237 struct snd_pcm_substream *substream) 1238 { 1239 struct hdac_stream *hstream = substream->runtime->private_data; 1240 struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream); 1241 u32 ldp_l, ldp_u; 1242 1243 /* 1244 * The pphc_addr have been calculated during probe in 1245 * hda_dsp_stream_init(): 1246 * pphc_addr = sdev->bar[HDA_DSP_PP_BAR] + 1247 * SOF_HDA_PPHC_BASE + 1248 * SOF_HDA_PPHC_INTERVAL * stream_index 1249 * 1250 * Use this pre-calculated address to avoid repeated re-calculation. 1251 */ 1252 ldp_l = readl(hext_stream->pphc_addr + AZX_REG_PPHCLDPL); 1253 ldp_u = readl(hext_stream->pphc_addr + AZX_REG_PPHCLDPU); 1254 1255 return ((u64)ldp_u << 32) | ldp_l; 1256 } 1257 EXPORT_SYMBOL_NS(hda_dsp_get_stream_ldp, "SND_SOC_SOF_INTEL_HDA_COMMON"); 1258 1259 struct hdac_ext_stream * 1260 hda_data_stream_prepare(struct device *dev, unsigned int format, unsigned int size, 1261 struct snd_dma_buffer *dmab, bool persistent_buffer, int direction, 1262 bool is_iccmax, bool pair) 1263 { 1264 struct snd_sof_dev *sdev = dev_get_drvdata(dev); 1265 struct hdac_ext_stream *hext_stream; 1266 struct hdac_stream *hstream; 1267 int ret; 1268 1269 if (pair) 1270 hext_stream = hda_dsp_stream_pair_get(sdev, direction, 0); 1271 else 1272 hext_stream = hda_dsp_stream_get(sdev, direction, 0); 1273 1274 if (!hext_stream) { 1275 dev_err(sdev->dev, "%s: no stream available\n", __func__); 1276 return ERR_PTR(-ENODEV); 1277 } 1278 hstream = &hext_stream->hstream; 1279 hstream->substream = NULL; 1280 1281 /* 1282 * Allocate DMA buffer if it is temporary or if the buffer is intended 1283 * to be persistent but not yet allocated. 1284 * We cannot rely solely on !dmab->area as caller might use a struct on 1285 * stack (when it is temporary) without clearing it to 0. 1286 */ 1287 if (!persistent_buffer || !dmab->area) { 1288 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, dev, size, dmab); 1289 if (ret < 0) { 1290 dev_err(sdev->dev, "%s: memory alloc failed: %d\n", 1291 __func__, ret); 1292 goto out_put; 1293 } 1294 } 1295 1296 hstream->period_bytes = 0; /* initialize period_bytes */ 1297 hstream->format_val = format; 1298 hstream->bufsize = size; 1299 1300 if (is_iccmax) { 1301 ret = hda_dsp_iccmax_stream_hw_params(sdev, hext_stream, dmab, NULL); 1302 if (ret < 0) { 1303 dev_err(sdev->dev, "%s: iccmax stream prepare failed: %d\n", 1304 __func__, ret); 1305 goto out_free; 1306 } 1307 } else { 1308 ret = hda_dsp_stream_hw_params(sdev, hext_stream, dmab, NULL); 1309 if (ret < 0) { 1310 dev_err(sdev->dev, "%s: hdac prepare failed: %d\n", __func__, ret); 1311 goto out_free; 1312 } 1313 hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_ENABLE, size); 1314 } 1315 1316 return hext_stream; 1317 1318 out_free: 1319 snd_dma_free_pages(dmab); 1320 dmab->area = NULL; 1321 dmab->bytes = 0; 1322 hstream->bufsize = 0; 1323 hstream->format_val = 0; 1324 out_put: 1325 if (pair) 1326 hda_dsp_stream_pair_put(sdev, direction, hstream->stream_tag); 1327 else 1328 hda_dsp_stream_put(sdev, direction, hstream->stream_tag); 1329 return ERR_PTR(ret); 1330 } 1331 EXPORT_SYMBOL_NS(hda_data_stream_prepare, "SND_SOC_SOF_INTEL_HDA_COMMON"); 1332 1333 int hda_data_stream_cleanup(struct device *dev, struct snd_dma_buffer *dmab, 1334 bool persistent_buffer, struct hdac_ext_stream *hext_stream, 1335 bool is_iccmax, bool pair) 1336 { 1337 struct snd_sof_dev *sdev = dev_get_drvdata(dev); 1338 struct hdac_stream *hstream = hdac_stream(hext_stream); 1339 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 1340 int ret = 0; 1341 1342 if (!is_iccmax) 1343 ret = hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0); 1344 1345 if (hstream->direction == SNDRV_PCM_STREAM_CAPTURE) 1346 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 1347 SOF_HDA_SD_CTL_DMA_START, 0); 1348 1349 if (pair) 1350 hda_dsp_stream_pair_put(sdev, hstream->direction, hstream->stream_tag); 1351 else 1352 hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag); 1353 1354 hstream->running = 0; 1355 hstream->substream = NULL; 1356 1357 /* reset BDL address */ 1358 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 1359 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 0); 1360 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 1361 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 0); 1362 1363 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0); 1364 1365 if (!persistent_buffer) { 1366 snd_dma_free_pages(dmab); 1367 dmab->area = NULL; 1368 dmab->bytes = 0; 1369 hstream->bufsize = 0; 1370 hstream->format_val = 0; 1371 } 1372 1373 return ret; 1374 } 1375 EXPORT_SYMBOL_NS(hda_data_stream_cleanup, "SND_SOC_SOF_INTEL_HDA_COMMON"); 1376