1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for HDA DSP code loader 16 */ 17 18 #include <linux/firmware.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include <sound/sof.h> 22 #include "ext_manifest.h" 23 #include "../ops.h" 24 #include "../sof-priv.h" 25 #include "hda.h" 26 27 #define HDA_CL_STREAM_FORMAT 0x40 28 29 static void hda_ssp_set_cbp_cfp(struct snd_sof_dev *sdev) 30 { 31 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 32 const struct sof_intel_dsp_desc *chip = hda->desc; 33 int i; 34 35 /* DSP is powered up, set all SSPs to clock consumer/codec provider mode */ 36 for (i = 0; i < chip->ssp_count; i++) { 37 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 38 chip->ssp_base_offset 39 + i * SSP_DEV_MEM_SIZE 40 + SSP_SSC1_OFFSET, 41 SSP_SET_CBP_CFP, 42 SSP_SET_CBP_CFP); 43 } 44 } 45 46 static struct hdac_ext_stream *cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, 47 unsigned int size, struct snd_dma_buffer *dmab, 48 int direction) 49 { 50 struct hdac_ext_stream *hext_stream; 51 struct hdac_stream *hstream; 52 struct pci_dev *pci = to_pci_dev(sdev->dev); 53 int ret; 54 55 hext_stream = hda_dsp_stream_get(sdev, direction, 0); 56 57 if (!hext_stream) { 58 dev_err(sdev->dev, "error: no stream available\n"); 59 return ERR_PTR(-ENODEV); 60 } 61 hstream = &hext_stream->hstream; 62 hstream->substream = NULL; 63 64 /* allocate DMA buffer */ 65 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab); 66 if (ret < 0) { 67 dev_err(sdev->dev, "error: memory alloc failed: %d\n", ret); 68 goto out_put; 69 } 70 71 hstream->period_bytes = 0;/* initialize period_bytes */ 72 hstream->format_val = format; 73 hstream->bufsize = size; 74 75 if (direction == SNDRV_PCM_STREAM_CAPTURE) { 76 ret = hda_dsp_iccmax_stream_hw_params(sdev, hext_stream, dmab, NULL); 77 if (ret < 0) { 78 dev_err(sdev->dev, "error: iccmax stream prepare failed: %d\n", ret); 79 goto out_free; 80 } 81 } else { 82 ret = hda_dsp_stream_hw_params(sdev, hext_stream, dmab, NULL); 83 if (ret < 0) { 84 dev_err(sdev->dev, "error: hdac prepare failed: %d\n", ret); 85 goto out_free; 86 } 87 hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_ENABLE, size); 88 } 89 90 return hext_stream; 91 92 out_free: 93 snd_dma_free_pages(dmab); 94 out_put: 95 hda_dsp_stream_put(sdev, direction, hstream->stream_tag); 96 return ERR_PTR(ret); 97 } 98 99 /* 100 * first boot sequence has some extra steps. core 0 waits for power 101 * status on core 1, so power up core 1 also momentarily, keep it in 102 * reset/stall and then turn it off 103 */ 104 static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag) 105 { 106 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 107 const struct sof_intel_dsp_desc *chip = hda->desc; 108 unsigned int status; 109 unsigned long mask; 110 char *dump_msg; 111 u32 flags, j; 112 int ret; 113 114 /* step 1: power up corex */ 115 ret = hda_dsp_enable_core(sdev, chip->host_managed_cores_mask); 116 if (ret < 0) { 117 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 118 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n"); 119 goto err; 120 } 121 122 hda_ssp_set_cbp_cfp(sdev); 123 124 /* step 2: purge FW request */ 125 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, 126 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW | 127 ((stream_tag - 1) << 9))); 128 129 /* step 3: unset core 0 reset state & unstall/run core 0 */ 130 ret = hda_dsp_core_run(sdev, BIT(0)); 131 if (ret < 0) { 132 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 133 dev_err(sdev->dev, 134 "error: dsp core start failed %d\n", ret); 135 ret = -EIO; 136 goto err; 137 } 138 139 /* step 4: wait for IPC DONE bit from ROM */ 140 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 141 chip->ipc_ack, status, 142 ((status & chip->ipc_ack_mask) 143 == chip->ipc_ack_mask), 144 HDA_DSP_REG_POLL_INTERVAL_US, 145 HDA_DSP_INIT_TIMEOUT_US); 146 147 if (ret < 0) { 148 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 149 dev_err(sdev->dev, 150 "error: %s: timeout for HIPCIE done\n", 151 __func__); 152 goto err; 153 } 154 155 /* set DONE bit to clear the reply IPC message */ 156 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 157 chip->ipc_ack, 158 chip->ipc_ack_mask, 159 chip->ipc_ack_mask); 160 161 /* step 5: power down cores that are no longer needed */ 162 ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask & 163 ~(chip->init_core_mask)); 164 if (ret < 0) { 165 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 166 dev_err(sdev->dev, 167 "error: dsp core x power down failed\n"); 168 goto err; 169 } 170 171 /* step 6: enable IPC interrupts */ 172 hda_dsp_ipc_int_enable(sdev); 173 174 /* step 7: wait for ROM init */ 175 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 176 HDA_DSP_SRAM_REG_ROM_STATUS, status, 177 ((status & HDA_DSP_ROM_STS_MASK) 178 == HDA_DSP_ROM_INIT), 179 HDA_DSP_REG_POLL_INTERVAL_US, 180 chip->rom_init_timeout * 181 USEC_PER_MSEC); 182 if (!ret) { 183 /* set enabled cores mask and increment ref count for cores in init_core_mask */ 184 sdev->enabled_cores_mask |= chip->init_core_mask; 185 mask = sdev->enabled_cores_mask; 186 for_each_set_bit(j, &mask, SOF_MAX_DSP_NUM_CORES) 187 sdev->dsp_core_ref_count[j]++; 188 return 0; 189 } 190 191 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 192 dev_err(sdev->dev, 193 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n", 194 __func__); 195 196 err: 197 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL; 198 199 /* after max boot attempts make sure that the dump is printed */ 200 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 201 flags &= ~SOF_DBG_DUMP_OPTIONAL; 202 203 dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d", 204 hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS); 205 snd_sof_dsp_dbg_dump(sdev, dump_msg, flags); 206 hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 207 208 kfree(dump_msg); 209 return ret; 210 } 211 212 static int cl_trigger(struct snd_sof_dev *sdev, 213 struct hdac_ext_stream *hext_stream, int cmd) 214 { 215 struct hdac_stream *hstream = &hext_stream->hstream; 216 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 217 218 /* code loader is special case that reuses stream ops */ 219 switch (cmd) { 220 case SNDRV_PCM_TRIGGER_START: 221 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 222 1 << hstream->index, 223 1 << hstream->index); 224 225 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 226 sd_offset, 227 SOF_HDA_SD_CTL_DMA_START | 228 SOF_HDA_CL_DMA_SD_INT_MASK, 229 SOF_HDA_SD_CTL_DMA_START | 230 SOF_HDA_CL_DMA_SD_INT_MASK); 231 232 hstream->running = true; 233 return 0; 234 default: 235 return hda_dsp_stream_trigger(sdev, hext_stream, cmd); 236 } 237 } 238 239 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 240 struct hdac_ext_stream *hext_stream) 241 { 242 struct hdac_stream *hstream = &hext_stream->hstream; 243 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 244 int ret = 0; 245 246 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) 247 ret = hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0); 248 else 249 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 250 SOF_HDA_SD_CTL_DMA_START, 0); 251 252 hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag); 253 hstream->running = 0; 254 hstream->substream = NULL; 255 256 /* reset BDL address */ 257 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 258 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0); 259 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 260 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0); 261 262 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0); 263 snd_dma_free_pages(dmab); 264 dmab->area = NULL; 265 hstream->bufsize = 0; 266 hstream->format_val = 0; 267 268 return ret; 269 } 270 271 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream) 272 { 273 unsigned int reg; 274 int ret, status; 275 276 ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_START); 277 if (ret < 0) { 278 dev_err(sdev->dev, "error: DMA trigger start failed\n"); 279 return ret; 280 } 281 282 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 283 HDA_DSP_SRAM_REG_ROM_STATUS, reg, 284 ((reg & HDA_DSP_ROM_STS_MASK) 285 == HDA_DSP_ROM_FW_ENTERED), 286 HDA_DSP_REG_POLL_INTERVAL_US, 287 HDA_DSP_BASEFW_TIMEOUT_US); 288 289 /* 290 * even in case of errors we still need to stop the DMAs, 291 * but we return the initial error should the DMA stop also fail 292 */ 293 294 if (status < 0) { 295 dev_err(sdev->dev, 296 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n", 297 __func__); 298 } 299 300 ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_STOP); 301 if (ret < 0) { 302 dev_err(sdev->dev, "error: DMA trigger stop failed\n"); 303 if (!status) 304 status = ret; 305 } 306 307 return status; 308 } 309 310 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev) 311 { 312 struct snd_sof_pdata *plat_data = sdev->pdata; 313 struct hdac_ext_stream *iccmax_stream; 314 struct hdac_bus *bus = sof_to_bus(sdev); 315 struct firmware stripped_firmware; 316 struct snd_dma_buffer dmab_bdl; 317 int ret, ret1; 318 u8 original_gb; 319 320 /* save the original LTRP guardband value */ 321 original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK; 322 323 if (plat_data->fw->size <= plat_data->fw_offset) { 324 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n"); 325 return -EINVAL; 326 } 327 328 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset; 329 330 /* prepare capture stream for ICCMAX */ 331 iccmax_stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size, 332 &dmab_bdl, SNDRV_PCM_STREAM_CAPTURE); 333 if (IS_ERR(iccmax_stream)) { 334 dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n"); 335 return PTR_ERR(iccmax_stream); 336 } 337 338 ret = hda_dsp_cl_boot_firmware(sdev); 339 340 /* 341 * Perform iccmax stream cleanup. This should be done even if firmware loading fails. 342 * If the cleanup also fails, we return the initial error 343 */ 344 ret1 = cl_cleanup(sdev, &dmab_bdl, iccmax_stream); 345 if (ret1 < 0) { 346 dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n"); 347 348 /* set return value to indicate cleanup failure */ 349 if (!ret) 350 ret = ret1; 351 } 352 353 /* restore the original guardband value after FW boot */ 354 snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb); 355 356 return ret; 357 } 358 359 static int hda_dsp_boot_imr(struct snd_sof_dev *sdev) 360 { 361 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 362 const struct sof_intel_dsp_desc *chip = hda->desc; 363 unsigned long mask; 364 u32 j; 365 int ret; 366 367 /* power up & unstall/run the cores to run the firmware */ 368 ret = hda_dsp_enable_core(sdev, chip->init_core_mask); 369 if (ret < 0) { 370 dev_err(sdev->dev, "dsp core start failed %d\n", ret); 371 return -EIO; 372 } 373 374 /* set enabled cores mask and increment ref count for cores in init_core_mask */ 375 sdev->enabled_cores_mask |= chip->init_core_mask; 376 mask = sdev->enabled_cores_mask; 377 for_each_set_bit(j, &mask, SOF_MAX_DSP_NUM_CORES) 378 sdev->dsp_core_ref_count[j]++; 379 380 hda_ssp_set_cbp_cfp(sdev); 381 382 /* enable IPC interrupts */ 383 hda_dsp_ipc_int_enable(sdev); 384 385 /* process wakes */ 386 hda_sdw_process_wakeen(sdev); 387 388 return ret; 389 } 390 391 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) 392 { 393 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 394 struct snd_sof_pdata *plat_data = sdev->pdata; 395 const struct sof_dev_desc *desc = plat_data->desc; 396 const struct sof_intel_dsp_desc *chip_info; 397 struct hdac_ext_stream *hext_stream; 398 struct firmware stripped_firmware; 399 struct snd_dma_buffer dmab; 400 int ret, ret1, i; 401 402 if ((sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT) && 403 !(sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) && 404 !sdev->first_boot) { 405 dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n"); 406 return hda_dsp_boot_imr(sdev); 407 } 408 409 chip_info = desc->chip_info; 410 411 if (plat_data->fw->size <= plat_data->fw_offset) { 412 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n"); 413 return -EINVAL; 414 } 415 416 stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset; 417 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset; 418 419 /* init for booting wait */ 420 init_waitqueue_head(&sdev->boot_wait); 421 422 /* prepare DMA for code loader stream */ 423 hext_stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size, 424 &dmab, SNDRV_PCM_STREAM_PLAYBACK); 425 if (IS_ERR(hext_stream)) { 426 dev_err(sdev->dev, "error: dma prepare for fw loading failed\n"); 427 return PTR_ERR(hext_stream); 428 } 429 430 memcpy(dmab.area, stripped_firmware.data, 431 stripped_firmware.size); 432 433 /* try ROM init a few times before giving up */ 434 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) { 435 dev_dbg(sdev->dev, 436 "Attempting iteration %d of Core En/ROM load...\n", i); 437 438 hda->boot_iteration = i + 1; 439 ret = cl_dsp_init(sdev, hext_stream->hstream.stream_tag); 440 441 /* don't retry anymore if successful */ 442 if (!ret) 443 break; 444 } 445 446 if (i == HDA_FW_BOOT_ATTEMPTS) { 447 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n", 448 i, ret); 449 goto cleanup; 450 } 451 452 /* 453 * When a SoundWire link is in clock stop state, a Slave 454 * device may trigger in-band wakes for events such as jack 455 * insertion or acoustic event detection. This event will lead 456 * to a WAKEEN interrupt, handled by the PCI device and routed 457 * to PME if the PCI device is in D3. The resume function in 458 * audio PCI driver will be invoked by ACPI for PME event and 459 * initialize the device and process WAKEEN interrupt. 460 * 461 * The WAKEEN interrupt should be processed ASAP to prevent an 462 * interrupt flood, otherwise other interrupts, such IPC, 463 * cannot work normally. The WAKEEN is handled after the ROM 464 * is initialized successfully, which ensures power rails are 465 * enabled before accessing the SoundWire SHIM registers 466 */ 467 if (!sdev->first_boot) 468 hda_sdw_process_wakeen(sdev); 469 470 /* 471 * Set the boot_iteration to the last attempt, indicating that the 472 * DSP ROM has been initialized and from this point there will be no 473 * retry done to boot. 474 * 475 * Continue with code loading and firmware boot 476 */ 477 hda->boot_iteration = HDA_FW_BOOT_ATTEMPTS; 478 ret = cl_copy_fw(sdev, hext_stream); 479 if (!ret) 480 dev_dbg(sdev->dev, "Firmware download successful, booting...\n"); 481 else 482 snd_sof_dsp_dbg_dump(sdev, "Firmware download failed", 483 SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX); 484 485 cleanup: 486 /* 487 * Perform codeloader stream cleanup. 488 * This should be done even if firmware loading fails. 489 * If the cleanup also fails, we return the initial error 490 */ 491 ret1 = cl_cleanup(sdev, &dmab, hext_stream); 492 if (ret1 < 0) { 493 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n"); 494 495 /* set return value to indicate cleanup failure */ 496 if (!ret) 497 ret = ret1; 498 } 499 500 /* 501 * return primary core id if both fw copy 502 * and stream clean up are successful 503 */ 504 if (!ret) 505 return chip_info->init_core_mask; 506 507 /* disable DSP */ 508 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, 509 SOF_HDA_REG_PP_PPCTL, 510 SOF_HDA_PPCTL_GPROCEN, 0); 511 return ret; 512 } 513 514 /* pre fw run operations */ 515 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev) 516 { 517 /* disable clock gating and power gating */ 518 return hda_dsp_ctrl_clock_power_gating(sdev, false); 519 } 520 521 /* post fw run operations */ 522 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev) 523 { 524 int ret; 525 526 if (sdev->first_boot) { 527 ret = hda_sdw_startup(sdev); 528 if (ret < 0) { 529 dev_err(sdev->dev, 530 "error: could not startup SoundWire links\n"); 531 return ret; 532 } 533 } 534 535 hda_sdw_int_enable(sdev, true); 536 537 /* re-enable clock gating and power gating */ 538 return hda_dsp_ctrl_clock_power_gating(sdev, true); 539 } 540 541 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 542 const struct sof_ext_man_elem_header *hdr) 543 { 544 const struct sof_ext_man_cavs_config_data *config_data = 545 container_of(hdr, struct sof_ext_man_cavs_config_data, hdr); 546 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 547 int i, elem_num; 548 549 /* calculate total number of config data elements */ 550 elem_num = (hdr->size - sizeof(struct sof_ext_man_elem_header)) 551 / sizeof(struct sof_config_elem); 552 if (elem_num <= 0) { 553 dev_err(sdev->dev, "cavs config data is inconsistent: %d\n", elem_num); 554 return -EINVAL; 555 } 556 557 for (i = 0; i < elem_num; i++) 558 switch (config_data->elems[i].token) { 559 case SOF_EXT_MAN_CAVS_CONFIG_EMPTY: 560 /* skip empty token */ 561 break; 562 case SOF_EXT_MAN_CAVS_CONFIG_CAVS_LPRO: 563 hda->clk_config_lpro = config_data->elems[i].value; 564 dev_dbg(sdev->dev, "FW clock config: %s\n", 565 hda->clk_config_lpro ? "LPRO" : "HPRO"); 566 break; 567 case SOF_EXT_MAN_CAVS_CONFIG_OUTBOX_SIZE: 568 case SOF_EXT_MAN_CAVS_CONFIG_INBOX_SIZE: 569 /* These elements are defined but not being used yet. No warn is required */ 570 break; 571 default: 572 dev_info(sdev->dev, "unsupported token type: %d\n", 573 config_data->elems[i].token); 574 } 575 576 return 0; 577 } 578