1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for HDA DSP code loader 16 */ 17 18 #include <linux/firmware.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include <sound/sof.h> 22 #include "ext_manifest.h" 23 #include "../ops.h" 24 #include "hda.h" 25 26 #define HDA_FW_BOOT_ATTEMPTS 3 27 #define HDA_CL_STREAM_FORMAT 0x40 28 29 static struct hdac_ext_stream *cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, 30 unsigned int size, struct snd_dma_buffer *dmab, 31 int direction) 32 { 33 struct hdac_ext_stream *dsp_stream; 34 struct hdac_stream *hstream; 35 struct pci_dev *pci = to_pci_dev(sdev->dev); 36 int ret; 37 38 dsp_stream = hda_dsp_stream_get(sdev, direction, 0); 39 40 if (!dsp_stream) { 41 dev_err(sdev->dev, "error: no stream available\n"); 42 return ERR_PTR(-ENODEV); 43 } 44 hstream = &dsp_stream->hstream; 45 hstream->substream = NULL; 46 47 /* allocate DMA buffer */ 48 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab); 49 if (ret < 0) { 50 dev_err(sdev->dev, "error: memory alloc failed: %d\n", ret); 51 goto error; 52 } 53 54 hstream->period_bytes = 0;/* initialize period_bytes */ 55 hstream->format_val = format; 56 hstream->bufsize = size; 57 58 if (direction == SNDRV_PCM_STREAM_CAPTURE) { 59 ret = hda_dsp_iccmax_stream_hw_params(sdev, dsp_stream, dmab, NULL); 60 if (ret < 0) { 61 dev_err(sdev->dev, "error: iccmax stream prepare failed: %d\n", ret); 62 goto error; 63 } 64 } else { 65 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL); 66 if (ret < 0) { 67 dev_err(sdev->dev, "error: hdac prepare failed: %d\n", ret); 68 goto error; 69 } 70 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size); 71 } 72 73 return dsp_stream; 74 75 error: 76 hda_dsp_stream_put(sdev, direction, hstream->stream_tag); 77 snd_dma_free_pages(dmab); 78 return ERR_PTR(ret); 79 } 80 81 /* 82 * first boot sequence has some extra steps. core 0 waits for power 83 * status on core 1, so power up core 1 also momentarily, keep it in 84 * reset/stall and then turn it off 85 */ 86 static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag) 87 { 88 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 89 const struct sof_intel_dsp_desc *chip = hda->desc; 90 unsigned int status; 91 unsigned long mask; 92 u32 flags, j; 93 int ret; 94 int i; 95 96 /* step 1: power up corex */ 97 ret = hda_dsp_enable_core(sdev, chip->host_managed_cores_mask); 98 if (ret < 0) { 99 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 100 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n"); 101 goto err; 102 } 103 104 /* DSP is powered up, set all SSPs to slave mode */ 105 for (i = 0; i < chip->ssp_count; i++) { 106 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 107 chip->ssp_base_offset 108 + i * SSP_DEV_MEM_SIZE 109 + SSP_SSC1_OFFSET, 110 SSP_SET_SLAVE, 111 SSP_SET_SLAVE); 112 } 113 114 /* step 2: purge FW request */ 115 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, 116 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW | 117 ((stream_tag - 1) << 9))); 118 119 /* step 3: unset core 0 reset state & unstall/run core 0 */ 120 ret = hda_dsp_core_run(sdev, BIT(0)); 121 if (ret < 0) { 122 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 123 dev_err(sdev->dev, 124 "error: dsp core start failed %d\n", ret); 125 ret = -EIO; 126 goto err; 127 } 128 129 /* step 4: wait for IPC DONE bit from ROM */ 130 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 131 chip->ipc_ack, status, 132 ((status & chip->ipc_ack_mask) 133 == chip->ipc_ack_mask), 134 HDA_DSP_REG_POLL_INTERVAL_US, 135 HDA_DSP_INIT_TIMEOUT_US); 136 137 if (ret < 0) { 138 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 139 dev_err(sdev->dev, 140 "error: %s: timeout for HIPCIE done\n", 141 __func__); 142 goto err; 143 } 144 145 /* set DONE bit to clear the reply IPC message */ 146 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, 147 chip->ipc_ack, 148 chip->ipc_ack_mask, 149 chip->ipc_ack_mask); 150 151 /* step 5: power down cores that are no longer needed */ 152 ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask & 153 ~(chip->init_core_mask)); 154 if (ret < 0) { 155 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 156 dev_err(sdev->dev, 157 "error: dsp core x power down failed\n"); 158 goto err; 159 } 160 161 /* step 6: enable IPC interrupts */ 162 hda_dsp_ipc_int_enable(sdev); 163 164 /* step 7: wait for ROM init */ 165 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 166 HDA_DSP_SRAM_REG_ROM_STATUS, status, 167 ((status & HDA_DSP_ROM_STS_MASK) 168 == HDA_DSP_ROM_INIT), 169 HDA_DSP_REG_POLL_INTERVAL_US, 170 chip->rom_init_timeout * 171 USEC_PER_MSEC); 172 if (!ret) { 173 /* set enabled cores mask and increment ref count for cores in init_core_mask */ 174 sdev->enabled_cores_mask |= chip->init_core_mask; 175 mask = sdev->enabled_cores_mask; 176 for_each_set_bit(j, &mask, SOF_MAX_DSP_NUM_CORES) 177 sdev->dsp_core_ref_count[j]++; 178 return 0; 179 } 180 181 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 182 dev_err(sdev->dev, 183 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n", 184 __func__); 185 186 err: 187 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL; 188 189 /* after max boot attempts make sure that the dump is printed */ 190 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) 191 flags &= ~SOF_DBG_DUMP_OPTIONAL; 192 193 snd_sof_dsp_dbg_dump(sdev, flags); 194 hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 195 196 return ret; 197 } 198 199 static int cl_trigger(struct snd_sof_dev *sdev, 200 struct hdac_ext_stream *stream, int cmd) 201 { 202 struct hdac_stream *hstream = &stream->hstream; 203 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 204 205 /* code loader is special case that reuses stream ops */ 206 switch (cmd) { 207 case SNDRV_PCM_TRIGGER_START: 208 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 209 1 << hstream->index, 210 1 << hstream->index); 211 212 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 213 sd_offset, 214 SOF_HDA_SD_CTL_DMA_START | 215 SOF_HDA_CL_DMA_SD_INT_MASK, 216 SOF_HDA_SD_CTL_DMA_START | 217 SOF_HDA_CL_DMA_SD_INT_MASK); 218 219 hstream->running = true; 220 return 0; 221 default: 222 return hda_dsp_stream_trigger(sdev, stream, cmd); 223 } 224 } 225 226 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 227 struct hdac_ext_stream *stream) 228 { 229 struct hdac_stream *hstream = &stream->hstream; 230 int sd_offset = SOF_STREAM_SD_OFFSET(hstream); 231 int ret = 0; 232 233 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) 234 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0); 235 else 236 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 237 SOF_HDA_SD_CTL_DMA_START, 0); 238 239 hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag); 240 hstream->running = 0; 241 hstream->substream = NULL; 242 243 /* reset BDL address */ 244 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 245 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0); 246 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 247 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0); 248 249 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0); 250 snd_dma_free_pages(dmab); 251 dmab->area = NULL; 252 hstream->bufsize = 0; 253 hstream->format_val = 0; 254 255 return ret; 256 } 257 258 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream) 259 { 260 unsigned int reg; 261 int ret, status; 262 263 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START); 264 if (ret < 0) { 265 dev_err(sdev->dev, "error: DMA trigger start failed\n"); 266 return ret; 267 } 268 269 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 270 HDA_DSP_SRAM_REG_ROM_STATUS, reg, 271 ((reg & HDA_DSP_ROM_STS_MASK) 272 == HDA_DSP_ROM_FW_ENTERED), 273 HDA_DSP_REG_POLL_INTERVAL_US, 274 HDA_DSP_BASEFW_TIMEOUT_US); 275 276 /* 277 * even in case of errors we still need to stop the DMAs, 278 * but we return the initial error should the DMA stop also fail 279 */ 280 281 if (status < 0) { 282 dev_err(sdev->dev, 283 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n", 284 __func__); 285 } 286 287 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP); 288 if (ret < 0) { 289 dev_err(sdev->dev, "error: DMA trigger stop failed\n"); 290 if (!status) 291 status = ret; 292 } 293 294 return status; 295 } 296 297 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev) 298 { 299 struct snd_sof_pdata *plat_data = sdev->pdata; 300 struct hdac_ext_stream *iccmax_stream; 301 struct hdac_bus *bus = sof_to_bus(sdev); 302 struct firmware stripped_firmware; 303 int ret, ret1; 304 u8 original_gb; 305 306 /* save the original LTRP guardband value */ 307 original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK; 308 309 if (plat_data->fw->size <= plat_data->fw_offset) { 310 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n"); 311 return -EINVAL; 312 } 313 314 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset; 315 316 /* prepare capture stream for ICCMAX */ 317 iccmax_stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size, 318 &sdev->dmab_bdl, SNDRV_PCM_STREAM_CAPTURE); 319 if (IS_ERR(iccmax_stream)) { 320 dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n"); 321 return PTR_ERR(iccmax_stream); 322 } 323 324 ret = hda_dsp_cl_boot_firmware(sdev); 325 326 /* 327 * Perform iccmax stream cleanup. This should be done even if firmware loading fails. 328 * If the cleanup also fails, we return the initial error 329 */ 330 ret1 = cl_cleanup(sdev, &sdev->dmab_bdl, iccmax_stream); 331 if (ret1 < 0) { 332 dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n"); 333 334 /* set return value to indicate cleanup failure */ 335 if (!ret) 336 ret = ret1; 337 } 338 339 /* restore the original guardband value after FW boot */ 340 snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb); 341 342 return ret; 343 } 344 345 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) 346 { 347 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 348 struct snd_sof_pdata *plat_data = sdev->pdata; 349 const struct sof_dev_desc *desc = plat_data->desc; 350 const struct sof_intel_dsp_desc *chip_info; 351 struct hdac_ext_stream *stream; 352 struct firmware stripped_firmware; 353 int ret, ret1, i; 354 355 chip_info = desc->chip_info; 356 357 if (plat_data->fw->size <= plat_data->fw_offset) { 358 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n"); 359 return -EINVAL; 360 } 361 362 stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset; 363 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset; 364 365 /* init for booting wait */ 366 init_waitqueue_head(&sdev->boot_wait); 367 368 /* prepare DMA for code loader stream */ 369 stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size, 370 &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK); 371 if (IS_ERR(stream)) { 372 dev_err(sdev->dev, "error: dma prepare for fw loading failed\n"); 373 return PTR_ERR(stream); 374 } 375 376 memcpy(sdev->dmab.area, stripped_firmware.data, 377 stripped_firmware.size); 378 379 /* try ROM init a few times before giving up */ 380 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) { 381 dev_dbg(sdev->dev, 382 "Attempting iteration %d of Core En/ROM load...\n", i); 383 384 hda->boot_iteration = i + 1; 385 ret = cl_dsp_init(sdev, stream->hstream.stream_tag); 386 387 /* don't retry anymore if successful */ 388 if (!ret) 389 break; 390 } 391 392 if (i == HDA_FW_BOOT_ATTEMPTS) { 393 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n", 394 i, ret); 395 goto cleanup; 396 } 397 398 /* 399 * When a SoundWire link is in clock stop state, a Slave 400 * device may trigger in-band wakes for events such as jack 401 * insertion or acoustic event detection. This event will lead 402 * to a WAKEEN interrupt, handled by the PCI device and routed 403 * to PME if the PCI device is in D3. The resume function in 404 * audio PCI driver will be invoked by ACPI for PME event and 405 * initialize the device and process WAKEEN interrupt. 406 * 407 * The WAKEEN interrupt should be processed ASAP to prevent an 408 * interrupt flood, otherwise other interrupts, such IPC, 409 * cannot work normally. The WAKEEN is handled after the ROM 410 * is initialized successfully, which ensures power rails are 411 * enabled before accessing the SoundWire SHIM registers 412 */ 413 if (!sdev->first_boot) 414 hda_sdw_process_wakeen(sdev); 415 416 /* 417 * at this point DSP ROM has been initialized and 418 * should be ready for code loading and firmware boot 419 */ 420 ret = cl_copy_fw(sdev, stream); 421 if (!ret) { 422 dev_dbg(sdev->dev, "Firmware download successful, booting...\n"); 423 } else { 424 snd_sof_dsp_dbg_dump(sdev, SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX); 425 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret); 426 } 427 428 cleanup: 429 /* 430 * Perform codeloader stream cleanup. 431 * This should be done even if firmware loading fails. 432 * If the cleanup also fails, we return the initial error 433 */ 434 ret1 = cl_cleanup(sdev, &sdev->dmab, stream); 435 if (ret1 < 0) { 436 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n"); 437 438 /* set return value to indicate cleanup failure */ 439 if (!ret) 440 ret = ret1; 441 } 442 443 /* 444 * return primary core id if both fw copy 445 * and stream clean up are successful 446 */ 447 if (!ret) 448 return chip_info->init_core_mask; 449 450 /* disable DSP */ 451 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, 452 SOF_HDA_REG_PP_PPCTL, 453 SOF_HDA_PPCTL_GPROCEN, 0); 454 return ret; 455 } 456 457 /* pre fw run operations */ 458 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev) 459 { 460 /* disable clock gating and power gating */ 461 return hda_dsp_ctrl_clock_power_gating(sdev, false); 462 } 463 464 /* post fw run operations */ 465 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev) 466 { 467 int ret; 468 469 if (sdev->first_boot) { 470 ret = hda_sdw_startup(sdev); 471 if (ret < 0) { 472 dev_err(sdev->dev, 473 "error: could not startup SoundWire links\n"); 474 return ret; 475 } 476 } 477 478 hda_sdw_int_enable(sdev, true); 479 480 /* re-enable clock gating and power gating */ 481 return hda_dsp_ctrl_clock_power_gating(sdev, true); 482 } 483 484 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 485 const struct sof_ext_man_elem_header *hdr) 486 { 487 const struct sof_ext_man_cavs_config_data *config_data = 488 container_of(hdr, struct sof_ext_man_cavs_config_data, hdr); 489 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 490 int i, elem_num; 491 492 /* calculate total number of config data elements */ 493 elem_num = (hdr->size - sizeof(struct sof_ext_man_elem_header)) 494 / sizeof(struct sof_config_elem); 495 if (elem_num <= 0) { 496 dev_err(sdev->dev, "cavs config data is inconsistent: %d\n", elem_num); 497 return -EINVAL; 498 } 499 500 for (i = 0; i < elem_num; i++) 501 switch (config_data->elems[i].token) { 502 case SOF_EXT_MAN_CAVS_CONFIG_EMPTY: 503 /* skip empty token */ 504 break; 505 case SOF_EXT_MAN_CAVS_CONFIG_CAVS_LPRO: 506 hda->clk_config_lpro = config_data->elems[i].value; 507 dev_dbg(sdev->dev, "FW clock config: %s\n", 508 hda->clk_config_lpro ? "LPRO" : "HPRO"); 509 break; 510 case SOF_EXT_MAN_CAVS_CONFIG_OUTBOX_SIZE: 511 case SOF_EXT_MAN_CAVS_CONFIG_INBOX_SIZE: 512 /* These elements are defined but not being used yet. No warn is required */ 513 break; 514 default: 515 dev_info(sdev->dev, "unsupported token type: %d\n", 516 config_data->elems[i].token); 517 } 518 519 return 0; 520 } 521