1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // 10 11 /* 12 * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail. 13 */ 14 15 #include <linux/module.h> 16 #include <sound/sof.h> 17 #include <sound/sof/xtensa.h> 18 #include <sound/soc-acpi.h> 19 #include <sound/soc-acpi-intel-match.h> 20 #include <sound/intel-dsp-config.h> 21 #include "../ops.h" 22 #include "shim.h" 23 #include "../sof-acpi-dev.h" 24 #include "../sof-audio.h" 25 #include "../../intel/common/soc-intel-quirks.h" 26 27 /* DSP memories */ 28 #define IRAM_OFFSET 0x0C0000 29 #define IRAM_SIZE (80 * 1024) 30 #define DRAM_OFFSET 0x100000 31 #define DRAM_SIZE (160 * 1024) 32 #define SHIM_OFFSET 0x140000 33 #define SHIM_SIZE_BYT 0x100 34 #define SHIM_SIZE_CHT 0x118 35 #define MBOX_OFFSET 0x144000 36 #define MBOX_SIZE 0x1000 37 #define EXCEPT_OFFSET 0x800 38 #define EXCEPT_MAX_HDR_SIZE 0x400 39 40 /* DSP peripherals */ 41 #define DMAC0_OFFSET 0x098000 42 #define DMAC1_OFFSET 0x09c000 43 #define DMAC2_OFFSET 0x094000 44 #define DMAC_SIZE 0x420 45 #define SSP0_OFFSET 0x0a0000 46 #define SSP1_OFFSET 0x0a1000 47 #define SSP2_OFFSET 0x0a2000 48 #define SSP3_OFFSET 0x0a4000 49 #define SSP4_OFFSET 0x0a5000 50 #define SSP5_OFFSET 0x0a6000 51 #define SSP_SIZE 0x100 52 53 #define BYT_STACK_DUMP_SIZE 32 54 55 #define BYT_PCI_BAR_SIZE 0x200000 56 57 #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32) 58 59 /* 60 * Debug 61 */ 62 63 #define MBOX_DUMP_SIZE 0x30 64 65 /* BARs */ 66 #define BYT_DSP_BAR 0 67 #define BYT_PCI_BAR 1 68 #define BYT_IMR_BAR 2 69 70 static const struct snd_sof_debugfs_map byt_debugfs[] = { 71 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 72 SOF_DEBUGFS_ACCESS_ALWAYS}, 73 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 74 SOF_DEBUGFS_ACCESS_ALWAYS}, 75 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 76 SOF_DEBUGFS_ACCESS_ALWAYS}, 77 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 78 SOF_DEBUGFS_ACCESS_ALWAYS}, 79 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 80 SOF_DEBUGFS_ACCESS_ALWAYS}, 81 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 82 SOF_DEBUGFS_ACCESS_D0_ONLY}, 83 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 84 SOF_DEBUGFS_ACCESS_D0_ONLY}, 85 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT, 86 SOF_DEBUGFS_ACCESS_ALWAYS}, 87 }; 88 89 static void byt_host_done(struct snd_sof_dev *sdev); 90 static void byt_dsp_done(struct snd_sof_dev *sdev); 91 static void byt_get_reply(struct snd_sof_dev *sdev); 92 93 /* 94 * Debug 95 */ 96 97 static void byt_get_registers(struct snd_sof_dev *sdev, 98 struct sof_ipc_dsp_oops_xtensa *xoops, 99 struct sof_ipc_panic_info *panic_info, 100 u32 *stack, size_t stack_words) 101 { 102 u32 offset = sdev->dsp_oops_offset; 103 104 /* first read regsisters */ 105 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 106 107 /* note: variable AR register array is not read */ 108 109 /* then get panic info */ 110 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 111 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 112 xoops->arch_hdr.totalsize); 113 return; 114 } 115 offset += xoops->arch_hdr.totalsize; 116 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 117 118 /* then get the stack */ 119 offset += sizeof(*panic_info); 120 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 121 } 122 123 static void byt_dump(struct snd_sof_dev *sdev, u32 flags) 124 { 125 struct sof_ipc_dsp_oops_xtensa xoops; 126 struct sof_ipc_panic_info panic_info; 127 u32 stack[BYT_STACK_DUMP_SIZE]; 128 u64 status, panic, imrd, imrx; 129 130 /* now try generic SOF status messages */ 131 status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 132 panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 133 byt_get_registers(sdev, &xoops, &panic_info, stack, 134 BYT_STACK_DUMP_SIZE); 135 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack, 136 BYT_STACK_DUMP_SIZE); 137 138 /* provide some context for firmware debug */ 139 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX); 140 imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD); 141 dev_err(sdev->dev, 142 "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n", 143 (panic & SHIM_IPCX_BUSY) ? "yes" : "no", 144 (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic); 145 dev_err(sdev->dev, 146 "error: mask host: pending %s complete %s raw 0x%llx\n", 147 (imrx & SHIM_IMRX_BUSY) ? "yes" : "no", 148 (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx); 149 dev_err(sdev->dev, 150 "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n", 151 (status & SHIM_IPCD_BUSY) ? "yes" : "no", 152 (status & SHIM_IPCD_DONE) ? "yes" : "no", status); 153 dev_err(sdev->dev, 154 "error: mask DSP: pending %s complete %s raw 0x%llx\n", 155 (imrd & SHIM_IMRD_BUSY) ? "yes" : "no", 156 (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd); 157 158 } 159 160 /* 161 * IPC Doorbell IRQ handler and thread. 162 */ 163 164 static irqreturn_t byt_irq_handler(int irq, void *context) 165 { 166 struct snd_sof_dev *sdev = context; 167 u64 ipcx, ipcd; 168 int ret = IRQ_NONE; 169 170 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 171 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 172 173 if (ipcx & SHIM_BYT_IPCX_DONE) { 174 175 /* reply message from DSP, Mask Done interrupt first */ 176 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 177 SHIM_IMRX, 178 SHIM_IMRX_DONE, 179 SHIM_IMRX_DONE); 180 ret = IRQ_WAKE_THREAD; 181 } 182 183 if (ipcd & SHIM_BYT_IPCD_BUSY) { 184 185 /* new message from DSP, Mask Busy interrupt first */ 186 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, 187 SHIM_IMRX, 188 SHIM_IMRX_BUSY, 189 SHIM_IMRX_BUSY); 190 ret = IRQ_WAKE_THREAD; 191 } 192 193 return ret; 194 } 195 196 static irqreturn_t byt_irq_thread(int irq, void *context) 197 { 198 struct snd_sof_dev *sdev = context; 199 u64 ipcx, ipcd; 200 201 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX); 202 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD); 203 204 /* reply message from DSP */ 205 if (ipcx & SHIM_BYT_IPCX_DONE) { 206 207 spin_lock_irq(&sdev->ipc_lock); 208 209 /* 210 * handle immediate reply from DSP core. If the msg is 211 * found, set done bit in cmd_done which is called at the 212 * end of message processing function, else set it here 213 * because the done bit can't be set in cmd_done function 214 * which is triggered by msg 215 */ 216 byt_get_reply(sdev); 217 snd_sof_ipc_reply(sdev, ipcx); 218 219 byt_dsp_done(sdev); 220 221 spin_unlock_irq(&sdev->ipc_lock); 222 } 223 224 /* new message from DSP */ 225 if (ipcd & SHIM_BYT_IPCD_BUSY) { 226 227 /* Handle messages from DSP Core */ 228 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 229 snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) + 230 MBOX_OFFSET); 231 } else { 232 snd_sof_ipc_msgs_rx(sdev); 233 } 234 235 byt_host_done(sdev); 236 } 237 238 return IRQ_HANDLED; 239 } 240 241 static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 242 { 243 /* unmask and prepare to receive Done interrupt */ 244 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 245 SHIM_IMRX_DONE, 0); 246 247 /* send the message */ 248 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, 249 msg->msg_size); 250 snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY); 251 252 return 0; 253 } 254 255 static void byt_get_reply(struct snd_sof_dev *sdev) 256 { 257 struct snd_sof_ipc_msg *msg = sdev->msg; 258 struct sof_ipc_reply reply; 259 int ret = 0; 260 261 /* 262 * Sometimes, there is unexpected reply ipc arriving. The reply 263 * ipc belongs to none of the ipcs sent from driver. 264 * In this case, the driver must ignore the ipc. 265 */ 266 if (!msg) { 267 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n"); 268 return; 269 } 270 271 /* get reply */ 272 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); 273 274 if (reply.error < 0) { 275 memcpy(msg->reply_data, &reply, sizeof(reply)); 276 ret = reply.error; 277 } else { 278 /* reply correct size ? */ 279 if (reply.hdr.size != msg->reply_size) { 280 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", 281 msg->reply_size, reply.hdr.size); 282 ret = -EINVAL; 283 } 284 285 /* read the message */ 286 if (msg->reply_size > 0) 287 sof_mailbox_read(sdev, sdev->host_box.offset, 288 msg->reply_data, msg->reply_size); 289 } 290 291 msg->reply_error = ret; 292 } 293 294 static int byt_get_mailbox_offset(struct snd_sof_dev *sdev) 295 { 296 return MBOX_OFFSET; 297 } 298 299 static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id) 300 { 301 return MBOX_OFFSET; 302 } 303 304 static void byt_host_done(struct snd_sof_dev *sdev) 305 { 306 /* clear BUSY bit and set DONE bit - accept new messages */ 307 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD, 308 SHIM_BYT_IPCD_BUSY | 309 SHIM_BYT_IPCD_DONE, 310 SHIM_BYT_IPCD_DONE); 311 312 /* unmask and prepare to receive next new message */ 313 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX, 314 SHIM_IMRX_BUSY, 0); 315 } 316 317 static void byt_dsp_done(struct snd_sof_dev *sdev) 318 { 319 /* clear DONE bit - tell DSP we have completed */ 320 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX, 321 SHIM_BYT_IPCX_DONE, 0); 322 } 323 324 /* 325 * DSP control. 326 */ 327 328 static int byt_run(struct snd_sof_dev *sdev) 329 { 330 int tries = 10; 331 332 /* release stall and wait to unstall */ 333 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 334 SHIM_BYT_CSR_STALL, 0x0); 335 while (tries--) { 336 if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) & 337 SHIM_BYT_CSR_PWAITMODE)) 338 break; 339 msleep(100); 340 } 341 if (tries < 0) { 342 dev_err(sdev->dev, "error: unable to run DSP firmware\n"); 343 byt_dump(sdev, SOF_DBG_DUMP_REGS | SOF_DBG_DUMP_MBOX); 344 return -ENODEV; 345 } 346 347 /* return init core mask */ 348 return 1; 349 } 350 351 static int byt_reset(struct snd_sof_dev *sdev) 352 { 353 /* put DSP into reset, set reset vector and stall */ 354 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 355 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 356 SHIM_BYT_CSR_STALL, 357 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL | 358 SHIM_BYT_CSR_STALL); 359 360 usleep_range(10, 15); 361 362 /* take DSP out of reset and keep stalled for FW loading */ 363 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 364 SHIM_BYT_CSR_RST, 0); 365 366 return 0; 367 } 368 369 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 370 const char *sof_tplg_filename, 371 const char *ssp_str) 372 { 373 const char *tplg_filename = NULL; 374 char *filename; 375 char *split_ext; 376 377 filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL); 378 if (!filename) 379 return NULL; 380 381 /* this assumes a .tplg extension */ 382 split_ext = strsep(&filename, "."); 383 if (split_ext) { 384 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 385 "%s-%s.tplg", 386 split_ext, ssp_str); 387 if (!tplg_filename) 388 return NULL; 389 } 390 return tplg_filename; 391 } 392 393 static void byt_machine_select(struct snd_sof_dev *sdev) 394 { 395 struct snd_sof_pdata *sof_pdata = sdev->pdata; 396 const struct sof_dev_desc *desc = sof_pdata->desc; 397 struct snd_soc_acpi_mach *mach; 398 struct platform_device *pdev; 399 const char *tplg_filename; 400 401 mach = snd_soc_acpi_find_machine(desc->machines); 402 if (!mach) { 403 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 404 return; 405 } 406 407 pdev = to_platform_device(sdev->dev); 408 if (soc_intel_is_byt_cr(pdev)) { 409 dev_dbg(sdev->dev, 410 "BYT-CR detected, SSP0 used instead of SSP2\n"); 411 412 tplg_filename = fixup_tplg_name(sdev, 413 mach->sof_tplg_filename, 414 "ssp0"); 415 } else { 416 tplg_filename = mach->sof_tplg_filename; 417 } 418 419 if (!tplg_filename) { 420 dev_dbg(sdev->dev, 421 "error: no topology filename\n"); 422 return; 423 } 424 425 sof_pdata->tplg_filename = tplg_filename; 426 mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc; 427 sof_pdata->machine = mach; 428 } 429 430 /* Baytrail DAIs */ 431 static struct snd_soc_dai_driver byt_dai[] = { 432 { 433 .name = "ssp0-port", 434 .playback = { 435 .channels_min = 1, 436 .channels_max = 8, 437 }, 438 .capture = { 439 .channels_min = 1, 440 .channels_max = 8, 441 }, 442 }, 443 { 444 .name = "ssp1-port", 445 .playback = { 446 .channels_min = 1, 447 .channels_max = 8, 448 }, 449 .capture = { 450 .channels_min = 1, 451 .channels_max = 8, 452 }, 453 }, 454 { 455 .name = "ssp2-port", 456 .playback = { 457 .channels_min = 1, 458 .channels_max = 8, 459 }, 460 .capture = { 461 .channels_min = 1, 462 .channels_max = 8, 463 } 464 }, 465 { 466 .name = "ssp3-port", 467 .playback = { 468 .channels_min = 1, 469 .channels_max = 8, 470 }, 471 .capture = { 472 .channels_min = 1, 473 .channels_max = 8, 474 }, 475 }, 476 { 477 .name = "ssp4-port", 478 .playback = { 479 .channels_min = 1, 480 .channels_max = 8, 481 }, 482 .capture = { 483 .channels_min = 1, 484 .channels_max = 8, 485 }, 486 }, 487 { 488 .name = "ssp5-port", 489 .playback = { 490 .channels_min = 1, 491 .channels_max = 8, 492 }, 493 .capture = { 494 .channels_min = 1, 495 .channels_max = 8, 496 }, 497 }, 498 }; 499 500 static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach, 501 struct snd_sof_dev *sdev) 502 { 503 struct snd_sof_pdata *pdata = sdev->pdata; 504 const struct sof_dev_desc *desc = pdata->desc; 505 struct snd_soc_acpi_mach_params *mach_params; 506 507 mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params; 508 mach_params->platform = dev_name(sdev->dev); 509 mach_params->num_dai_drivers = desc->ops->num_drv; 510 mach_params->dai_drivers = desc->ops->drv; 511 } 512 513 /* 514 * Probe and remove. 515 */ 516 517 #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD) 518 519 static int tangier_pci_probe(struct snd_sof_dev *sdev) 520 { 521 struct snd_sof_pdata *pdata = sdev->pdata; 522 const struct sof_dev_desc *desc = pdata->desc; 523 struct pci_dev *pci = to_pci_dev(sdev->dev); 524 u32 base, size; 525 int ret; 526 527 /* DSP DMA can only access low 31 bits of host memory */ 528 ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31)); 529 if (ret < 0) { 530 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 531 return ret; 532 } 533 534 /* LPE base */ 535 base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; 536 size = BYT_PCI_BAR_SIZE; 537 538 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 539 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 540 if (!sdev->bar[BYT_DSP_BAR]) { 541 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 542 base, size); 543 return -ENODEV; 544 } 545 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 546 547 /* IMR base - optional */ 548 if (desc->resindex_imr_base == -1) 549 goto irq; 550 551 base = pci_resource_start(pci, desc->resindex_imr_base); 552 size = pci_resource_len(pci, desc->resindex_imr_base); 553 554 /* some BIOSes don't map IMR */ 555 if (base == 0x55aa55aa || base == 0x0) { 556 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 557 goto irq; 558 } 559 560 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 561 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 562 if (!sdev->bar[BYT_IMR_BAR]) { 563 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 564 base, size); 565 return -ENODEV; 566 } 567 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 568 569 irq: 570 /* register our IRQ */ 571 sdev->ipc_irq = pci->irq; 572 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 573 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 574 byt_irq_handler, byt_irq_thread, 575 0, "AudioDSP", sdev); 576 if (ret < 0) { 577 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 578 sdev->ipc_irq); 579 return ret; 580 } 581 582 /* enable BUSY and disable DONE Interrupt by default */ 583 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 584 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 585 SHIM_IMRX_DONE); 586 587 /* set default mailbox offset for FW ready message */ 588 sdev->dsp_box.offset = MBOX_OFFSET; 589 590 return ret; 591 } 592 593 const struct snd_sof_dsp_ops sof_tng_ops = { 594 /* device init */ 595 .probe = tangier_pci_probe, 596 597 /* DSP core boot / reset */ 598 .run = byt_run, 599 .reset = byt_reset, 600 601 /* Register IO */ 602 .write = sof_io_write, 603 .read = sof_io_read, 604 .write64 = sof_io_write64, 605 .read64 = sof_io_read64, 606 607 /* Block IO */ 608 .block_read = sof_block_read, 609 .block_write = sof_block_write, 610 611 /* doorbell */ 612 .irq_handler = byt_irq_handler, 613 .irq_thread = byt_irq_thread, 614 615 /* ipc */ 616 .send_msg = byt_send_msg, 617 .fw_ready = sof_fw_ready, 618 .get_mailbox_offset = byt_get_mailbox_offset, 619 .get_window_offset = byt_get_window_offset, 620 621 .ipc_msg_data = intel_ipc_msg_data, 622 .ipc_pcm_params = intel_ipc_pcm_params, 623 624 /* machine driver */ 625 .machine_select = byt_machine_select, 626 .machine_register = sof_machine_register, 627 .machine_unregister = sof_machine_unregister, 628 .set_mach_params = byt_set_mach_params, 629 630 /* debug */ 631 .debug_map = byt_debugfs, 632 .debug_map_count = ARRAY_SIZE(byt_debugfs), 633 .dbg_dump = byt_dump, 634 635 /* stream callbacks */ 636 .pcm_open = intel_pcm_open, 637 .pcm_close = intel_pcm_close, 638 639 /* module loading */ 640 .load_module = snd_sof_parse_module_memcpy, 641 642 /*Firmware loading */ 643 .load_firmware = snd_sof_load_firmware_memcpy, 644 645 /* DAI drivers */ 646 .drv = byt_dai, 647 .num_drv = 3, /* we have only 3 SSPs on byt*/ 648 649 /* ALSA HW info flags */ 650 .hw_info = SNDRV_PCM_INFO_MMAP | 651 SNDRV_PCM_INFO_MMAP_VALID | 652 SNDRV_PCM_INFO_INTERLEAVED | 653 SNDRV_PCM_INFO_PAUSE | 654 SNDRV_PCM_INFO_BATCH, 655 656 .arch_ops = &sof_xtensa_arch_ops, 657 }; 658 EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); 659 660 const struct sof_intel_dsp_desc tng_chip_info = { 661 .cores_num = 1, 662 .host_managed_cores_mask = 1, 663 }; 664 EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); 665 666 #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */ 667 668 #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) 669 670 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev) 671 { 672 /* Disable Interrupt from both sides */ 673 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3); 674 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3); 675 676 /* Put DSP into reset, set reset vector */ 677 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR, 678 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL, 679 SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL); 680 } 681 682 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state) 683 { 684 byt_reset_dsp_disable_int(sdev); 685 686 return 0; 687 } 688 689 static int byt_resume(struct snd_sof_dev *sdev) 690 { 691 /* enable BUSY and disable DONE Interrupt by default */ 692 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 693 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 694 SHIM_IMRX_DONE); 695 696 return 0; 697 } 698 699 static int byt_remove(struct snd_sof_dev *sdev) 700 { 701 byt_reset_dsp_disable_int(sdev); 702 703 return 0; 704 } 705 706 static const struct snd_sof_debugfs_map cht_debugfs[] = { 707 {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE, 708 SOF_DEBUGFS_ACCESS_ALWAYS}, 709 {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE, 710 SOF_DEBUGFS_ACCESS_ALWAYS}, 711 {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE, 712 SOF_DEBUGFS_ACCESS_ALWAYS}, 713 {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE, 714 SOF_DEBUGFS_ACCESS_ALWAYS}, 715 {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE, 716 SOF_DEBUGFS_ACCESS_ALWAYS}, 717 {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE, 718 SOF_DEBUGFS_ACCESS_ALWAYS}, 719 {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE, 720 SOF_DEBUGFS_ACCESS_ALWAYS}, 721 {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE, 722 SOF_DEBUGFS_ACCESS_ALWAYS}, 723 {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE, 724 SOF_DEBUGFS_ACCESS_ALWAYS}, 725 {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE, 726 SOF_DEBUGFS_ACCESS_D0_ONLY}, 727 {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE, 728 SOF_DEBUGFS_ACCESS_D0_ONLY}, 729 {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT, 730 SOF_DEBUGFS_ACCESS_ALWAYS}, 731 }; 732 733 static int byt_acpi_probe(struct snd_sof_dev *sdev) 734 { 735 struct snd_sof_pdata *pdata = sdev->pdata; 736 const struct sof_dev_desc *desc = pdata->desc; 737 struct platform_device *pdev = 738 container_of(sdev->dev, struct platform_device, dev); 739 struct resource *mmio; 740 u32 base, size; 741 int ret; 742 743 /* DSP DMA can only access low 31 bits of host memory */ 744 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31)); 745 if (ret < 0) { 746 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret); 747 return ret; 748 } 749 750 /* LPE base */ 751 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 752 desc->resindex_lpe_base); 753 if (mmio) { 754 base = mmio->start; 755 size = resource_size(mmio); 756 } else { 757 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n", 758 desc->resindex_lpe_base); 759 return -EINVAL; 760 } 761 762 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); 763 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); 764 if (!sdev->bar[BYT_DSP_BAR]) { 765 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n", 766 base, size); 767 return -ENODEV; 768 } 769 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]); 770 771 /* TODO: add offsets */ 772 sdev->mmio_bar = BYT_DSP_BAR; 773 sdev->mailbox_bar = BYT_DSP_BAR; 774 775 /* IMR base - optional */ 776 if (desc->resindex_imr_base == -1) 777 goto irq; 778 779 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 780 desc->resindex_imr_base); 781 if (mmio) { 782 base = mmio->start; 783 size = resource_size(mmio); 784 } else { 785 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n", 786 desc->resindex_imr_base); 787 return -ENODEV; 788 } 789 790 /* some BIOSes don't map IMR */ 791 if (base == 0x55aa55aa || base == 0x0) { 792 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n"); 793 goto irq; 794 } 795 796 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); 797 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); 798 if (!sdev->bar[BYT_IMR_BAR]) { 799 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n", 800 base, size); 801 return -ENODEV; 802 } 803 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]); 804 805 irq: 806 /* register our IRQ */ 807 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc); 808 if (sdev->ipc_irq < 0) 809 return sdev->ipc_irq; 810 811 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq); 812 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq, 813 byt_irq_handler, byt_irq_thread, 814 IRQF_SHARED, "AudioDSP", sdev); 815 if (ret < 0) { 816 dev_err(sdev->dev, "error: failed to register IRQ %d\n", 817 sdev->ipc_irq); 818 return ret; 819 } 820 821 /* enable BUSY and disable DONE Interrupt by default */ 822 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 823 SHIM_IMRX_BUSY | SHIM_IMRX_DONE, 824 SHIM_IMRX_DONE); 825 826 /* set default mailbox offset for FW ready message */ 827 sdev->dsp_box.offset = MBOX_OFFSET; 828 829 return ret; 830 } 831 832 /* baytrail ops */ 833 static const struct snd_sof_dsp_ops sof_byt_ops = { 834 /* device init */ 835 .probe = byt_acpi_probe, 836 .remove = byt_remove, 837 838 /* DSP core boot / reset */ 839 .run = byt_run, 840 .reset = byt_reset, 841 842 /* Register IO */ 843 .write = sof_io_write, 844 .read = sof_io_read, 845 .write64 = sof_io_write64, 846 .read64 = sof_io_read64, 847 848 /* Block IO */ 849 .block_read = sof_block_read, 850 .block_write = sof_block_write, 851 852 /* doorbell */ 853 .irq_handler = byt_irq_handler, 854 .irq_thread = byt_irq_thread, 855 856 /* ipc */ 857 .send_msg = byt_send_msg, 858 .fw_ready = sof_fw_ready, 859 .get_mailbox_offset = byt_get_mailbox_offset, 860 .get_window_offset = byt_get_window_offset, 861 862 .ipc_msg_data = intel_ipc_msg_data, 863 .ipc_pcm_params = intel_ipc_pcm_params, 864 865 /* machine driver */ 866 .machine_select = byt_machine_select, 867 .machine_register = sof_machine_register, 868 .machine_unregister = sof_machine_unregister, 869 .set_mach_params = byt_set_mach_params, 870 871 /* debug */ 872 .debug_map = byt_debugfs, 873 .debug_map_count = ARRAY_SIZE(byt_debugfs), 874 .dbg_dump = byt_dump, 875 876 /* stream callbacks */ 877 .pcm_open = intel_pcm_open, 878 .pcm_close = intel_pcm_close, 879 880 /* module loading */ 881 .load_module = snd_sof_parse_module_memcpy, 882 883 /*Firmware loading */ 884 .load_firmware = snd_sof_load_firmware_memcpy, 885 886 /* PM */ 887 .suspend = byt_suspend, 888 .resume = byt_resume, 889 890 /* DAI drivers */ 891 .drv = byt_dai, 892 .num_drv = 3, /* we have only 3 SSPs on byt*/ 893 894 /* ALSA HW info flags */ 895 .hw_info = SNDRV_PCM_INFO_MMAP | 896 SNDRV_PCM_INFO_MMAP_VALID | 897 SNDRV_PCM_INFO_INTERLEAVED | 898 SNDRV_PCM_INFO_PAUSE | 899 SNDRV_PCM_INFO_BATCH, 900 901 .arch_ops = &sof_xtensa_arch_ops, 902 }; 903 904 static const struct sof_intel_dsp_desc byt_chip_info = { 905 .cores_num = 1, 906 .host_managed_cores_mask = 1, 907 }; 908 909 /* cherrytrail and braswell ops */ 910 static const struct snd_sof_dsp_ops sof_cht_ops = { 911 /* device init */ 912 .probe = byt_acpi_probe, 913 .remove = byt_remove, 914 915 /* DSP core boot / reset */ 916 .run = byt_run, 917 .reset = byt_reset, 918 919 /* Register IO */ 920 .write = sof_io_write, 921 .read = sof_io_read, 922 .write64 = sof_io_write64, 923 .read64 = sof_io_read64, 924 925 /* Block IO */ 926 .block_read = sof_block_read, 927 .block_write = sof_block_write, 928 929 /* doorbell */ 930 .irq_handler = byt_irq_handler, 931 .irq_thread = byt_irq_thread, 932 933 /* ipc */ 934 .send_msg = byt_send_msg, 935 .fw_ready = sof_fw_ready, 936 .get_mailbox_offset = byt_get_mailbox_offset, 937 .get_window_offset = byt_get_window_offset, 938 939 .ipc_msg_data = intel_ipc_msg_data, 940 .ipc_pcm_params = intel_ipc_pcm_params, 941 942 /* machine driver */ 943 .machine_select = byt_machine_select, 944 .machine_register = sof_machine_register, 945 .machine_unregister = sof_machine_unregister, 946 .set_mach_params = byt_set_mach_params, 947 948 /* debug */ 949 .debug_map = cht_debugfs, 950 .debug_map_count = ARRAY_SIZE(cht_debugfs), 951 .dbg_dump = byt_dump, 952 953 /* stream callbacks */ 954 .pcm_open = intel_pcm_open, 955 .pcm_close = intel_pcm_close, 956 957 /* module loading */ 958 .load_module = snd_sof_parse_module_memcpy, 959 960 /*Firmware loading */ 961 .load_firmware = snd_sof_load_firmware_memcpy, 962 963 /* PM */ 964 .suspend = byt_suspend, 965 .resume = byt_resume, 966 967 /* DAI drivers */ 968 .drv = byt_dai, 969 /* all 6 SSPs may be available for cherrytrail */ 970 .num_drv = ARRAY_SIZE(byt_dai), 971 972 /* ALSA HW info flags */ 973 .hw_info = SNDRV_PCM_INFO_MMAP | 974 SNDRV_PCM_INFO_MMAP_VALID | 975 SNDRV_PCM_INFO_INTERLEAVED | 976 SNDRV_PCM_INFO_PAUSE | 977 SNDRV_PCM_INFO_BATCH, 978 979 .arch_ops = &sof_xtensa_arch_ops, 980 }; 981 982 static const struct sof_intel_dsp_desc cht_chip_info = { 983 .cores_num = 1, 984 .host_managed_cores_mask = 1, 985 }; 986 987 /* BYTCR uses different IRQ index */ 988 static const struct sof_dev_desc sof_acpi_baytrailcr_desc = { 989 .machines = snd_soc_acpi_intel_baytrail_machines, 990 .resindex_lpe_base = 0, 991 .resindex_pcicfg_base = 1, 992 .resindex_imr_base = 2, 993 .irqindex_host_ipc = 0, 994 .chip_info = &byt_chip_info, 995 .default_fw_path = "intel/sof", 996 .default_tplg_path = "intel/sof-tplg", 997 .default_fw_filename = "sof-byt.ri", 998 .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 999 .ops = &sof_byt_ops, 1000 }; 1001 1002 static const struct sof_dev_desc sof_acpi_baytrail_desc = { 1003 .machines = snd_soc_acpi_intel_baytrail_machines, 1004 .resindex_lpe_base = 0, 1005 .resindex_pcicfg_base = 1, 1006 .resindex_imr_base = 2, 1007 .irqindex_host_ipc = 5, 1008 .chip_info = &byt_chip_info, 1009 .default_fw_path = "intel/sof", 1010 .default_tplg_path = "intel/sof-tplg", 1011 .default_fw_filename = "sof-byt.ri", 1012 .nocodec_tplg_filename = "sof-byt-nocodec.tplg", 1013 .ops = &sof_byt_ops, 1014 }; 1015 1016 static const struct sof_dev_desc sof_acpi_cherrytrail_desc = { 1017 .machines = snd_soc_acpi_intel_cherrytrail_machines, 1018 .resindex_lpe_base = 0, 1019 .resindex_pcicfg_base = 1, 1020 .resindex_imr_base = 2, 1021 .irqindex_host_ipc = 5, 1022 .chip_info = &cht_chip_info, 1023 .default_fw_path = "intel/sof", 1024 .default_tplg_path = "intel/sof-tplg", 1025 .default_fw_filename = "sof-cht.ri", 1026 .nocodec_tplg_filename = "sof-cht-nocodec.tplg", 1027 .ops = &sof_cht_ops, 1028 }; 1029 1030 static const struct acpi_device_id sof_baytrail_match[] = { 1031 { "80860F28", (unsigned long)&sof_acpi_baytrail_desc }, 1032 { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc }, 1033 { } 1034 }; 1035 MODULE_DEVICE_TABLE(acpi, sof_baytrail_match); 1036 1037 static int sof_baytrail_probe(struct platform_device *pdev) 1038 { 1039 struct device *dev = &pdev->dev; 1040 const struct sof_dev_desc *desc; 1041 const struct acpi_device_id *id; 1042 int ret; 1043 1044 id = acpi_match_device(dev->driver->acpi_match_table, dev); 1045 if (!id) 1046 return -ENODEV; 1047 1048 ret = snd_intel_acpi_dsp_driver_probe(dev, id->id); 1049 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1050 dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n"); 1051 return -ENODEV; 1052 } 1053 1054 desc = device_get_match_data(&pdev->dev); 1055 if (!desc) 1056 return -ENODEV; 1057 1058 if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev)) 1059 desc = &sof_acpi_baytrailcr_desc; 1060 1061 return sof_acpi_probe(pdev, desc); 1062 } 1063 1064 /* acpi_driver definition */ 1065 static struct platform_driver snd_sof_acpi_intel_byt_driver = { 1066 .probe = sof_baytrail_probe, 1067 .remove = sof_acpi_remove, 1068 .driver = { 1069 .name = "sof-audio-acpi-intel-byt", 1070 .pm = &sof_acpi_pm, 1071 .acpi_match_table = sof_baytrail_match, 1072 }, 1073 }; 1074 module_platform_driver(snd_sof_acpi_intel_byt_driver); 1075 1076 #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */ 1077 1078 MODULE_LICENSE("Dual BSD/GPL"); 1079 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC); 1080 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1081 MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV); 1082