1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // Copyright 2020-2025 NXP 4 // 5 // Common helpers for the audio DSP on i.MX8 6 7 #include <linux/firmware/imx/dsp.h> 8 #include <linux/module.h> 9 #include <linux/of_address.h> 10 #include <linux/of_reserved_mem.h> 11 #include <linux/pm_domain.h> 12 #include <sound/sof/xtensa.h> 13 14 #include "../ops.h" 15 16 #include "imx-common.h" 17 18 /** 19 * imx8_get_registers() - This function is called in case of DSP oops 20 * in order to gather information about the registers, filename and 21 * linenumber and stack. 22 * @sdev: SOF device 23 * @xoops: Stores information about registers. 24 * @panic_info: Stores information about filename and line number. 25 * @stack: Stores the stack dump. 26 * @stack_words: Size of the stack dump. 27 */ 28 void imx8_get_registers(struct snd_sof_dev *sdev, 29 struct sof_ipc_dsp_oops_xtensa *xoops, 30 struct sof_ipc_panic_info *panic_info, 31 u32 *stack, size_t stack_words) 32 { 33 u32 offset = sdev->dsp_oops_offset; 34 35 /* first read registers */ 36 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 37 38 /* then get panic info */ 39 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 40 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 41 xoops->arch_hdr.totalsize); 42 return; 43 } 44 offset += xoops->arch_hdr.totalsize; 45 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info)); 46 47 /* then get the stack */ 48 offset += sizeof(*panic_info); 49 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32)); 50 } 51 52 /** 53 * imx8_dump() - This function is called when a panic message is 54 * received from the firmware. 55 * @sdev: SOF device 56 * @flags: parameter not used but required by ops prototype 57 */ 58 void imx8_dump(struct snd_sof_dev *sdev, u32 flags) 59 { 60 struct sof_ipc_dsp_oops_xtensa xoops; 61 struct sof_ipc_panic_info panic_info; 62 u32 stack[IMX8_STACK_DUMP_SIZE]; 63 u32 status; 64 65 /* Get information about the panic status from the debug box area. 66 * Compute the trace point based on the status. 67 */ 68 sof_mailbox_read(sdev, sdev->debug_box.offset + 0x4, &status, 4); 69 70 /* Get information about the registers, the filename and line 71 * number and the stack. 72 */ 73 imx8_get_registers(sdev, &xoops, &panic_info, stack, 74 IMX8_STACK_DUMP_SIZE); 75 76 /* Print the information to the console */ 77 sof_print_oops_and_stack(sdev, KERN_ERR, status, status, &xoops, 78 &panic_info, stack, IMX8_STACK_DUMP_SIZE); 79 } 80 EXPORT_SYMBOL(imx8_dump); 81 82 static void imx_handle_reply(struct imx_dsp_ipc *ipc) 83 { 84 struct snd_sof_dev *sdev = imx_dsp_get_data(ipc); 85 86 guard(spinlock_irqsave)(&sdev->ipc_lock); 87 snd_sof_ipc_process_reply(sdev, 0); 88 } 89 90 static void imx_handle_request(struct imx_dsp_ipc *ipc) 91 { 92 struct snd_sof_dev *sdev; 93 u32 panic_code; 94 95 sdev = imx_dsp_get_data(ipc); 96 97 if (get_chip_info(sdev)->ipc_info.has_panic_code) { 98 sof_mailbox_read(sdev, sdev->debug_box.offset + 0x4, 99 &panic_code, 100 sizeof(panic_code)); 101 102 if ((panic_code & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { 103 snd_sof_dsp_panic(sdev, panic_code, true); 104 return; 105 } 106 } 107 108 snd_sof_ipc_msgs_rx(sdev); 109 } 110 111 static struct imx_dsp_ops imx_ipc_ops = { 112 .handle_reply = imx_handle_reply, 113 .handle_request = imx_handle_request, 114 }; 115 116 static int imx_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) 117 { 118 struct imx_common_data *common = sdev->pdata->hw_pdata; 119 120 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, msg->msg_size); 121 imx_dsp_ring_doorbell(common->ipc_handle, 0x0); 122 123 return 0; 124 } 125 126 static int imx_get_bar_index(struct snd_sof_dev *sdev, u32 type) 127 { 128 switch (type) { 129 case SOF_FW_BLK_TYPE_IRAM: 130 case SOF_FW_BLK_TYPE_SRAM: 131 return type; 132 default: 133 return -EINVAL; 134 } 135 } 136 137 static int imx_get_mailbox_offset(struct snd_sof_dev *sdev) 138 { 139 return get_chip_info(sdev)->ipc_info.boot_mbox_offset; 140 } 141 142 static int imx_get_window_offset(struct snd_sof_dev *sdev, u32 id) 143 { 144 return get_chip_info(sdev)->ipc_info.window_offset; 145 } 146 147 static int imx_set_power_state(struct snd_sof_dev *sdev, 148 const struct sof_dsp_power_state *target) 149 { 150 sdev->dsp_power_state = *target; 151 152 return 0; 153 } 154 155 static int imx_common_resume(struct snd_sof_dev *sdev) 156 { 157 struct imx_common_data *common; 158 int ret, i; 159 160 common = sdev->pdata->hw_pdata; 161 162 ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 163 if (ret) 164 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret); 165 166 for (i = 0; i < DSP_MU_CHAN_NUM; i++) 167 imx_dsp_request_channel(common->ipc_handle, i); 168 169 /* done. If need be, core will be started by SOF core immediately after */ 170 return 0; 171 } 172 173 static int imx_common_suspend(struct snd_sof_dev *sdev) 174 { 175 struct imx_common_data *common; 176 int i, ret; 177 178 common = sdev->pdata->hw_pdata; 179 180 ret = imx_chip_core_shutdown(sdev); 181 if (ret < 0) { 182 dev_err(sdev->dev, "failed to shutdown core: %d\n", ret); 183 return ret; 184 } 185 186 for (i = 0; i < DSP_MU_CHAN_NUM; i++) 187 imx_dsp_free_channel(common->ipc_handle, i); 188 189 clk_bulk_disable_unprepare(common->clk_num, common->clks); 190 191 return 0; 192 } 193 194 static int imx_runtime_resume(struct snd_sof_dev *sdev) 195 { 196 const struct sof_dsp_power_state target_state = { 197 .state = SOF_DSP_PM_D0, 198 }; 199 int ret; 200 201 ret = imx_common_resume(sdev); 202 if (ret < 0) { 203 dev_err(sdev->dev, "failed to runtime common resume: %d\n", ret); 204 return ret; 205 } 206 207 return snd_sof_dsp_set_power_state(sdev, &target_state); 208 } 209 210 static int imx_resume(struct snd_sof_dev *sdev) 211 { 212 const struct sof_dsp_power_state target_state = { 213 .state = SOF_DSP_PM_D0, 214 }; 215 int ret; 216 217 ret = imx_common_resume(sdev); 218 if (ret < 0) { 219 dev_err(sdev->dev, "failed to common resume: %d\n", ret); 220 return ret; 221 } 222 223 if (pm_runtime_suspended(sdev->dev)) { 224 pm_runtime_disable(sdev->dev); 225 pm_runtime_set_active(sdev->dev); 226 pm_runtime_mark_last_busy(sdev->dev); 227 pm_runtime_enable(sdev->dev); 228 pm_runtime_idle(sdev->dev); 229 } 230 231 return snd_sof_dsp_set_power_state(sdev, &target_state); 232 } 233 234 static int imx_runtime_suspend(struct snd_sof_dev *sdev) 235 { 236 const struct sof_dsp_power_state target_state = { 237 .state = SOF_DSP_PM_D3, 238 }; 239 int ret; 240 241 ret = imx_common_suspend(sdev); 242 if (ret < 0) 243 dev_err(sdev->dev, "failed to runtime common suspend: %d\n", ret); 244 245 return snd_sof_dsp_set_power_state(sdev, &target_state); 246 } 247 248 static int imx_suspend(struct snd_sof_dev *sdev, unsigned int target_state) 249 { 250 const struct sof_dsp_power_state target_power_state = { 251 .state = target_state, 252 }; 253 int ret; 254 255 if (!pm_runtime_suspended(sdev->dev)) { 256 ret = imx_common_suspend(sdev); 257 if (ret < 0) { 258 dev_err(sdev->dev, "failed to common suspend: %d\n", ret); 259 return ret; 260 } 261 } 262 263 return snd_sof_dsp_set_power_state(sdev, &target_power_state); 264 } 265 266 static int imx_region_name_to_blk_type(const char *region_name) 267 { 268 if (!strcmp(region_name, "iram")) 269 return SOF_FW_BLK_TYPE_IRAM; 270 else if (!strcmp(region_name, "dram")) 271 return SOF_FW_BLK_TYPE_DRAM; 272 else if (!strcmp(region_name, "sram")) 273 return SOF_FW_BLK_TYPE_SRAM; 274 else 275 return -EINVAL; 276 } 277 278 static int imx_parse_ioremap_memory(struct snd_sof_dev *sdev) 279 { 280 const struct imx_chip_info *chip_info; 281 struct platform_device *pdev; 282 struct resource *res, _res; 283 int i, blk_type, ret; 284 285 pdev = to_platform_device(sdev->dev); 286 chip_info = get_chip_info(sdev); 287 288 for (i = 0; chip_info->memory[i].name; i++) { 289 blk_type = imx_region_name_to_blk_type(chip_info->memory[i].name); 290 if (blk_type < 0) 291 return dev_err_probe(sdev->dev, blk_type, 292 "no blk type for region %s\n", 293 chip_info->memory[i].name); 294 295 if (!chip_info->memory[i].reserved) { 296 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 297 chip_info->memory[i].name); 298 if (!res) 299 return dev_err_probe(sdev->dev, -ENODEV, 300 "failed to fetch %s resource\n", 301 chip_info->memory[i].name); 302 303 } else { 304 ret = of_reserved_mem_region_to_resource_byname(pdev->dev.of_node, 305 chip_info->memory[i].name, 306 &_res); 307 if (ret < 0) 308 return dev_err_probe(sdev->dev, ret, 309 "no valid entry for %s\n", 310 chip_info->memory[i].name); 311 res = &_res; 312 } 313 314 sdev->bar[blk_type] = devm_ioremap_resource(sdev->dev, res); 315 if (IS_ERR(sdev->bar[blk_type])) 316 return dev_err_probe(sdev->dev, 317 PTR_ERR(sdev->bar[blk_type]), 318 "failed to ioremap %s region\n", 319 chip_info->memory[i].name); 320 } 321 322 return 0; 323 } 324 325 static void imx_unregister_action(void *data) 326 { 327 struct imx_common_data *common; 328 struct snd_sof_dev *sdev; 329 330 sdev = data; 331 common = sdev->pdata->hw_pdata; 332 333 if (get_chip_info(sdev)->has_dma_reserved) 334 of_reserved_mem_device_release(sdev->dev); 335 336 platform_device_unregister(common->ipc_dev); 337 } 338 339 static int imx_probe(struct snd_sof_dev *sdev) 340 { 341 struct dev_pm_domain_attach_data domain_data = { 342 .pd_names = NULL, /* no filtering */ 343 .pd_flags = PD_FLAG_DEV_LINK_ON, 344 }; 345 struct imx_common_data *common; 346 struct platform_device *pdev; 347 int ret; 348 349 pdev = to_platform_device(sdev->dev); 350 351 common = devm_kzalloc(sdev->dev, sizeof(*common), GFP_KERNEL); 352 if (!common) 353 return -ENOMEM; 354 355 sdev->pdata->hw_pdata = common; 356 357 common->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp", 358 PLATFORM_DEVID_NONE, 359 pdev, sizeof(*pdev)); 360 if (IS_ERR(common->ipc_dev)) 361 return dev_err_probe(sdev->dev, PTR_ERR(common->ipc_dev), 362 "failed to create IPC device\n"); 363 364 if (get_chip_info(sdev)->has_dma_reserved) { 365 ret = of_reserved_mem_device_init_by_name(sdev->dev, 366 pdev->dev.of_node, 367 "dma"); 368 if (ret) { 369 platform_device_unregister(common->ipc_dev); 370 371 return dev_err_probe(sdev->dev, ret, 372 "failed to bind DMA region\n"); 373 } 374 } 375 376 /* let the devres API take care of the cleanup */ 377 ret = devm_add_action_or_reset(sdev->dev, 378 imx_unregister_action, 379 sdev); 380 if (ret) 381 return ret; 382 383 common->ipc_handle = dev_get_drvdata(&common->ipc_dev->dev); 384 if (!common->ipc_handle) 385 return dev_err_probe(sdev->dev, -EPROBE_DEFER, 386 "failed to fetch IPC handle\n"); 387 388 ret = imx_parse_ioremap_memory(sdev); 389 if (ret < 0) 390 return dev_err_probe(sdev->dev, ret, 391 "failed to parse/ioremap memory regions\n"); 392 393 if (!sdev->dev->pm_domain) { 394 ret = devm_pm_domain_attach_list(sdev->dev, 395 &domain_data, &common->pd_list); 396 if (ret < 0) 397 return dev_err_probe(sdev->dev, ret, "failed to attach PDs\n"); 398 } 399 400 ret = devm_clk_bulk_get_all(sdev->dev, &common->clks); 401 if (ret < 0) 402 return dev_err_probe(sdev->dev, ret, "failed to fetch clocks\n"); 403 common->clk_num = ret; 404 405 ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 406 if (ret < 0) 407 return dev_err_probe(sdev->dev, ret, "failed to enable clocks\n"); 408 409 common->ipc_handle->ops = &imx_ipc_ops; 410 imx_dsp_set_data(common->ipc_handle, sdev); 411 412 sdev->num_cores = 1; 413 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; 414 sdev->dsp_box.offset = get_chip_info(sdev)->ipc_info.boot_mbox_offset; 415 416 return imx_chip_probe(sdev); 417 } 418 419 static void imx_remove(struct snd_sof_dev *sdev) 420 { 421 struct imx_common_data *common; 422 int ret; 423 424 common = sdev->pdata->hw_pdata; 425 426 if (!pm_runtime_suspended(sdev->dev)) { 427 ret = imx_chip_core_shutdown(sdev); 428 if (ret < 0) 429 dev_err(sdev->dev, "failed to shutdown core: %d\n", ret); 430 431 clk_bulk_disable_unprepare(common->clk_num, common->clks); 432 } 433 } 434 435 const struct snd_sof_dsp_ops sof_imx_ops = { 436 .probe = imx_probe, 437 .remove = imx_remove, 438 439 .run = imx_chip_core_kick, 440 .reset = imx_chip_core_reset, 441 442 .block_read = sof_block_read, 443 .block_write = sof_block_write, 444 445 .mailbox_read = sof_mailbox_read, 446 .mailbox_write = sof_mailbox_write, 447 448 .send_msg = imx_send_msg, 449 .get_mailbox_offset = imx_get_mailbox_offset, 450 .get_window_offset = imx_get_window_offset, 451 452 .ipc_msg_data = sof_ipc_msg_data, 453 .set_stream_data_offset = sof_set_stream_data_offset, 454 455 .get_bar_index = imx_get_bar_index, 456 .load_firmware = snd_sof_load_firmware_memcpy, 457 458 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, 459 460 .pcm_open = sof_stream_pcm_open, 461 .pcm_close = sof_stream_pcm_close, 462 463 .runtime_suspend = imx_runtime_suspend, 464 .runtime_resume = imx_runtime_resume, 465 .suspend = imx_suspend, 466 .resume = imx_resume, 467 468 .set_power_state = imx_set_power_state, 469 470 .hw_info = SNDRV_PCM_INFO_MMAP | 471 SNDRV_PCM_INFO_MMAP_VALID | 472 SNDRV_PCM_INFO_INTERLEAVED | 473 SNDRV_PCM_INFO_PAUSE | 474 SNDRV_PCM_INFO_BATCH | 475 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, 476 }; 477 EXPORT_SYMBOL(sof_imx_ops); 478 479 MODULE_LICENSE("Dual BSD/GPL"); 480 MODULE_DESCRIPTION("SOF helpers for IMX platforms"); 481