1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include "../sof-priv.h" 15 16 #define ACP_MAX_STREAM 8 17 18 #define ACP_DSP_BAR 0 19 20 #define ACP_HW_SEM_RETRY_COUNT 10000 21 #define ACP_REG_POLL_INTERVAL 500 22 #define ACP_REG_POLL_TIMEOUT_US 2000 23 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 24 25 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 26 #define ACP_PGFSM_STATUS_MASK 0x03 27 #define ACP_POWERED_ON 0x00 28 #define ACP_ASSERT_RESET 0x01 29 #define ACP_RELEASE_RESET 0x00 30 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 31 32 #define ACP_DSP_INTR_EN_MASK 0x00000001 33 #define ACP_SRAM_PTE_OFFSET 0x02050000 34 #define PAGE_SIZE_4K_ENABLE 0x2 35 #define ACP_PAGE_SIZE 0x1000 36 #define ACP_DMA_CH_RUN 0x02 37 #define ACP_MAX_DESC_CNT 0x02 38 #define DSP_FW_RUN_ENABLE 0x01 39 #define ACP_SHA_RUN 0x01 40 #define ACP_SHA_RESET 0x02 41 #define ACP_DMA_CH_RST 0x01 42 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 43 #define ACP_ATU_CACHE_INVALID 0x01 44 #define ACP_MAX_DESC 128 45 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 46 47 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 48 #define ACP_SCRATCH_MEMORY_ADDRESS 0x02050000 49 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 50 #define ACP_IRAM_BASE_ADDRESS 0x000000 51 #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 52 #define ACP_DRAM_PAGE_COUNT 128 53 54 #define ACP_DSP_TO_HOST_IRQ 0x04 55 56 #define HOST_BRIDGE_CZN 0x1630 57 #define ACP_SHA_STAT 0x8000 58 #define ACP_PSP_TIMEOUT_COUNTER 5 59 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 60 #define MP0_C2PMSG_26_REG 0x03810570 61 #define MBOX_ACP_SHA_DMA_COMMAND 0x330000 62 #define MBOX_READY_MASK 0x80000000 63 #define MBOX_STATUS_MASK 0xFFFF 64 65 struct acp_atu_grp_pte { 66 u32 low; 67 u32 high; 68 }; 69 70 union dma_tx_cnt { 71 struct { 72 unsigned int count : 19; 73 unsigned int reserved : 12; 74 unsigned ioc : 1; 75 } bitfields, bits; 76 unsigned int u32_all; 77 signed int i32_all; 78 }; 79 80 struct dma_descriptor { 81 unsigned int src_addr; 82 unsigned int dest_addr; 83 union dma_tx_cnt tx_cnt; 84 unsigned int reserved; 85 }; 86 87 /* Scratch memory structure for communication b/w host and dsp */ 88 struct scratch_ipc_conf { 89 /* DSP mailbox */ 90 u8 sof_out_box[512]; 91 /* Host mailbox */ 92 u8 sof_in_box[512]; 93 /* Debug memory */ 94 u8 sof_debug_box[1024]; 95 /* Exception memory*/ 96 u8 sof_except_box[1024]; 97 /* Stream buffer */ 98 u8 sof_stream_box[1024]; 99 /* Trace buffer */ 100 u8 sof_trace_box[1024]; 101 /* Host msg flag */ 102 u32 sof_host_msg_write; 103 /* Host ack flag*/ 104 u32 sof_host_ack_write; 105 /* DSP msg flag */ 106 u32 sof_dsp_msg_write; 107 /* Dsp ack flag */ 108 u32 sof_dsp_ack_write; 109 }; 110 111 struct scratch_reg_conf { 112 struct scratch_ipc_conf info; 113 struct acp_atu_grp_pte grp1_pte[16]; 114 struct acp_atu_grp_pte grp2_pte[16]; 115 struct acp_atu_grp_pte grp3_pte[16]; 116 struct acp_atu_grp_pte grp4_pte[16]; 117 struct acp_atu_grp_pte grp5_pte[16]; 118 struct acp_atu_grp_pte grp6_pte[16]; 119 struct acp_atu_grp_pte grp7_pte[16]; 120 struct acp_atu_grp_pte grp8_pte[16]; 121 struct dma_descriptor dma_desc[64]; 122 unsigned int reg_offset[8]; 123 unsigned int buf_size[8]; 124 u8 acp_tx_fifo_buf[256]; 125 u8 acp_rx_fifo_buf[256]; 126 unsigned int reserve[]; 127 }; 128 129 struct acp_dsp_stream { 130 struct list_head list; 131 struct snd_sof_dev *sdev; 132 struct snd_pcm_substream *substream; 133 struct snd_dma_buffer *dmab; 134 int num_pages; 135 int stream_tag; 136 int active; 137 unsigned int reg_offset; 138 }; 139 140 /* Common device data struct for ACP devices */ 141 struct acp_dev_data { 142 struct snd_sof_dev *dev; 143 unsigned int fw_bin_size; 144 unsigned int fw_data_bin_size; 145 u32 fw_bin_page_count; 146 dma_addr_t sha_dma_addr; 147 u8 *bin_buf; 148 dma_addr_t dma_addr; 149 u8 *data_buf; 150 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 151 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 152 struct acp_dsp_stream *dtrace_stream; 153 struct pci_dev *smn_dev; 154 }; 155 156 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 157 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 158 159 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 160 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 161 unsigned int dest_addr, int dsp_data_size); 162 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 163 unsigned int start_addr, unsigned int dest_addr, 164 unsigned int image_length); 165 166 /* ACP device probe/remove */ 167 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 168 int amd_sof_acp_remove(struct snd_sof_dev *sdev); 169 170 /* DSP Loader callbacks */ 171 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 172 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 173 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 174 175 /* Block IO callbacks */ 176 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 177 u32 offset, void *src, size_t size); 178 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 179 u32 offset, void *dest, size_t size); 180 181 /* IPC callbacks */ 182 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 183 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 184 void *p, size_t sz); 185 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 186 struct snd_sof_ipc_msg *msg); 187 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 188 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 189 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 190 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 191 192 /* ACP - DSP stream callbacks */ 193 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 194 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 195 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 196 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 197 198 /* 199 * DSP PCM Operations. 200 */ 201 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 202 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 203 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 204 struct snd_pcm_hw_params *params, 205 struct snd_sof_platform_stream_params *platform_params); 206 207 extern const struct snd_sof_dsp_ops sof_renoir_ops; 208 209 /* Machine configuration */ 210 int snd_amd_acp_find_config(struct pci_dev *pci); 211 212 /* Trace */ 213 int acp_sof_trace_init(struct snd_sof_dev *sdev, 214 struct sof_ipc_dma_trace_params_ext *dtrace_params); 215 int acp_sof_trace_release(struct snd_sof_dev *sdev); 216 217 struct sof_amd_acp_desc { 218 unsigned int host_bridge_id; 219 }; 220 221 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 222 { 223 const struct sof_dev_desc *desc = pdata->desc; 224 225 return desc->chip_info; 226 } 227 #endif 228