1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include <linux/dmi.h> 15 16 #include "../sof-priv.h" 17 #include "../sof-audio.h" 18 19 #define ACP_MAX_STREAM 8 20 21 #define ACP_DSP_BAR 0 22 23 #define ACP_HW_SEM_RETRY_COUNT 10000 24 #define ACP_REG_POLL_INTERVAL 500 25 #define ACP_REG_POLL_TIMEOUT_US 2000 26 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 27 28 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 29 #define ACP_PGFSM_STATUS_MASK 0x03 30 #define ACP_POWERED_ON 0x00 31 #define ACP_ASSERT_RESET 0x01 32 #define ACP_RELEASE_RESET 0x00 33 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 34 35 #define ACP_DSP_INTR_EN_MASK 0x00000001 36 #define ACP3X_SRAM_PTE_OFFSET 0x02050000 37 #define ACP5X_SRAM_PTE_OFFSET 0x02050000 38 #define ACP6X_SRAM_PTE_OFFSET 0x03800000 39 #define PAGE_SIZE_4K_ENABLE 0x2 40 #define ACP_PAGE_SIZE 0x1000 41 #define ACP_DMA_CH_RUN 0x02 42 #define ACP_MAX_DESC_CNT 0x02 43 #define DSP_FW_RUN_ENABLE 0x01 44 #define ACP_SHA_RUN 0x01 45 #define ACP_SHA_RESET 0x02 46 #define ACP_SHA_HEADER 0x01 47 #define ACP_DMA_CH_RST 0x01 48 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 49 #define ACP_ATU_CACHE_INVALID 0x01 50 #define ACP_MAX_DESC 128 51 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 52 53 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 54 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 55 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 56 #define ACP_IRAM_BASE_ADDRESS 0x000000 57 #define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 58 #define ACP_DRAM_PAGE_COUNT 128 59 60 #define ACP_DSP_TO_HOST_IRQ 0x04 61 62 #define ACP_RN_PCI_ID 0x01 63 #define ACP_VANGOGH_PCI_ID 0x50 64 #define ACP_RMB_PCI_ID 0x6F 65 66 #define HOST_BRIDGE_CZN 0x1630 67 #define HOST_BRIDGE_VGH 0x1645 68 #define HOST_BRIDGE_RMB 0x14B5 69 #define ACP_SHA_STAT 0x8000 70 #define ACP_PSP_TIMEOUT_US 1000000 71 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 72 #define MP0_C2PMSG_114_REG 0x3810AC8 73 #define MP0_C2PMSG_73_REG 0x3810A24 74 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000 75 #define MBOX_DELAY_US 1000 76 #define MBOX_READY_MASK 0x80000000 77 #define MBOX_STATUS_MASK 0xFFFF 78 79 #define BOX_SIZE_512 0x200 80 #define BOX_SIZE_1024 0x400 81 82 #define EXCEPT_MAX_HDR_SIZE 0x400 83 #define AMD_STACK_DUMP_SIZE 32 84 85 #define SRAM1_SIZE 0x13A000 86 #define PROBE_STATUS_BIT BIT(31) 87 88 #define ACP_FIRMWARE_SIGNATURE 0x100 89 90 enum clock_source { 91 ACP_CLOCK_96M = 0, 92 ACP_CLOCK_48M, 93 ACP_CLOCK_24M, 94 ACP_CLOCK_ACLK, 95 ACP_CLOCK_MCLK, 96 }; 97 98 struct acp_atu_grp_pte { 99 u32 low; 100 u32 high; 101 }; 102 103 union dma_tx_cnt { 104 struct { 105 unsigned int count : 19; 106 unsigned int reserved : 12; 107 unsigned ioc : 1; 108 } bitfields, bits; 109 unsigned int u32_all; 110 signed int i32_all; 111 }; 112 113 struct dma_descriptor { 114 unsigned int src_addr; 115 unsigned int dest_addr; 116 union dma_tx_cnt tx_cnt; 117 unsigned int reserved; 118 }; 119 120 /* Scratch memory structure for communication b/w host and dsp */ 121 struct scratch_ipc_conf { 122 /* Debug memory */ 123 u8 sof_debug_box[1024]; 124 /* Exception memory*/ 125 u8 sof_except_box[1024]; 126 /* Stream buffer */ 127 u8 sof_stream_box[1024]; 128 /* Trace buffer */ 129 u8 sof_trace_box[1024]; 130 /* Host msg flag */ 131 u32 sof_host_msg_write; 132 /* Host ack flag*/ 133 u32 sof_host_ack_write; 134 /* DSP msg flag */ 135 u32 sof_dsp_msg_write; 136 /* Dsp ack flag */ 137 u32 sof_dsp_ack_write; 138 }; 139 140 struct scratch_reg_conf { 141 struct scratch_ipc_conf info; 142 struct acp_atu_grp_pte grp1_pte[16]; 143 struct acp_atu_grp_pte grp2_pte[16]; 144 struct acp_atu_grp_pte grp3_pte[16]; 145 struct acp_atu_grp_pte grp4_pte[16]; 146 struct acp_atu_grp_pte grp5_pte[16]; 147 struct acp_atu_grp_pte grp6_pte[16]; 148 struct acp_atu_grp_pte grp7_pte[16]; 149 struct acp_atu_grp_pte grp8_pte[16]; 150 struct dma_descriptor dma_desc[64]; 151 unsigned int reg_offset[8]; 152 unsigned int buf_size[8]; 153 u8 acp_tx_fifo_buf[256]; 154 u8 acp_rx_fifo_buf[256]; 155 unsigned int reserve[]; 156 }; 157 158 struct acp_dsp_stream { 159 struct list_head list; 160 struct snd_sof_dev *sdev; 161 struct snd_pcm_substream *substream; 162 struct snd_dma_buffer *dmab; 163 int num_pages; 164 int stream_tag; 165 int active; 166 unsigned int reg_offset; 167 size_t posn_offset; 168 struct snd_compr_stream *cstream; 169 u64 cstream_posn; 170 }; 171 172 struct sof_amd_acp_desc { 173 unsigned int rev; 174 const char *name; 175 unsigned int host_bridge_id; 176 u32 pgfsm_base; 177 u32 ext_intr_enb; 178 u32 ext_intr_stat; 179 u32 dsp_intr_base; 180 u32 sram_pte_offset; 181 u32 hw_semaphore_offset; 182 u32 acp_clkmux_sel; 183 u32 fusion_dsp_offset; 184 u32 probe_reg_offset; 185 }; 186 187 /* Common device data struct for ACP devices */ 188 struct acp_dev_data { 189 struct snd_sof_dev *dev; 190 const struct firmware *fw_dbin; 191 /* DMIC device */ 192 struct platform_device *dmic_dev; 193 unsigned int fw_bin_size; 194 unsigned int fw_data_bin_size; 195 const char *fw_code_bin; 196 const char *fw_data_bin; 197 u32 fw_bin_page_count; 198 dma_addr_t sha_dma_addr; 199 u8 *bin_buf; 200 dma_addr_t dma_addr; 201 u8 *data_buf; 202 bool signed_fw_image; 203 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 204 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 205 struct acp_dsp_stream *dtrace_stream; 206 struct pci_dev *smn_dev; 207 struct acp_dsp_stream *probe_stream; 208 bool enable_fw_debug; 209 }; 210 211 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 212 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 213 214 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 215 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 216 unsigned int dest_addr, int dsp_data_size); 217 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 218 unsigned int start_addr, unsigned int dest_addr, 219 unsigned int image_length); 220 221 /* ACP device probe/remove */ 222 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 223 int amd_sof_acp_remove(struct snd_sof_dev *sdev); 224 225 /* DSP Loader callbacks */ 226 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 227 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 228 int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev); 229 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 230 231 /* Block IO callbacks */ 232 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 233 u32 offset, void *src, size_t size); 234 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 235 u32 offset, void *dest, size_t size); 236 237 /* IPC callbacks */ 238 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 239 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, 240 void *p, size_t sz); 241 int acp_set_stream_data_offset(struct snd_sof_dev *sdev, 242 struct snd_sof_pcm_stream *sps, 243 size_t posn_offset); 244 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 245 struct snd_sof_ipc_msg *msg); 246 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 247 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 248 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 249 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 250 251 /* ACP - DSP stream callbacks */ 252 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 253 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 254 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 255 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 256 257 /* 258 * DSP PCM Operations. 259 */ 260 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 261 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 262 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 263 struct snd_pcm_hw_params *params, 264 struct snd_sof_platform_stream_params *platform_params); 265 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev, 266 struct snd_pcm_substream *substream); 267 268 extern struct snd_sof_dsp_ops sof_acp_common_ops; 269 270 extern struct snd_sof_dsp_ops sof_renoir_ops; 271 int sof_renoir_ops_init(struct snd_sof_dev *sdev); 272 extern struct snd_sof_dsp_ops sof_vangogh_ops; 273 int sof_vangogh_ops_init(struct snd_sof_dev *sdev); 274 extern struct snd_sof_dsp_ops sof_rembrandt_ops; 275 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 276 277 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 278 /* Machine configuration */ 279 int snd_amd_acp_find_config(struct pci_dev *pci); 280 281 /* Trace */ 282 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 283 struct sof_ipc_dma_trace_params_ext *dtrace_params); 284 int acp_sof_trace_release(struct snd_sof_dev *sdev); 285 286 /* PM Callbacks */ 287 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state); 288 int amd_sof_acp_resume(struct snd_sof_dev *sdev); 289 290 void amd_sof_ipc_dump(struct snd_sof_dev *sdev); 291 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags); 292 293 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 294 { 295 const struct sof_dev_desc *desc = pdata->desc; 296 297 return desc->chip_info; 298 } 299 300 int acp_probes_register(struct snd_sof_dev *sdev); 301 void acp_probes_unregister(struct snd_sof_dev *sdev); 302 303 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[]; 304 extern const struct dmi_system_id acp_sof_quirk_table[]; 305 #endif 306