1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com> 9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 10 11 /* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 19 #include "../ops.h" 20 #include "acp.h" 21 #include "acp-dsp-offset.h" 22 23 #define SECURED_FIRMWARE 1 24 25 static bool enable_fw_debug; 26 module_param(enable_fw_debug, bool, 0444); 27 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug"); 28 29 const struct dmi_system_id acp_sof_quirk_table[] = { 30 { 31 /* Steam Deck OLED device */ 32 .matches = { 33 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 34 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 35 }, 36 .driver_data = (void *)SECURED_FIRMWARE, 37 }, 38 {} 39 }; 40 EXPORT_SYMBOL_GPL(acp_sof_quirk_table); 41 42 static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data) 43 { 44 pci_write_config_dword(dev, 0x60, smn_addr); 45 pci_write_config_dword(dev, 0x64, data); 46 47 return 0; 48 } 49 50 static int smn_read(struct pci_dev *dev, u32 smn_addr) 51 { 52 u32 data = 0; 53 54 pci_write_config_dword(dev, 0x60, smn_addr); 55 pci_read_config_dword(dev, 0x64, &data); 56 57 return data; 58 } 59 60 static void init_dma_descriptor(struct acp_dev_data *adata) 61 { 62 struct snd_sof_dev *sdev = adata->dev; 63 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 64 unsigned int addr; 65 66 addr = desc->sram_pte_offset + sdev->debug_box.offset + 67 offsetof(struct scratch_reg_conf, dma_desc); 68 69 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr); 70 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT); 71 } 72 73 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 74 struct dma_descriptor *dscr_info) 75 { 76 struct snd_sof_dev *sdev = adata->dev; 77 unsigned int offset; 78 79 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset + 80 offsetof(struct scratch_reg_conf, dma_desc) + 81 idx * sizeof(struct dma_descriptor); 82 83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 85 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 86 } 87 88 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 89 unsigned int idx, unsigned int dscr_count) 90 { 91 struct snd_sof_dev *sdev = adata->dev; 92 unsigned int val, status; 93 int ret; 94 95 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), 96 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 97 98 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val, 99 val & (1 << ch), ACP_REG_POLL_INTERVAL, 100 ACP_REG_POLL_TIMEOUT_US); 101 if (ret < 0) { 102 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS); 103 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32)); 104 105 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 106 return ret; 107 } 108 109 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0); 110 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count); 111 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx); 112 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0); 113 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 114 115 return ret; 116 } 117 118 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 119 unsigned int dscr_count, struct dma_descriptor *dscr_info) 120 { 121 struct snd_sof_dev *sdev = adata->dev; 122 int ret; 123 u16 dscr; 124 125 if (!dscr_info || !dscr_count) 126 return -EINVAL; 127 128 for (dscr = 0; dscr < dscr_count; dscr++) 129 configure_dma_descriptor(adata, dscr, dscr_info++); 130 131 ret = config_dma_channel(adata, ch, 0, dscr_count); 132 if (ret < 0) 133 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 134 135 return ret; 136 } 137 138 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 139 unsigned int dest_addr, int dsp_data_size) 140 { 141 struct snd_sof_dev *sdev = adata->dev; 142 unsigned int desc_count, index; 143 int ret; 144 145 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 146 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 147 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 148 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 149 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 150 if (dsp_data_size < ACP_PAGE_SIZE) 151 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 152 } 153 154 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 155 if (ret) 156 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 157 158 /* Clear descriptor array */ 159 for (index = 0; index < desc_count; index++) 160 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 161 162 return ret; 163 } 164 165 /* 166 * psp_mbox_ready- function to poll ready bit of psp mbox 167 * @adata: acp device data 168 * @ack: bool variable to check ready bit status or psp ack 169 */ 170 171 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack) 172 { 173 struct snd_sof_dev *sdev = adata->dev; 174 int ret; 175 u32 data; 176 177 ret = read_poll_timeout(smn_read, data, data & MBOX_READY_MASK, MBOX_DELAY_US, 178 ACP_PSP_TIMEOUT_US, false, adata->smn_dev, MP0_C2PMSG_114_REG); 179 if (!ret) 180 return 0; 181 182 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK); 183 184 if (ack) 185 return -ETIMEDOUT; 186 187 return -EBUSY; 188 } 189 190 /* 191 * psp_send_cmd - function to send psp command over mbox 192 * @adata: acp device data 193 * @cmd: non zero integer value for command type 194 */ 195 196 static int psp_send_cmd(struct acp_dev_data *adata, int cmd) 197 { 198 struct snd_sof_dev *sdev = adata->dev; 199 int ret; 200 u32 data; 201 202 if (!cmd) 203 return -EINVAL; 204 205 /* Get a non-zero Doorbell value from PSP */ 206 ret = read_poll_timeout(smn_read, data, data, MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, 207 adata->smn_dev, MP0_C2PMSG_73_REG); 208 209 if (ret) { 210 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG); 211 return ret; 212 } 213 214 /* Check if PSP is ready for new command */ 215 ret = psp_mbox_ready(adata, 0); 216 if (ret) 217 return ret; 218 219 smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd); 220 221 /* Ring the Doorbell for PSP */ 222 smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data); 223 224 /* Check MBOX ready as PSP ack */ 225 ret = psp_mbox_ready(adata, 1); 226 227 return ret; 228 } 229 230 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 231 unsigned int start_addr, unsigned int dest_addr, 232 unsigned int image_length) 233 { 234 struct snd_sof_dev *sdev = adata->dev; 235 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 236 unsigned int tx_count, fw_qualifier, val; 237 int ret; 238 239 if (!image_addr) { 240 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 241 return -EINVAL; 242 } 243 244 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 245 if (val & ACP_SHA_RUN) { 246 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 247 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 248 val, val & ACP_SHA_RESET, 249 ACP_REG_POLL_INTERVAL, 250 ACP_REG_POLL_TIMEOUT_US); 251 if (ret < 0) { 252 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 253 return ret; 254 } 255 } 256 257 if (adata->signed_fw_image) 258 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); 259 260 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 261 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 262 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 263 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 264 265 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 266 tx_count, tx_count == image_length, 267 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 268 if (ret < 0) { 269 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 270 return ret; 271 } 272 273 /* psp_send_cmd only required for renoir platform (rev - 3) */ 274 if (desc->rev == 3) { 275 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 276 if (ret) 277 return ret; 278 } 279 280 /* psp_send_cmd only required for vangogh platform (rev - 5) */ 281 if (desc->rev == 5) { 282 /* Modify IRAM and DRAM size */ 283 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); 284 if (ret) 285 return ret; 286 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); 287 if (ret) 288 return ret; 289 } 290 291 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 292 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, 293 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 294 if (ret < 0) { 295 dev_err(sdev->dev, "PSP validation failed\n"); 296 return ret; 297 } 298 299 return 0; 300 } 301 302 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 303 { 304 struct snd_sof_dev *sdev = adata->dev; 305 unsigned int val; 306 int ret = 0; 307 308 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 309 if (val & ACP_DMA_CH_RUN) { 310 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val, 311 ACP_REG_POLL_INTERVAL, 312 ACP_DMA_COMPLETE_TIMEOUT_US); 313 if (ret < 0) 314 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 315 } 316 317 return ret; 318 } 319 320 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 321 { 322 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 323 int i, j; 324 325 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 326 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 327 } 328 329 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 330 { 331 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 332 int i, j; 333 334 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 335 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 336 } 337 338 static int acp_memory_init(struct snd_sof_dev *sdev) 339 { 340 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 341 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 342 343 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET, 344 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 345 init_dma_descriptor(adata); 346 347 return 0; 348 } 349 350 static irqreturn_t acp_irq_thread(int irq, void *context) 351 { 352 struct snd_sof_dev *sdev = context; 353 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 354 unsigned int count = ACP_HW_SEM_RETRY_COUNT; 355 356 spin_lock_irq(&sdev->ipc_lock); 357 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) { 358 /* Wait until acquired HW Semaphore lock or timeout */ 359 count--; 360 if (!count) { 361 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 362 spin_unlock_irq(&sdev->ipc_lock); 363 return IRQ_NONE; 364 } 365 } 366 367 sof_ops(sdev)->irq_thread(irq, sdev); 368 /* Unlock or Release HW Semaphore */ 369 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); 370 371 spin_unlock_irq(&sdev->ipc_lock); 372 return IRQ_HANDLED; 373 }; 374 375 static irqreturn_t acp_irq_handler(int irq, void *dev_id) 376 { 377 struct amd_sdw_manager *amd_manager; 378 struct snd_sof_dev *sdev = dev_id; 379 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 380 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 381 unsigned int base = desc->dsp_intr_base; 382 unsigned int val; 383 int irq_flag = 0; 384 385 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 386 if (val & ACP_DSP_TO_HOST_IRQ) { 387 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 388 ACP_DSP_TO_HOST_IRQ); 389 return IRQ_WAKE_THREAD; 390 } 391 392 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 393 if (val & ACP_SDW0_IRQ_MASK) { 394 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 395 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); 396 if (amd_manager) 397 schedule_work(&amd_manager->amd_sdw_irq_thread); 398 irq_flag = 1; 399 } 400 401 if (val & ACP_ERROR_IRQ_MASK) { 402 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 403 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW0_I2S_ERROR_REASON, 0); 404 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW1_I2S_ERROR_REASON, 0); 405 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_ERROR_STATUS, 0); 406 irq_flag = 1; 407 } 408 409 if (desc->ext_intr_stat1) { 410 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 411 if (val & ACP_SDW1_IRQ_MASK) { 412 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 413 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 414 ACP_SDW1_IRQ_MASK); 415 if (amd_manager) 416 schedule_work(&amd_manager->amd_sdw_irq_thread); 417 irq_flag = 1; 418 } 419 } 420 if (irq_flag) 421 return IRQ_HANDLED; 422 else 423 return IRQ_NONE; 424 } 425 426 static int acp_power_on(struct snd_sof_dev *sdev) 427 { 428 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 429 unsigned int base = desc->pgfsm_base; 430 unsigned int val; 431 int ret; 432 433 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); 434 435 if (val == ACP_POWERED_ON) 436 return 0; 437 438 if (val & ACP_PGFSM_STATUS_MASK) 439 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, 440 ACP_PGFSM_CNTL_POWER_ON_MASK); 441 442 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val, 443 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 444 if (ret < 0) 445 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 446 447 return ret; 448 } 449 450 static int acp_reset(struct snd_sof_dev *sdev) 451 { 452 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 453 unsigned int val; 454 int ret; 455 456 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 457 458 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 459 val & ACP_SOFT_RESET_DONE_MASK, 460 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 461 if (ret < 0) { 462 dev_err(sdev->dev, "timeout asserting reset\n"); 463 return ret; 464 } 465 466 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 467 468 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 469 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 470 if (ret < 0) 471 dev_err(sdev->dev, "timeout in releasing reset\n"); 472 473 if (desc->acp_clkmux_sel) 474 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); 475 476 if (desc->ext_intr_enb) 477 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); 478 479 if (desc->ext_intr_cntl) 480 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); 481 return ret; 482 } 483 484 static int acp_dsp_reset(struct snd_sof_dev *sdev) 485 { 486 unsigned int val; 487 int ret; 488 489 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); 490 491 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 492 val & ACP_DSP_SOFT_RESET_DONE_MASK, 493 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 494 if (ret < 0) { 495 dev_err(sdev->dev, "timeout asserting reset\n"); 496 return ret; 497 } 498 499 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); 500 501 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 502 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 503 if (ret < 0) 504 dev_err(sdev->dev, "timeout in releasing reset\n"); 505 506 return ret; 507 } 508 509 static int acp_init(struct snd_sof_dev *sdev) 510 { 511 int ret; 512 513 /* power on */ 514 ret = acp_power_on(sdev); 515 if (ret) { 516 dev_err(sdev->dev, "ACP power on failed\n"); 517 return ret; 518 } 519 520 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); 521 /* Reset */ 522 return acp_reset(sdev); 523 } 524 525 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 526 { 527 struct acp_dev_data *acp_data; 528 u32 sdw0_en, sdw1_en; 529 530 acp_data = sdev->pdata->hw_pdata; 531 if (!acp_data->sdw) 532 return false; 533 534 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN); 535 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN); 536 acp_data->sdw_en_stat = sdw0_en || sdw1_en; 537 return acp_data->sdw_en_stat; 538 } 539 540 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 541 { 542 int ret; 543 544 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and 545 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will 546 * be reset to default values which will break the ClockStop Mode functionality. 547 * Add a condition check to apply DSP reset when SoundWire ClockStop mode 548 * is selected. For the rest of the scenarios, apply acp reset sequence. 549 */ 550 if (check_acp_sdw_enable_status(sdev)) 551 return acp_dsp_reset(sdev); 552 553 ret = acp_reset(sdev); 554 if (ret) { 555 dev_err(sdev->dev, "ACP Reset failed\n"); 556 return ret; 557 } 558 559 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00); 560 561 return 0; 562 } 563 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON); 564 565 int amd_sof_acp_resume(struct snd_sof_dev *sdev) 566 { 567 int ret; 568 struct acp_dev_data *acp_data; 569 570 acp_data = sdev->pdata->hw_pdata; 571 if (!acp_data->sdw_en_stat) { 572 ret = acp_init(sdev); 573 if (ret) { 574 dev_err(sdev->dev, "ACP Init failed\n"); 575 return ret; 576 } 577 return acp_memory_init(sdev); 578 } else { 579 return acp_dsp_reset(sdev); 580 } 581 } 582 EXPORT_SYMBOL_NS(amd_sof_acp_resume, SND_SOC_SOF_AMD_COMMON); 583 584 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE) 585 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 586 { 587 struct acpi_device *sdw_dev; 588 struct acp_dev_data *acp_data; 589 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 590 591 if (!addr) 592 return -ENODEV; 593 594 acp_data = sdev->pdata->hw_pdata; 595 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0); 596 if (!sdw_dev) 597 return -ENODEV; 598 599 acp_data->info.handle = sdw_dev->handle; 600 acp_data->info.count = desc->sdw_max_link_count; 601 602 return amd_sdw_scan_controller(&acp_data->info); 603 } 604 605 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 606 { 607 struct acp_dev_data *acp_data; 608 struct sdw_amd_res sdw_res; 609 int ret; 610 611 acp_data = sdev->pdata->hw_pdata; 612 613 memset(&sdw_res, 0, sizeof(sdw_res)); 614 sdw_res.addr = acp_data->addr; 615 sdw_res.reg_range = acp_data->reg_range; 616 sdw_res.handle = acp_data->info.handle; 617 sdw_res.parent = sdev->dev; 618 sdw_res.dev = sdev->dev; 619 sdw_res.acp_lock = &acp_data->acp_lock; 620 sdw_res.count = acp_data->info.count; 621 sdw_res.link_mask = acp_data->info.link_mask; 622 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR]; 623 624 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); 625 if (ret) 626 dev_err(sdev->dev, "SoundWire probe failed\n"); 627 return ret; 628 } 629 630 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 631 { 632 struct acp_dev_data *acp_data; 633 634 acp_data = sdev->pdata->hw_pdata; 635 if (acp_data->sdw) 636 sdw_amd_exit(acp_data->sdw); 637 acp_data->sdw = NULL; 638 639 return 0; 640 } 641 642 #else 643 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 644 { 645 return 0; 646 } 647 648 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 649 { 650 return 0; 651 } 652 653 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 654 { 655 return 0; 656 } 657 #endif 658 659 int amd_sof_acp_probe(struct snd_sof_dev *sdev) 660 { 661 struct pci_dev *pci = to_pci_dev(sdev->dev); 662 struct acp_dev_data *adata; 663 const struct sof_amd_acp_desc *chip; 664 const struct dmi_system_id *dmi_id; 665 unsigned int addr; 666 int ret; 667 668 chip = get_chip_info(sdev->pdata); 669 if (!chip) { 670 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 671 return -EIO; 672 } 673 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 674 GFP_KERNEL); 675 if (!adata) 676 return -ENOMEM; 677 678 adata->dev = sdev; 679 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 680 PLATFORM_DEVID_NONE, NULL, 0); 681 if (IS_ERR(adata->dmic_dev)) { 682 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 683 return PTR_ERR(adata->dmic_dev); 684 } 685 addr = pci_resource_start(pci, ACP_DSP_BAR); 686 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 687 if (!sdev->bar[ACP_DSP_BAR]) { 688 dev_err(sdev->dev, "ioremap error\n"); 689 ret = -ENXIO; 690 goto unregister_dev; 691 } 692 693 pci_set_master(pci); 694 adata->addr = addr; 695 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 696 mutex_init(&adata->acp_lock); 697 sdev->pdata->hw_pdata = adata; 698 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL); 699 if (!adata->smn_dev) { 700 dev_err(sdev->dev, "Failed to get host bridge device\n"); 701 ret = -ENODEV; 702 goto unregister_dev; 703 } 704 705 sdev->ipc_irq = pci->irq; 706 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 707 IRQF_SHARED, "AudioDSP", sdev); 708 if (ret < 0) { 709 dev_err(sdev->dev, "failed to register IRQ %d\n", 710 sdev->ipc_irq); 711 goto free_smn_dev; 712 } 713 714 ret = acp_init(sdev); 715 if (ret < 0) 716 goto free_ipc_irq; 717 718 /* scan SoundWire capabilities exposed by DSDT */ 719 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr); 720 if (ret < 0) { 721 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 722 goto skip_soundwire; 723 } 724 ret = amd_sof_sdw_probe(sdev); 725 if (ret < 0) { 726 dev_err(sdev->dev, "error: SoundWire probe error\n"); 727 free_irq(sdev->ipc_irq, sdev); 728 pci_dev_put(adata->smn_dev); 729 return ret; 730 } 731 732 skip_soundwire: 733 sdev->dsp_box.offset = 0; 734 sdev->dsp_box.size = BOX_SIZE_512; 735 736 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 737 sdev->host_box.size = BOX_SIZE_512; 738 739 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 740 sdev->debug_box.size = BOX_SIZE_1024; 741 742 adata->signed_fw_image = false; 743 dmi_id = dmi_first_match(acp_sof_quirk_table); 744 if (dmi_id && dmi_id->driver_data) { 745 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 746 "sof-%s-code.bin", 747 chip->name); 748 if (!adata->fw_code_bin) { 749 ret = -ENOMEM; 750 goto free_ipc_irq; 751 } 752 753 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 754 "sof-%s-data.bin", 755 chip->name); 756 if (!adata->fw_data_bin) { 757 ret = -ENOMEM; 758 goto free_ipc_irq; 759 } 760 761 adata->signed_fw_image = dmi_id->driver_data; 762 } 763 764 adata->enable_fw_debug = enable_fw_debug; 765 acp_memory_init(sdev); 766 767 acp_dsp_stream_init(sdev); 768 769 return 0; 770 771 free_ipc_irq: 772 free_irq(sdev->ipc_irq, sdev); 773 free_smn_dev: 774 pci_dev_put(adata->smn_dev); 775 unregister_dev: 776 platform_device_unregister(adata->dmic_dev); 777 return ret; 778 } 779 EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON); 780 781 void amd_sof_acp_remove(struct snd_sof_dev *sdev) 782 { 783 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 784 785 if (adata->smn_dev) 786 pci_dev_put(adata->smn_dev); 787 788 if (adata->sdw) 789 amd_sof_sdw_exit(sdev); 790 791 if (sdev->ipc_irq) 792 free_irq(sdev->ipc_irq, sdev); 793 794 if (adata->dmic_dev) 795 platform_device_unregister(adata->dmic_dev); 796 797 acp_reset(sdev); 798 } 799 EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON); 800 801 MODULE_DESCRIPTION("AMD ACP sof driver"); 802 MODULE_IMPORT_NS(SOUNDWIRE_AMD_INIT); 803 MODULE_IMPORT_NS(SND_AMD_SOUNDWIRE_ACPI); 804 MODULE_LICENSE("Dual BSD/GPL"); 805