1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com> 9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 10 11 /* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15 #include <linux/acpi.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 20 #include <asm/amd/node.h> 21 22 #include "../ops.h" 23 #include "acp.h" 24 #include "acp-dsp-offset.h" 25 26 static bool enable_fw_debug; 27 module_param(enable_fw_debug, bool, 0444); 28 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug"); 29 30 static struct acp_quirk_entry quirk_valve_galileo = { 31 .signed_fw_image = true, 32 .skip_iram_dram_size_mod = true, 33 .post_fw_run_delay = true, 34 }; 35 36 const struct dmi_system_id acp_sof_quirk_table[] = { 37 { 38 /* Steam Deck OLED device */ 39 .matches = { 40 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 41 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 42 }, 43 .driver_data = &quirk_valve_galileo, 44 }, 45 {} 46 }; 47 EXPORT_SYMBOL_GPL(acp_sof_quirk_table); 48 49 static void init_dma_descriptor(struct acp_dev_data *adata) 50 { 51 struct snd_sof_dev *sdev = adata->dev; 52 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 53 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 54 unsigned int addr; 55 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr; 56 57 addr = desc->sram_pte_offset + sdev->debug_box.offset + 58 offsetof(struct scratch_reg_conf, dma_desc); 59 60 switch (acp_data->pci_rev) { 61 case ACP70_PCI_ID: 62 case ACP71_PCI_ID: 63 case ACP72_PCI_ID: 64 case ACP7B_PCI_ID: 65 case ACP7F_PCI_ID: 66 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR; 67 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR; 68 break; 69 default: 70 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR; 71 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR; 72 } 73 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr); 74 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT); 75 } 76 77 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 78 struct dma_descriptor *dscr_info) 79 { 80 struct snd_sof_dev *sdev = adata->dev; 81 unsigned int offset; 82 83 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset + 84 offsetof(struct scratch_reg_conf, dma_desc) + 85 idx * sizeof(struct dma_descriptor); 86 87 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 88 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 89 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 90 } 91 92 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 93 unsigned int idx, unsigned int dscr_count) 94 { 95 struct snd_sof_dev *sdev = adata->dev; 96 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 97 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 98 unsigned int val, status; 99 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0; 100 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0; 101 int ret; 102 103 switch (acp_data->pci_rev) { 104 case ACP70_PCI_ID: 105 case ACP71_PCI_ID: 106 case ACP72_PCI_ID: 107 case ACP7B_PCI_ID: 108 case ACP7F_PCI_ID: 109 acp_dma_cntl_0 = ACP70_DMA_CNTL_0; 110 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS; 111 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0; 112 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0; 113 acp_dma_prio_0 = ACP70_DMA_PRIO_0; 114 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0; 115 break; 116 default: 117 acp_dma_cntl_0 = ACP_DMA_CNTL_0; 118 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS; 119 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0; 120 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0; 121 acp_dma_prio_0 = ACP_DMA_PRIO_0; 122 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0; 123 } 124 125 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), 126 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 127 128 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val, 129 val & (1 << ch), ACP_REG_POLL_INTERVAL, 130 ACP_REG_POLL_TIMEOUT_US); 131 if (ret < 0) { 132 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat); 133 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 + 134 ch * sizeof(u32)); 135 136 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 137 return ret; 138 } 139 140 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0); 141 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count); 142 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx); 143 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0); 144 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 145 146 return ret; 147 } 148 149 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 150 unsigned int dscr_count, struct dma_descriptor *dscr_info) 151 { 152 struct snd_sof_dev *sdev = adata->dev; 153 int ret; 154 u16 dscr; 155 156 if (!dscr_info || !dscr_count) 157 return -EINVAL; 158 159 for (dscr = 0; dscr < dscr_count; dscr++) 160 configure_dma_descriptor(adata, dscr, dscr_info++); 161 162 ret = config_dma_channel(adata, ch, 0, dscr_count); 163 if (ret < 0) 164 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 165 166 return ret; 167 } 168 169 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 170 unsigned int dest_addr, int dsp_data_size) 171 { 172 struct snd_sof_dev *sdev = adata->dev; 173 unsigned int desc_count, index; 174 int ret; 175 176 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 177 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 178 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 179 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 180 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 181 if (dsp_data_size < ACP_PAGE_SIZE) 182 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 183 } 184 185 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 186 if (ret) 187 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 188 189 /* Clear descriptor array */ 190 for (index = 0; index < desc_count; index++) 191 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 192 193 return ret; 194 } 195 196 /* 197 * psp_mbox_ready- function to poll ready bit of psp mbox 198 * @adata: acp device data 199 * @ack: bool variable to check ready bit status or psp ack 200 */ 201 202 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack) 203 { 204 struct snd_sof_dev *sdev = adata->dev; 205 int ret, data; 206 207 ret = read_poll_timeout(smn_read_register, data, data > 0 && data & MBOX_READY_MASK, 208 MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_114_REG); 209 210 if (!ret) 211 return 0; 212 213 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK); 214 215 if (ack) 216 return -ETIMEDOUT; 217 218 return -EBUSY; 219 } 220 221 /* 222 * psp_send_cmd - function to send psp command over mbox 223 * @adata: acp device data 224 * @cmd: non zero integer value for command type 225 */ 226 227 static int psp_send_cmd(struct acp_dev_data *adata, int cmd) 228 { 229 struct snd_sof_dev *sdev = adata->dev; 230 int ret; 231 int data; 232 233 if (!cmd) 234 return -EINVAL; 235 236 /* Get a non-zero Doorbell value from PSP */ 237 ret = read_poll_timeout(smn_read_register, data, data > 0, MBOX_DELAY_US, 238 ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_73_REG); 239 240 if (ret) { 241 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG); 242 return ret; 243 } 244 245 /* Check if PSP is ready for new command */ 246 ret = psp_mbox_ready(adata, 0); 247 if (ret) 248 return ret; 249 250 ret = amd_smn_write(0, MP0_C2PMSG_114_REG, cmd); 251 if (ret) 252 return ret; 253 254 /* Ring the Doorbell for PSP */ 255 ret = amd_smn_write(0, MP0_C2PMSG_73_REG, data); 256 if (ret) 257 return ret; 258 259 /* Check MBOX ready as PSP ack */ 260 ret = psp_mbox_ready(adata, 1); 261 262 return ret; 263 } 264 265 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 266 unsigned int start_addr, unsigned int dest_addr, 267 unsigned int image_length) 268 { 269 struct snd_sof_dev *sdev = adata->dev; 270 unsigned int tx_count, fw_qualifier, val; 271 int ret; 272 273 if (!image_addr) { 274 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 275 return -EINVAL; 276 } 277 278 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 279 if (val & ACP_SHA_RUN) { 280 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 281 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 282 val, val & ACP_SHA_RESET, 283 ACP_REG_POLL_INTERVAL, 284 ACP_REG_POLL_TIMEOUT_US); 285 if (ret < 0) { 286 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 287 return ret; 288 } 289 } 290 291 if (adata->quirks && adata->quirks->signed_fw_image) 292 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); 293 294 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 295 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 296 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 297 298 /* psp_send_cmd only required for vangogh platform */ 299 if (adata->pci_rev == ACP_VANGOGH_PCI_ID && 300 !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { 301 /* Modify IRAM and DRAM size */ 302 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); 303 if (ret) 304 return ret; 305 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); 306 if (ret) 307 return ret; 308 } 309 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 310 311 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 312 tx_count, tx_count == image_length, 313 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 314 if (ret < 0) { 315 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 316 return ret; 317 } 318 319 /* psp_send_cmd only required for renoir platform*/ 320 if (adata->pci_rev == ACP_RN_PCI_ID) { 321 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 322 if (ret) 323 return ret; 324 } 325 326 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 327 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, 328 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 329 if (ret < 0) { 330 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_PSP_ACK); 331 dev_err(sdev->dev, "PSP validation failed: fw_qualifier = %#x, ACP_SHA_PSP_ACK = %#x\n", 332 fw_qualifier, val); 333 return ret; 334 } 335 336 return 0; 337 } 338 339 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 340 { 341 struct snd_sof_dev *sdev = adata->dev; 342 unsigned int val; 343 unsigned int acp_dma_ch_sts; 344 int ret = 0; 345 346 switch (adata->pci_rev) { 347 case ACP70_PCI_ID: 348 case ACP71_PCI_ID: 349 case ACP72_PCI_ID: 350 case ACP7B_PCI_ID: 351 case ACP7F_PCI_ID: 352 acp_dma_ch_sts = ACP70_DMA_CH_STS; 353 break; 354 default: 355 acp_dma_ch_sts = ACP_DMA_CH_STS; 356 } 357 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 358 if (val & ACP_DMA_CH_RUN) { 359 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_sts, val, !val, 360 ACP_REG_POLL_INTERVAL, 361 ACP_DMA_COMPLETE_TIMEOUT_US); 362 if (ret < 0) 363 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 364 } 365 366 return ret; 367 } 368 369 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 370 { 371 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 372 int i, j; 373 374 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 375 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 376 } 377 378 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 379 { 380 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 381 int i, j; 382 383 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 384 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 385 } 386 387 static int acp_init_scratch_mem_ipc_flags(struct snd_sof_dev *sdev) 388 { 389 u32 dsp_msg_write, dsp_ack_write, host_msg_write, host_ack_write; 390 391 dsp_msg_write = sdev->debug_box.offset + 392 offsetof(struct scratch_ipc_conf, sof_dsp_msg_write); 393 dsp_ack_write = sdev->debug_box.offset + 394 offsetof(struct scratch_ipc_conf, sof_dsp_ack_write); 395 host_msg_write = sdev->debug_box.offset + 396 offsetof(struct scratch_ipc_conf, sof_host_msg_write); 397 host_ack_write = sdev->debug_box.offset + 398 offsetof(struct scratch_ipc_conf, sof_host_ack_write); 399 /* Initialize host message write flag */ 400 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg_write, 0); 401 402 /* Initialize host ack write flag */ 403 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_ack_write, 0); 404 405 /* Initialize DSP message write flag */ 406 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write, 0); 407 408 /* Initialize DSP ack write flag */ 409 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write, 0); 410 411 return 0; 412 } 413 414 static int acp_memory_init(struct snd_sof_dev *sdev) 415 { 416 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 417 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 418 419 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET, 420 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 421 acp_init_scratch_mem_ipc_flags(sdev); 422 init_dma_descriptor(adata); 423 424 return 0; 425 } 426 427 static void amd_sof_handle_acp70_sdw_wake_event(struct acp_dev_data *adata) 428 { 429 struct amd_sdw_manager *amd_manager; 430 431 if (adata->acp70_sdw0_wake_event) { 432 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 433 if (amd_manager) 434 pm_request_resume(amd_manager->dev); 435 adata->acp70_sdw0_wake_event = 0; 436 } 437 438 if (adata->acp70_sdw1_wake_event) { 439 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 440 if (amd_manager) 441 pm_request_resume(amd_manager->dev); 442 adata->acp70_sdw1_wake_event = 0; 443 } 444 } 445 446 static int amd_sof_check_and_handle_acp70_sdw_wake_irq(struct snd_sof_dev *sdev) 447 { 448 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 449 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 450 u32 ext_intr_stat1; 451 int irq_flag = 0; 452 bool sdw_wake_irq = false; 453 454 ext_intr_stat1 = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 455 if (ext_intr_stat1 & ACP70_SDW0_HOST_WAKE_STAT) { 456 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 457 ACP70_SDW0_HOST_WAKE_STAT); 458 adata->acp70_sdw0_wake_event = true; 459 sdw_wake_irq = true; 460 } 461 462 if (ext_intr_stat1 & ACP70_SDW1_HOST_WAKE_STAT) { 463 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 464 ACP70_SDW1_HOST_WAKE_STAT); 465 adata->acp70_sdw1_wake_event = true; 466 sdw_wake_irq = true; 467 } 468 469 if (ext_intr_stat1 & ACP70_SDW0_PME_STAT) { 470 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN, 0); 471 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW0_PME_STAT); 472 adata->acp70_sdw0_wake_event = true; 473 sdw_wake_irq = true; 474 } 475 476 if (ext_intr_stat1 & ACP70_SDW1_PME_STAT) { 477 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN, 0); 478 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW1_PME_STAT); 479 adata->acp70_sdw1_wake_event = true; 480 sdw_wake_irq = true; 481 } 482 483 if (sdw_wake_irq) { 484 amd_sof_handle_acp70_sdw_wake_event(adata); 485 irq_flag = 1; 486 } 487 return irq_flag; 488 } 489 490 static irqreturn_t acp_irq_thread(int irq, void *context) 491 { 492 struct snd_sof_dev *sdev = context; 493 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 494 unsigned int count = ACP_HW_SEM_RETRY_COUNT; 495 496 spin_lock_irq(&sdev->ipc_lock); 497 /* Wait until acquired HW Semaphore lock or timeout */ 498 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count) 499 ; 500 spin_unlock_irq(&sdev->ipc_lock); 501 502 if (!count) { 503 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 504 return IRQ_NONE; 505 } 506 507 sof_ops(sdev)->irq_thread(irq, sdev); 508 /* Unlock or Release HW Semaphore */ 509 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); 510 511 return IRQ_HANDLED; 512 }; 513 514 static irqreturn_t acp_irq_handler(int irq, void *dev_id) 515 { 516 struct amd_sdw_manager *amd_manager; 517 struct snd_sof_dev *sdev = dev_id; 518 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 519 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 520 unsigned int base = desc->dsp_intr_base; 521 unsigned int val; 522 int irq_flag = 0, wake_irq_flag = 0; 523 524 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 525 if (val & ACP_DSP_TO_HOST_IRQ) { 526 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 527 ACP_DSP_TO_HOST_IRQ); 528 return IRQ_WAKE_THREAD; 529 } 530 531 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 532 if (val & ACP_SDW0_IRQ_MASK) { 533 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 534 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); 535 if (amd_manager) 536 schedule_work(&amd_manager->amd_sdw_irq_thread); 537 irq_flag = 1; 538 } 539 540 if (val & ACP_ERROR_IRQ_MASK) { 541 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 542 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); 543 /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */ 544 switch (adata->pci_rev) { 545 case ACP_RMB_PCI_ID: 546 case ACP63_PCI_ID: 547 case ACP70_PCI_ID: 548 case ACP71_PCI_ID: 549 case ACP72_PCI_ID: 550 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); 551 break; 552 default: 553 break; 554 } 555 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 556 irq_flag = 1; 557 } 558 559 if (desc->ext_intr_stat1) { 560 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 561 if (val & ACP_SDW1_IRQ_MASK) { 562 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 563 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 564 ACP_SDW1_IRQ_MASK); 565 if (amd_manager) 566 schedule_work(&amd_manager->amd_sdw_irq_thread); 567 irq_flag = 1; 568 } 569 switch (adata->pci_rev) { 570 case ACP70_PCI_ID: 571 case ACP71_PCI_ID: 572 case ACP72_PCI_ID: 573 wake_irq_flag = amd_sof_check_and_handle_acp70_sdw_wake_irq(sdev); 574 break; 575 } 576 } 577 if (irq_flag || wake_irq_flag) 578 return IRQ_HANDLED; 579 else 580 return IRQ_NONE; 581 } 582 583 static irqreturn_t acp7x_irq_handler(int irq, void *dev_id) 584 { 585 struct snd_sof_dev *sdev = dev_id; 586 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 587 unsigned int base = desc->dsp_intr_base; 588 unsigned int val; 589 unsigned int ext_intr_stat; 590 int irq_flag = 0; 591 592 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 593 if (val & ACP_DSP_TO_HOST_IRQ) { 594 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 595 ACP_DSP_TO_HOST_IRQ); 596 return IRQ_WAKE_THREAD; 597 } 598 599 ext_intr_stat = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 600 if (ext_intr_stat & ACP_ERROR_IRQ_MASK) { 601 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 602 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 603 irq_flag = 1; 604 } 605 606 if (irq_flag) 607 return IRQ_HANDLED; 608 609 return IRQ_NONE; 610 } 611 612 static int acp_power_on(struct snd_sof_dev *sdev) 613 { 614 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 615 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 616 unsigned int base = desc->pgfsm_base; 617 unsigned int val; 618 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask; 619 bool use_masked_status = false; 620 int ret; 621 622 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); 623 624 if (val == ACP_POWERED_ON) 625 return 0; 626 627 switch (adata->pci_rev) { 628 case ACP_RN_PCI_ID: 629 case ACP_VANGOGH_PCI_ID: 630 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK; 631 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK; 632 break; 633 case ACP_RMB_PCI_ID: 634 case ACP63_PCI_ID: 635 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK; 636 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK; 637 break; 638 case ACP70_PCI_ID: 639 case ACP71_PCI_ID: 640 case ACP72_PCI_ID: 641 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK; 642 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK; 643 break; 644 case ACP7B_PCI_ID: 645 case ACP7F_PCI_ID: 646 acp_pgfsm_status_mask = ACP7X_PGFSM_STATUS_MASK; 647 acp_pgfsm_cntl_mask = ACP7X_PGFSM_CNTL_POWER_ON_MASK; 648 use_masked_status = true; 649 break; 650 default: 651 return -EINVAL; 652 } 653 654 if (val & acp_pgfsm_status_mask) 655 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, 656 acp_pgfsm_cntl_mask); 657 658 if (use_masked_status) 659 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, 660 base + PGFSM_STATUS_OFFSET, val, 661 !(val & acp_pgfsm_status_mask), 662 ACP_REG_POLL_INTERVAL, 663 ACP_REG_POLL_TIMEOUT_US); 664 else 665 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, 666 base + PGFSM_STATUS_OFFSET, val, 667 !val, ACP_REG_POLL_INTERVAL, 668 ACP_REG_POLL_TIMEOUT_US); 669 if (ret < 0) 670 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 671 672 return ret; 673 } 674 675 static int acp_reset(struct snd_sof_dev *sdev) 676 { 677 unsigned int val; 678 int ret; 679 680 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 681 682 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 683 val & ACP_SOFT_RESET_DONE_MASK, 684 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 685 if (ret < 0) { 686 dev_err(sdev->dev, "timeout asserting reset\n"); 687 return ret; 688 } 689 690 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 691 692 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 693 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 694 if (ret < 0) 695 dev_err(sdev->dev, "timeout in releasing reset\n"); 696 697 return ret; 698 } 699 700 static int acp_dsp_reset(struct snd_sof_dev *sdev) 701 { 702 unsigned int val; 703 int ret; 704 705 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); 706 707 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 708 val & ACP_DSP_SOFT_RESET_DONE_MASK, 709 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 710 if (ret < 0) { 711 dev_err(sdev->dev, "timeout asserting reset\n"); 712 return ret; 713 } 714 715 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); 716 717 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 718 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 719 if (ret < 0) 720 dev_err(sdev->dev, "timeout in releasing reset\n"); 721 722 return ret; 723 } 724 725 static int acp_init(struct snd_sof_dev *sdev) 726 { 727 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 728 struct acp_dev_data *acp_data; 729 unsigned int sdw0_wake_en, sdw1_wake_en; 730 int ret; 731 732 /* power on */ 733 acp_data = sdev->pdata->hw_pdata; 734 ret = acp_power_on(sdev); 735 if (ret) { 736 dev_err(sdev->dev, "ACP power on failed\n"); 737 return ret; 738 } 739 740 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); 741 /* Reset */ 742 ret = acp_reset(sdev); 743 if (ret) 744 return ret; 745 746 if (desc->acp_clkmux_sel) 747 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); 748 749 if (desc->ext_intr_enb) 750 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); 751 752 if (desc->ext_intr_cntl) 753 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); 754 755 switch (acp_data->pci_rev) { 756 case ACP70_PCI_ID: 757 case ACP71_PCI_ID: 758 case ACP72_PCI_ID: 759 sdw0_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN); 760 sdw1_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN); 761 if (sdw0_wake_en || sdw1_wake_en) 762 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, ACP70_EXTERNAL_INTR_CNTL1, 763 ACP70_SDW_HOST_WAKE_MASK, ACP70_SDW_HOST_WAKE_MASK); 764 765 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1); 766 break; 767 case ACP7B_PCI_ID: 768 case ACP7F_PCI_ID: 769 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_ZSC_DSP_CTRL, 0); 770 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_PME_EN, 1); 771 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP7X_DSP0_IDMA_ERROR_MASK, 772 ACP7X_IDMA_ERROR_MASK); 773 break; 774 } 775 return 0; 776 } 777 778 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 779 { 780 struct acp_dev_data *acp_data; 781 u32 sdw0_en, sdw1_en; 782 783 acp_data = sdev->pdata->hw_pdata; 784 if (!acp_data->sdw) 785 return false; 786 787 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN); 788 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN); 789 acp_data->sdw_en_stat = sdw0_en || sdw1_en; 790 return acp_data->sdw_en_stat; 791 } 792 793 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 794 { 795 struct acp_dev_data *acp_data; 796 int ret; 797 bool enable = false; 798 799 acp_data = sdev->pdata->hw_pdata; 800 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and 801 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will 802 * be reset to default values which will break the ClockStop Mode functionality. 803 * Add a condition check to apply DSP reset when SoundWire ClockStop mode 804 * is selected. For the rest of the scenarios, apply acp reset sequence. 805 */ 806 if (check_acp_sdw_enable_status(sdev)) 807 return acp_dsp_reset(sdev); 808 809 ret = acp_reset(sdev); 810 if (ret) { 811 dev_err(sdev->dev, "ACP Reset failed\n"); 812 return ret; 813 } 814 switch (acp_data->pci_rev) { 815 case ACP70_PCI_ID: 816 case ACP71_PCI_ID: 817 case ACP72_PCI_ID: 818 enable = true; 819 break; 820 default: 821 break; 822 } 823 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable); 824 825 return 0; 826 } 827 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, "SND_SOC_SOF_AMD_COMMON"); 828 829 int amd_sof_acp_resume(struct snd_sof_dev *sdev) 830 { 831 int ret; 832 struct acp_dev_data *acp_data; 833 834 acp_data = sdev->pdata->hw_pdata; 835 if (!acp_data->sdw_en_stat) { 836 ret = acp_init(sdev); 837 if (ret) { 838 dev_err(sdev->dev, "ACP Init failed\n"); 839 return ret; 840 } 841 return acp_memory_init(sdev); 842 } 843 switch (acp_data->pci_rev) { 844 case ACP70_PCI_ID: 845 case ACP71_PCI_ID: 846 case ACP72_PCI_ID: 847 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1); 848 break; 849 } 850 851 return acp_dsp_reset(sdev); 852 } 853 EXPORT_SYMBOL_NS(amd_sof_acp_resume, "SND_SOC_SOF_AMD_COMMON"); 854 855 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE) 856 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 857 { 858 struct acpi_device *sdw_dev; 859 struct acp_dev_data *acp_data; 860 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 861 862 if (!addr) 863 return -ENODEV; 864 865 acp_data = sdev->pdata->hw_pdata; 866 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0); 867 if (!sdw_dev) 868 return -ENODEV; 869 870 acp_data->info.handle = sdw_dev->handle; 871 acp_data->info.count = desc->sdw_max_link_count; 872 873 return amd_sdw_scan_controller(&acp_data->info); 874 } 875 876 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 877 { 878 struct acp_dev_data *acp_data; 879 struct sdw_amd_res sdw_res; 880 int ret; 881 882 acp_data = sdev->pdata->hw_pdata; 883 884 memset(&sdw_res, 0, sizeof(sdw_res)); 885 sdw_res.addr = acp_data->addr; 886 sdw_res.reg_range = acp_data->reg_range; 887 sdw_res.handle = acp_data->info.handle; 888 sdw_res.parent = sdev->dev; 889 sdw_res.dev = sdev->dev; 890 sdw_res.acp_lock = &acp_data->acp_lock; 891 sdw_res.count = acp_data->info.count; 892 sdw_res.link_mask = acp_data->info.link_mask; 893 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR]; 894 sdw_res.acp_rev = acp_data->pci_rev; 895 896 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); 897 if (ret) 898 dev_err(sdev->dev, "SoundWire probe failed\n"); 899 return ret; 900 } 901 902 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 903 { 904 struct acp_dev_data *acp_data; 905 906 acp_data = sdev->pdata->hw_pdata; 907 if (acp_data->sdw) 908 sdw_amd_exit(acp_data->sdw); 909 acp_data->sdw = NULL; 910 911 return 0; 912 } 913 914 #else 915 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 916 { 917 return 0; 918 } 919 920 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 921 { 922 return 0; 923 } 924 925 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 926 { 927 return 0; 928 } 929 #endif 930 931 int amd_sof_acp_probe(struct snd_sof_dev *sdev) 932 { 933 struct pci_dev *pci = to_pci_dev(sdev->dev); 934 struct acp_dev_data *adata; 935 const struct sof_amd_acp_desc *chip; 936 const struct dmi_system_id *dmi_id; 937 unsigned int addr; 938 int ret; 939 940 chip = get_chip_info(sdev->pdata); 941 if (!chip) { 942 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 943 return -EIO; 944 } 945 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 946 GFP_KERNEL); 947 if (!adata) 948 return -ENOMEM; 949 950 adata->dev = sdev; 951 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 952 PLATFORM_DEVID_NONE, NULL, 0); 953 if (IS_ERR(adata->dmic_dev)) { 954 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 955 return PTR_ERR(adata->dmic_dev); 956 } 957 addr = pci_resource_start(pci, ACP_DSP_BAR); 958 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 959 if (!sdev->bar[ACP_DSP_BAR]) { 960 dev_err(sdev->dev, "ioremap error\n"); 961 ret = -ENXIO; 962 goto unregister_dev; 963 } 964 965 pci_set_master(pci); 966 adata->addr = addr; 967 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 968 adata->pci_rev = pci->revision; 969 mutex_init(&adata->acp_lock); 970 sdev->pdata->hw_pdata = adata; 971 972 ret = acp_init(sdev); 973 if (ret < 0) 974 goto unregister_dev; 975 976 sdev->ipc_irq = pci->irq; 977 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 978 IRQF_SHARED, "AudioDSP", sdev); 979 if (ret < 0) { 980 dev_err(sdev->dev, "failed to register IRQ %d\n", 981 sdev->ipc_irq); 982 goto unregister_dev; 983 } 984 985 /* scan SoundWire capabilities exposed by DSDT */ 986 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr); 987 if (ret < 0) { 988 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 989 goto skip_soundwire; 990 } 991 ret = amd_sof_sdw_probe(sdev); 992 if (ret < 0) { 993 dev_err(sdev->dev, "error: SoundWire probe error\n"); 994 free_irq(sdev->ipc_irq, sdev); 995 return ret; 996 } 997 998 skip_soundwire: 999 sdev->dsp_box.offset = 0; 1000 sdev->dsp_box.size = BOX_SIZE_512; 1001 1002 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 1003 sdev->host_box.size = BOX_SIZE_512; 1004 1005 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 1006 sdev->debug_box.size = BOX_SIZE_1024; 1007 1008 dmi_id = dmi_first_match(acp_sof_quirk_table); 1009 if (dmi_id) { 1010 adata->quirks = dmi_id->driver_data; 1011 1012 if (adata->quirks->signed_fw_image) { 1013 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 1014 "sof-%s-code.bin", 1015 chip->name); 1016 if (!adata->fw_code_bin) { 1017 ret = -ENOMEM; 1018 goto free_ipc_irq; 1019 } 1020 1021 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 1022 "sof-%s-data.bin", 1023 chip->name); 1024 if (!adata->fw_data_bin) { 1025 ret = -ENOMEM; 1026 goto free_ipc_irq; 1027 } 1028 } 1029 } 1030 1031 adata->enable_fw_debug = enable_fw_debug; 1032 acp_memory_init(sdev); 1033 1034 acp_dsp_stream_init(sdev); 1035 1036 return 0; 1037 1038 free_ipc_irq: 1039 free_irq(sdev->ipc_irq, sdev); 1040 unregister_dev: 1041 platform_device_unregister(adata->dmic_dev); 1042 return ret; 1043 } 1044 EXPORT_SYMBOL_NS(amd_sof_acp_probe, "SND_SOC_SOF_AMD_COMMON"); 1045 1046 void amd_sof_acp_remove(struct snd_sof_dev *sdev) 1047 { 1048 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 1049 1050 if (adata->sdw) 1051 amd_sof_sdw_exit(sdev); 1052 1053 if (sdev->ipc_irq) 1054 free_irq(sdev->ipc_irq, sdev); 1055 1056 if (adata->dmic_dev) 1057 platform_device_unregister(adata->dmic_dev); 1058 1059 acp_reset(sdev); 1060 } 1061 EXPORT_SYMBOL_NS(amd_sof_acp_remove, "SND_SOC_SOF_AMD_COMMON"); 1062 1063 int amd_sof_acp7x_probe(struct snd_sof_dev *sdev) 1064 { 1065 struct pci_dev *pci = to_pci_dev(sdev->dev); 1066 struct acp_dev_data *adata; 1067 const struct sof_amd_acp_desc *chip; 1068 const union acpi_object *obj; 1069 struct acpi_device *adev; 1070 unsigned int addr; 1071 unsigned int irqflags; 1072 int ret; 1073 1074 chip = get_chip_info(sdev->pdata); 1075 if (!chip) { 1076 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 1077 return -EIO; 1078 } 1079 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), GFP_KERNEL); 1080 if (!adata) 1081 return -ENOMEM; 1082 1083 adata->dev = sdev; 1084 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1085 PLATFORM_DEVID_NONE, NULL, 0); 1086 if (IS_ERR(adata->dmic_dev)) { 1087 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 1088 return PTR_ERR(adata->dmic_dev); 1089 } 1090 1091 addr = pci_resource_start(pci, ACP_DSP_BAR); 1092 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 1093 if (!sdev->bar[ACP_DSP_BAR]) { 1094 dev_err(sdev->dev, "ioremap error\n"); 1095 ret = -ENXIO; 1096 goto unregister_dev; 1097 } 1098 1099 pci_set_master(pci); 1100 adata->addr = addr; 1101 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 1102 adata->pci_rev = pci->revision; 1103 mutex_init(&adata->acp_lock); 1104 sdev->pdata->hw_pdata = adata; 1105 1106 ret = acp_init(sdev); 1107 if (ret < 0) 1108 goto unregister_dev; 1109 1110 adev = ACPI_COMPANION(&pci->dev); 1111 1112 sdev->ipc_irq = pci->irq; 1113 irqflags = IRQF_SHARED; 1114 1115 ret = request_threaded_irq(pci->irq, acp7x_irq_handler, acp_irq_thread, 1116 irqflags, "AudioDSP", sdev); 1117 if (ret < 0) { 1118 dev_err(sdev->dev, "failed to register IRQ %d\n", sdev->ipc_irq); 1119 goto unregister_dev; 1120 } 1121 1122 if (adev) { 1123 if (!acpi_dev_get_property(adev, "acp-sof-signed-firmware-image", 1124 ACPI_TYPE_INTEGER, &obj)) 1125 adata->acp_sof_signed_firmware_image = obj->integer.value; 1126 } 1127 1128 sdev->dsp_box.offset = 0; 1129 sdev->dsp_box.size = BOX_SIZE_512; 1130 1131 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 1132 sdev->host_box.size = BOX_SIZE_512; 1133 1134 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 1135 sdev->debug_box.size = BOX_SIZE_1024; 1136 1137 if (adata->acp_sof_signed_firmware_image) { 1138 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 1139 "sof-%s-code.bin", chip->name); 1140 if (!adata->fw_code_bin) { 1141 ret = -ENOMEM; 1142 goto free_ipc_irq; 1143 } 1144 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 1145 "sof-%s-data.bin", chip->name); 1146 if (!adata->fw_data_bin) { 1147 ret = -ENOMEM; 1148 goto free_ipc_irq; 1149 } 1150 } 1151 1152 adata->enable_fw_debug = enable_fw_debug; 1153 acp_memory_init(sdev); 1154 acp_dsp_stream_init(sdev); 1155 1156 return 0; 1157 1158 free_ipc_irq: 1159 free_irq(sdev->ipc_irq, sdev); 1160 unregister_dev: 1161 platform_device_unregister(adata->dmic_dev); 1162 return ret; 1163 } 1164 EXPORT_SYMBOL_NS(amd_sof_acp7x_probe, "SND_SOC_SOF_AMD_COMMON"); 1165 1166 void amd_sof_acp7x_remove(struct snd_sof_dev *sdev) 1167 { 1168 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 1169 1170 if (sdev->ipc_irq) 1171 free_irq(sdev->ipc_irq, sdev); 1172 1173 if (adata->dmic_dev) 1174 platform_device_unregister(adata->dmic_dev); 1175 1176 acp_reset(sdev); 1177 } 1178 EXPORT_SYMBOL_NS(amd_sof_acp7x_remove, "SND_SOC_SOF_AMD_COMMON"); 1179 1180 MODULE_LICENSE("Dual BSD/GPL"); 1181 MODULE_DESCRIPTION("AMD ACP sof driver"); 1182 MODULE_IMPORT_NS("SOUNDWIRE_AMD_INIT"); 1183 MODULE_IMPORT_NS("SND_AMD_SOUNDWIRE_ACPI"); 1184