1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com> 9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 10 11 /* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 19 #include <asm/amd_node.h> 20 21 #include "../ops.h" 22 #include "acp.h" 23 #include "acp-dsp-offset.h" 24 25 static bool enable_fw_debug; 26 module_param(enable_fw_debug, bool, 0444); 27 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug"); 28 29 static struct acp_quirk_entry quirk_valve_galileo = { 30 .signed_fw_image = true, 31 .skip_iram_dram_size_mod = true, 32 .post_fw_run_delay = true, 33 }; 34 35 const struct dmi_system_id acp_sof_quirk_table[] = { 36 { 37 /* Steam Deck OLED device */ 38 .matches = { 39 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 40 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 41 }, 42 .driver_data = &quirk_valve_galileo, 43 }, 44 {} 45 }; 46 EXPORT_SYMBOL_GPL(acp_sof_quirk_table); 47 48 static void init_dma_descriptor(struct acp_dev_data *adata) 49 { 50 struct snd_sof_dev *sdev = adata->dev; 51 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 52 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 53 unsigned int addr; 54 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr; 55 56 addr = desc->sram_pte_offset + sdev->debug_box.offset + 57 offsetof(struct scratch_reg_conf, dma_desc); 58 59 switch (acp_data->pci_rev) { 60 case ACP70_PCI_ID: 61 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR; 62 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR; 63 break; 64 default: 65 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR; 66 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR; 67 } 68 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr); 69 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT); 70 } 71 72 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 73 struct dma_descriptor *dscr_info) 74 { 75 struct snd_sof_dev *sdev = adata->dev; 76 unsigned int offset; 77 78 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset + 79 offsetof(struct scratch_reg_conf, dma_desc) + 80 idx * sizeof(struct dma_descriptor); 81 82 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 85 } 86 87 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 88 unsigned int idx, unsigned int dscr_count) 89 { 90 struct snd_sof_dev *sdev = adata->dev; 91 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 92 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 93 unsigned int val, status; 94 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0; 95 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0; 96 int ret; 97 98 switch (acp_data->pci_rev) { 99 case ACP70_PCI_ID: 100 acp_dma_cntl_0 = ACP70_DMA_CNTL_0; 101 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS; 102 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0; 103 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0; 104 acp_dma_prio_0 = ACP70_DMA_PRIO_0; 105 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0; 106 break; 107 default: 108 acp_dma_cntl_0 = ACP_DMA_CNTL_0; 109 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS; 110 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0; 111 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0; 112 acp_dma_prio_0 = ACP_DMA_PRIO_0; 113 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0; 114 } 115 116 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), 117 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 118 119 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val, 120 val & (1 << ch), ACP_REG_POLL_INTERVAL, 121 ACP_REG_POLL_TIMEOUT_US); 122 if (ret < 0) { 123 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat); 124 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 + 125 ch * sizeof(u32)); 126 127 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 128 return ret; 129 } 130 131 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0); 132 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count); 133 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx); 134 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0); 135 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 136 137 return ret; 138 } 139 140 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 141 unsigned int dscr_count, struct dma_descriptor *dscr_info) 142 { 143 struct snd_sof_dev *sdev = adata->dev; 144 int ret; 145 u16 dscr; 146 147 if (!dscr_info || !dscr_count) 148 return -EINVAL; 149 150 for (dscr = 0; dscr < dscr_count; dscr++) 151 configure_dma_descriptor(adata, dscr, dscr_info++); 152 153 ret = config_dma_channel(adata, ch, 0, dscr_count); 154 if (ret < 0) 155 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 156 157 return ret; 158 } 159 160 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 161 unsigned int dest_addr, int dsp_data_size) 162 { 163 struct snd_sof_dev *sdev = adata->dev; 164 unsigned int desc_count, index; 165 int ret; 166 167 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 168 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 169 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 170 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 171 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 172 if (dsp_data_size < ACP_PAGE_SIZE) 173 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 174 } 175 176 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 177 if (ret) 178 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 179 180 /* Clear descriptor array */ 181 for (index = 0; index < desc_count; index++) 182 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 183 184 return ret; 185 } 186 187 /* 188 * psp_mbox_ready- function to poll ready bit of psp mbox 189 * @adata: acp device data 190 * @ack: bool variable to check ready bit status or psp ack 191 */ 192 193 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack) 194 { 195 struct snd_sof_dev *sdev = adata->dev; 196 int ret, data; 197 198 ret = read_poll_timeout(smn_read_register, data, data > 0 && data & MBOX_READY_MASK, 199 MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_114_REG); 200 201 if (!ret) 202 return 0; 203 204 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK); 205 206 if (ack) 207 return -ETIMEDOUT; 208 209 return -EBUSY; 210 } 211 212 /* 213 * psp_send_cmd - function to send psp command over mbox 214 * @adata: acp device data 215 * @cmd: non zero integer value for command type 216 */ 217 218 static int psp_send_cmd(struct acp_dev_data *adata, int cmd) 219 { 220 struct snd_sof_dev *sdev = adata->dev; 221 int ret; 222 u32 data; 223 224 if (!cmd) 225 return -EINVAL; 226 227 /* Get a non-zero Doorbell value from PSP */ 228 ret = read_poll_timeout(smn_read_register, data, data > 0, MBOX_DELAY_US, 229 ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_73_REG); 230 231 if (ret) { 232 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG); 233 return ret; 234 } 235 236 /* Check if PSP is ready for new command */ 237 ret = psp_mbox_ready(adata, 0); 238 if (ret) 239 return ret; 240 241 ret = amd_smn_write(0, MP0_C2PMSG_114_REG, cmd); 242 if (ret) 243 return ret; 244 245 /* Ring the Doorbell for PSP */ 246 ret = amd_smn_write(0, MP0_C2PMSG_73_REG, data); 247 if (ret) 248 return ret; 249 250 /* Check MBOX ready as PSP ack */ 251 ret = psp_mbox_ready(adata, 1); 252 253 return ret; 254 } 255 256 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 257 unsigned int start_addr, unsigned int dest_addr, 258 unsigned int image_length) 259 { 260 struct snd_sof_dev *sdev = adata->dev; 261 unsigned int tx_count, fw_qualifier, val; 262 int ret; 263 264 if (!image_addr) { 265 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 266 return -EINVAL; 267 } 268 269 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 270 if (val & ACP_SHA_RUN) { 271 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 272 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 273 val, val & ACP_SHA_RESET, 274 ACP_REG_POLL_INTERVAL, 275 ACP_REG_POLL_TIMEOUT_US); 276 if (ret < 0) { 277 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 278 return ret; 279 } 280 } 281 282 if (adata->quirks && adata->quirks->signed_fw_image) 283 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); 284 285 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 286 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 287 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 288 289 /* psp_send_cmd only required for vangogh platform */ 290 if (adata->pci_rev == ACP_VANGOGH_PCI_ID && 291 !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { 292 /* Modify IRAM and DRAM size */ 293 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); 294 if (ret) 295 return ret; 296 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); 297 if (ret) 298 return ret; 299 } 300 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 301 302 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 303 tx_count, tx_count == image_length, 304 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 305 if (ret < 0) { 306 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 307 return ret; 308 } 309 310 /* psp_send_cmd only required for renoir platform*/ 311 if (adata->pci_rev == ACP_RN_PCI_ID) { 312 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 313 if (ret) 314 return ret; 315 } 316 317 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 318 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, 319 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 320 if (ret < 0) { 321 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_PSP_ACK); 322 dev_err(sdev->dev, "PSP validation failed: fw_qualifier = %#x, ACP_SHA_PSP_ACK = %#x\n", 323 fw_qualifier, val); 324 return ret; 325 } 326 327 return 0; 328 } 329 330 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 331 { 332 struct snd_sof_dev *sdev = adata->dev; 333 unsigned int val; 334 unsigned int acp_dma_ch_sts; 335 int ret = 0; 336 337 switch (adata->pci_rev) { 338 case ACP70_PCI_ID: 339 acp_dma_ch_sts = ACP70_DMA_CH_STS; 340 break; 341 default: 342 acp_dma_ch_sts = ACP_DMA_CH_STS; 343 } 344 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 345 if (val & ACP_DMA_CH_RUN) { 346 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_sts, val, !val, 347 ACP_REG_POLL_INTERVAL, 348 ACP_DMA_COMPLETE_TIMEOUT_US); 349 if (ret < 0) 350 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 351 } 352 353 return ret; 354 } 355 356 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 357 { 358 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 359 int i, j; 360 361 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 362 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 363 } 364 365 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 366 { 367 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 368 int i, j; 369 370 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 371 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 372 } 373 374 static int acp_memory_init(struct snd_sof_dev *sdev) 375 { 376 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 377 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 378 379 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET, 380 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 381 init_dma_descriptor(adata); 382 383 return 0; 384 } 385 386 static irqreturn_t acp_irq_thread(int irq, void *context) 387 { 388 struct snd_sof_dev *sdev = context; 389 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 390 unsigned int count = ACP_HW_SEM_RETRY_COUNT; 391 392 spin_lock_irq(&sdev->ipc_lock); 393 /* Wait until acquired HW Semaphore lock or timeout */ 394 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count) 395 ; 396 spin_unlock_irq(&sdev->ipc_lock); 397 398 if (!count) { 399 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 400 return IRQ_NONE; 401 } 402 403 sof_ops(sdev)->irq_thread(irq, sdev); 404 /* Unlock or Release HW Semaphore */ 405 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); 406 407 return IRQ_HANDLED; 408 }; 409 410 static irqreturn_t acp_irq_handler(int irq, void *dev_id) 411 { 412 struct amd_sdw_manager *amd_manager; 413 struct snd_sof_dev *sdev = dev_id; 414 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 415 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 416 unsigned int base = desc->dsp_intr_base; 417 unsigned int val; 418 int irq_flag = 0; 419 420 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 421 if (val & ACP_DSP_TO_HOST_IRQ) { 422 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 423 ACP_DSP_TO_HOST_IRQ); 424 return IRQ_WAKE_THREAD; 425 } 426 427 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 428 if (val & ACP_SDW0_IRQ_MASK) { 429 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 430 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); 431 if (amd_manager) 432 schedule_work(&amd_manager->amd_sdw_irq_thread); 433 irq_flag = 1; 434 } 435 436 if (val & ACP_ERROR_IRQ_MASK) { 437 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 438 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); 439 /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */ 440 if (adata->pci_rev >= ACP_RMB_PCI_ID) 441 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); 442 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 443 irq_flag = 1; 444 } 445 446 if (desc->ext_intr_stat1) { 447 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 448 if (val & ACP_SDW1_IRQ_MASK) { 449 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 450 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 451 ACP_SDW1_IRQ_MASK); 452 if (amd_manager) 453 schedule_work(&amd_manager->amd_sdw_irq_thread); 454 irq_flag = 1; 455 } 456 } 457 if (irq_flag) 458 return IRQ_HANDLED; 459 else 460 return IRQ_NONE; 461 } 462 463 static int acp_power_on(struct snd_sof_dev *sdev) 464 { 465 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 466 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 467 unsigned int base = desc->pgfsm_base; 468 unsigned int val; 469 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask; 470 int ret; 471 472 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); 473 474 if (val == ACP_POWERED_ON) 475 return 0; 476 477 switch (adata->pci_rev) { 478 case ACP_RN_PCI_ID: 479 case ACP_VANGOGH_PCI_ID: 480 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK; 481 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK; 482 break; 483 case ACP_RMB_PCI_ID: 484 case ACP63_PCI_ID: 485 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK; 486 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK; 487 break; 488 case ACP70_PCI_ID: 489 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK; 490 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK; 491 break; 492 default: 493 return -EINVAL; 494 } 495 496 if (val & acp_pgfsm_status_mask) 497 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, 498 acp_pgfsm_cntl_mask); 499 500 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val, 501 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 502 if (ret < 0) 503 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 504 505 return ret; 506 } 507 508 static int acp_reset(struct snd_sof_dev *sdev) 509 { 510 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 511 unsigned int val; 512 int ret; 513 514 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 515 516 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 517 val & ACP_SOFT_RESET_DONE_MASK, 518 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 519 if (ret < 0) { 520 dev_err(sdev->dev, "timeout asserting reset\n"); 521 return ret; 522 } 523 524 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 525 526 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 527 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 528 if (ret < 0) 529 dev_err(sdev->dev, "timeout in releasing reset\n"); 530 531 if (desc->acp_clkmux_sel) 532 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); 533 534 if (desc->ext_intr_enb) 535 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); 536 537 if (desc->ext_intr_cntl) 538 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); 539 return ret; 540 } 541 542 static int acp_dsp_reset(struct snd_sof_dev *sdev) 543 { 544 unsigned int val; 545 int ret; 546 547 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); 548 549 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 550 val & ACP_DSP_SOFT_RESET_DONE_MASK, 551 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 552 if (ret < 0) { 553 dev_err(sdev->dev, "timeout asserting reset\n"); 554 return ret; 555 } 556 557 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); 558 559 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 560 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 561 if (ret < 0) 562 dev_err(sdev->dev, "timeout in releasing reset\n"); 563 564 return ret; 565 } 566 567 static int acp_init(struct snd_sof_dev *sdev) 568 { 569 int ret; 570 571 /* power on */ 572 ret = acp_power_on(sdev); 573 if (ret) { 574 dev_err(sdev->dev, "ACP power on failed\n"); 575 return ret; 576 } 577 578 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); 579 /* Reset */ 580 return acp_reset(sdev); 581 } 582 583 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 584 { 585 struct acp_dev_data *acp_data; 586 u32 sdw0_en, sdw1_en; 587 588 acp_data = sdev->pdata->hw_pdata; 589 if (!acp_data->sdw) 590 return false; 591 592 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN); 593 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN); 594 acp_data->sdw_en_stat = sdw0_en || sdw1_en; 595 return acp_data->sdw_en_stat; 596 } 597 598 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 599 { 600 struct acp_dev_data *acp_data; 601 int ret; 602 bool enable = false; 603 604 acp_data = sdev->pdata->hw_pdata; 605 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and 606 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will 607 * be reset to default values which will break the ClockStop Mode functionality. 608 * Add a condition check to apply DSP reset when SoundWire ClockStop mode 609 * is selected. For the rest of the scenarios, apply acp reset sequence. 610 */ 611 if (check_acp_sdw_enable_status(sdev)) 612 return acp_dsp_reset(sdev); 613 614 ret = acp_reset(sdev); 615 if (ret) { 616 dev_err(sdev->dev, "ACP Reset failed\n"); 617 return ret; 618 } 619 if (acp_data->pci_rev == ACP70_PCI_ID) 620 enable = true; 621 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable); 622 623 return 0; 624 } 625 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, "SND_SOC_SOF_AMD_COMMON"); 626 627 int amd_sof_acp_resume(struct snd_sof_dev *sdev) 628 { 629 int ret; 630 struct acp_dev_data *acp_data; 631 632 acp_data = sdev->pdata->hw_pdata; 633 if (!acp_data->sdw_en_stat) { 634 ret = acp_init(sdev); 635 if (ret) { 636 dev_err(sdev->dev, "ACP Init failed\n"); 637 return ret; 638 } 639 return acp_memory_init(sdev); 640 } else { 641 return acp_dsp_reset(sdev); 642 } 643 } 644 EXPORT_SYMBOL_NS(amd_sof_acp_resume, "SND_SOC_SOF_AMD_COMMON"); 645 646 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE) 647 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 648 { 649 struct acpi_device *sdw_dev; 650 struct acp_dev_data *acp_data; 651 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 652 653 if (!addr) 654 return -ENODEV; 655 656 acp_data = sdev->pdata->hw_pdata; 657 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0); 658 if (!sdw_dev) 659 return -ENODEV; 660 661 acp_data->info.handle = sdw_dev->handle; 662 acp_data->info.count = desc->sdw_max_link_count; 663 664 return amd_sdw_scan_controller(&acp_data->info); 665 } 666 667 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 668 { 669 struct acp_dev_data *acp_data; 670 struct sdw_amd_res sdw_res; 671 int ret; 672 673 acp_data = sdev->pdata->hw_pdata; 674 675 memset(&sdw_res, 0, sizeof(sdw_res)); 676 sdw_res.addr = acp_data->addr; 677 sdw_res.reg_range = acp_data->reg_range; 678 sdw_res.handle = acp_data->info.handle; 679 sdw_res.parent = sdev->dev; 680 sdw_res.dev = sdev->dev; 681 sdw_res.acp_lock = &acp_data->acp_lock; 682 sdw_res.count = acp_data->info.count; 683 sdw_res.link_mask = acp_data->info.link_mask; 684 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR]; 685 sdw_res.acp_rev = acp_data->pci_rev; 686 687 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); 688 if (ret) 689 dev_err(sdev->dev, "SoundWire probe failed\n"); 690 return ret; 691 } 692 693 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 694 { 695 struct acp_dev_data *acp_data; 696 697 acp_data = sdev->pdata->hw_pdata; 698 if (acp_data->sdw) 699 sdw_amd_exit(acp_data->sdw); 700 acp_data->sdw = NULL; 701 702 return 0; 703 } 704 705 #else 706 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 707 { 708 return 0; 709 } 710 711 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 712 { 713 return 0; 714 } 715 716 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 717 { 718 return 0; 719 } 720 #endif 721 722 int amd_sof_acp_probe(struct snd_sof_dev *sdev) 723 { 724 struct pci_dev *pci = to_pci_dev(sdev->dev); 725 struct acp_dev_data *adata; 726 const struct sof_amd_acp_desc *chip; 727 const struct dmi_system_id *dmi_id; 728 unsigned int addr; 729 int ret; 730 731 chip = get_chip_info(sdev->pdata); 732 if (!chip) { 733 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 734 return -EIO; 735 } 736 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 737 GFP_KERNEL); 738 if (!adata) 739 return -ENOMEM; 740 741 adata->dev = sdev; 742 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 743 PLATFORM_DEVID_NONE, NULL, 0); 744 if (IS_ERR(adata->dmic_dev)) { 745 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 746 return PTR_ERR(adata->dmic_dev); 747 } 748 addr = pci_resource_start(pci, ACP_DSP_BAR); 749 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 750 if (!sdev->bar[ACP_DSP_BAR]) { 751 dev_err(sdev->dev, "ioremap error\n"); 752 ret = -ENXIO; 753 goto unregister_dev; 754 } 755 756 pci_set_master(pci); 757 adata->addr = addr; 758 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 759 adata->pci_rev = pci->revision; 760 mutex_init(&adata->acp_lock); 761 sdev->pdata->hw_pdata = adata; 762 763 ret = acp_init(sdev); 764 if (ret < 0) 765 goto unregister_dev; 766 767 sdev->ipc_irq = pci->irq; 768 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 769 IRQF_SHARED, "AudioDSP", sdev); 770 if (ret < 0) { 771 dev_err(sdev->dev, "failed to register IRQ %d\n", 772 sdev->ipc_irq); 773 goto unregister_dev; 774 } 775 776 /* scan SoundWire capabilities exposed by DSDT */ 777 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr); 778 if (ret < 0) { 779 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 780 goto skip_soundwire; 781 } 782 ret = amd_sof_sdw_probe(sdev); 783 if (ret < 0) { 784 dev_err(sdev->dev, "error: SoundWire probe error\n"); 785 free_irq(sdev->ipc_irq, sdev); 786 return ret; 787 } 788 789 skip_soundwire: 790 sdev->dsp_box.offset = 0; 791 sdev->dsp_box.size = BOX_SIZE_512; 792 793 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 794 sdev->host_box.size = BOX_SIZE_512; 795 796 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 797 sdev->debug_box.size = BOX_SIZE_1024; 798 799 dmi_id = dmi_first_match(acp_sof_quirk_table); 800 if (dmi_id) { 801 adata->quirks = dmi_id->driver_data; 802 803 if (adata->quirks->signed_fw_image) { 804 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 805 "sof-%s-code.bin", 806 chip->name); 807 if (!adata->fw_code_bin) { 808 ret = -ENOMEM; 809 goto free_ipc_irq; 810 } 811 812 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 813 "sof-%s-data.bin", 814 chip->name); 815 if (!adata->fw_data_bin) { 816 ret = -ENOMEM; 817 goto free_ipc_irq; 818 } 819 } 820 } 821 822 adata->enable_fw_debug = enable_fw_debug; 823 acp_memory_init(sdev); 824 825 acp_dsp_stream_init(sdev); 826 827 return 0; 828 829 free_ipc_irq: 830 free_irq(sdev->ipc_irq, sdev); 831 unregister_dev: 832 platform_device_unregister(adata->dmic_dev); 833 return ret; 834 } 835 EXPORT_SYMBOL_NS(amd_sof_acp_probe, "SND_SOC_SOF_AMD_COMMON"); 836 837 void amd_sof_acp_remove(struct snd_sof_dev *sdev) 838 { 839 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 840 841 if (adata->sdw) 842 amd_sof_sdw_exit(sdev); 843 844 if (sdev->ipc_irq) 845 free_irq(sdev->ipc_irq, sdev); 846 847 if (adata->dmic_dev) 848 platform_device_unregister(adata->dmic_dev); 849 850 acp_reset(sdev); 851 } 852 EXPORT_SYMBOL_NS(amd_sof_acp_remove, "SND_SOC_SOF_AMD_COMMON"); 853 854 MODULE_LICENSE("Dual BSD/GPL"); 855 MODULE_DESCRIPTION("AMD ACP sof driver"); 856 MODULE_IMPORT_NS("SOUNDWIRE_AMD_INIT"); 857 MODULE_IMPORT_NS("SND_AMD_SOUNDWIRE_ACPI"); 858